JPH0463015A - Initial input stage circuit for semiconductor device - Google Patents

Abstract

PURPOSE:To nearly uniformalize the minimum value of high level of an input voltage or the maximum value of low level of it by varying the pattern of each input initial stage circuit corresponding to distance from a power source pad. CONSTITUTION:The input/output characteristic of the input initial stage circuit and the minimum value and the maximum value of high level and low level of the input voltage can be nearly uniformalized by using different layout patterns in the channel length(LPi), channel width(WPi), and resistance(rPi) with VCC wiring of the a P-channel transistor, and the channel length(LNi), channel width(WNi), and resistance(rNi) with VSS wiring of an N-channel transistor based on arrangement from a power source.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to the V+H+1Iin (input H
This invention relates to an input first-stage circuit that reduces variations between each pin in (minimum value) and (1) wax (input maximum value).

[Conventional technology]

This is a circuit diagram showing the relationship between power supply wiring resistances Rr, Rt, Rs, R4, a human-powered first-stage circuit (4), and an input pad (3).
Qp; , Qs; ;i = 1.2.3) and the resistance between each transistor and the 1i source wiring (rFi + rN
, ; i-1, 2, 3) use the same layout pattern, and the gate length of each transistor (Lrt,
Lsi; i = 1.2.3) or channel width <
Wpr, WNri i =1.2.3) were the same. FIG. 3 is a circuit diagram showing one input first stage circuit of a conventional semiconductor device having a plurality of input first stage circuits, in which the output (5) of the input first stage circuit (4) is changes. The fourth leap is a curve diagram showing the relationship between the input voltage and the output voltage in FIG. 3. This is the input/output characteristic of the inverter, including the ratio of ga (conductance) between the P-channel transistor and the N-chuffle transistor, the resistance (r□+'st) between each transistor and the power supply wiring, and the power supply band to each input first-stage circuit. resistance up to (R+, R
z, Rs, R,).

Qualitatively, the larger the gs+ of the N channel and the smaller the gm of the P channel, the closer the level of the output voltage to the input voltage becomes, and the characteristic curve in FIG. 4 changes from a broken line to a solid line. Here, the high level of the output voltage is 4.25V or higher,
Assuming normal operation at a low level of 0.75V or less, the maximum value of the input voltage low level (V + t) is 4.2V for the input first stage circuit with the characteristics shown by the solid line in Figure 4.
At an input voltage of 5V or more, it is 1.50V, and in the input first stage circuit with the characteristics shown by the broken line, it will be around 1.50V,
On the other hand, the minimum value of the high level (vlM) of the input voltage is 0.75 for the input first stage circuit with the characteristics shown by the solid line in Figure 4.
The input voltage below V is 1.75 V, and in the input first stage circuit having the characteristics shown by the broken line, it is around 2.1 V. In FIG. 1, when the input first stage circuit (4) has the same layout pattern, it is closest to VCC pad +11 and closest to V3.
In the input first stage circuit far from band (2), ■8.
Due to the resistance of the wiring (R3R,), the characteristic is shown by the broken line in FIG.
The input first stage circuit near the bat (2) has the characteristics shown by the solid line in FIG. 4 due to the resistance (R, , R2) of the wiring. The minimum value of the input voltage high level (VIM) and the maximum value of the input voltage low level (VIL) of the input first stage circuit will differ depending on the position from the power supply.

[Problem to be solved by the invention]

Conventional input first-stage circuits were configured as described above, and because they were configured with the same layout pattern without considering the distance from the power supply puff, the wiring resistance from the Wa puffed There is a problem that the minimum and maximum values of the high level (VIN) and low level (Vat) of the input voltage vary. FIG. 5 is a characteristic diagram showing the difference in the minimum and maximum values of V HH and V IL depending on the position of the input first stage circuit.

This invention was made to solve the above-mentioned problems, and it is possible to reduce variations in V , , (sin), and V + t (maX) depending on the layout position of the input first stage circuit. The purpose is to obtain an input first stage circuit for a semiconductor device.

[Means to solve the problem]

When there is a plurality of input first stage circuits of the semiconductor device according to the present invention, the input first stage circuit can be configured to have a P-channel transistor, an N-channel transistor, a power supply wiring and a P-channel transistor, or The resistance value between the N-channel transistors is adjusted.

C action] The input first stage circuit in this invention has the channel length (Lr;), channel width (Wr=),
Resistance with Vcc wiring (rr;), channel length of N-channel transistor (txt), channel width (WN+)
By using different layout patterns depending on the placement of the resistance (r,,i) with the Vss wiring from the power supply, the input/output characteristics of the input first stage circuit can be made almost uniform, and the input voltage is high and the health is low. Make the minimum and maximum values of health almost uniform.

〔Example〕

An embodiment of this invention will be described below with reference to the drawings. 1st
In the figure, the channel length (t
, r;), L from the side closest to the VCC pad.
FI>Lrz>Lr3. When adjusting by the channel width (WPi) of the P-channel transistor, set WPI < L pt < L R3 from the side closest to the VCC pad. When adjusting the resistance between the P-channel transistor and the VCC wiring, select r□>r from the side closest to the VCC pad.
, □ rr3. N-channel transistor> When adjusting by the channel length (L w+) of the transistor, ■LNI<LNI<LN3 from the side closest to the winnowing pad.

When adjusting by the chuffle radiation (W, 4.) of an N-channel transistor, WN, >
Let WN□>Wl. N-channel transistor and V8.
When adjusting by resistance between wirings, set r, ,<rN□<r, 13 from the side closest to the VCC pad. Of course, a combination of the above is also possible. The input/output characteristics of the input first-stage circuit are the gm and VC of the P-channel transistor.
The resistance including the wiring resistance up to the CCC pad P-channel transistor, gIll of the N-channel transistor, and V
It changes depending on the resistance including the wiring resistance up to the SSSS pad N-channel transistor. By changing the layout of the input first-stage circuit according to the distance from the power supply pad, it is possible to provide almost uniform input/output characteristics.

In addition, in the above embodiment, a case was explained in which an inverter (inversion circuit) composed of one P-channel transistor and one N-channel transistor was used as the input first-stage circuit, but the NOR circuit shown in FIG. 2 may also be used. . In this case as well, rPi+ rNi+ Qr+l+ Q
Adjust the channel length, channel width, and resistance of pzt + QNll. Q, □1=rN□, is not related to the input/output characteristics with respect to external input.

〔Effect of the invention〕

As described above, according to the present invention, the minimum value (V
+++, l1in) and the maximum value (V+, 1.may) of the low level (■1,) of the input voltage can be made almost uniform.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the relationship between the power supply band in a semiconductor device, the wiring resistance of the power supply, and each input first-stage circuit for explaining an embodiment of the present invention and a conventional one, and FIG. 2 is a circuit diagram of the present invention. A circuit side diagram of an input first stage circuit showing another embodiment of
Fig. 3 is a circuit diagram explaining each transistor in the conventional input first stage circuit and its channel length, Fig. 4M is a curve diagram showing the relationship between input voltage and output voltage of the input first stage circuit of Fig. 3, and Fig. 5 1 is a characteristic diagram showing the minimum value of the input high voltage and the maximum value of the input low voltage of each input first stage circuit in FIG. 1. FIG. In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 2 Heka's first null 4fl output T-Internal sound P eyes χm11-Input Figure 3

Claims (1)

[Claims] In an input first stage circuit that transmits an external input signal to an internal circuit of a semiconductor device, a P-channel transistor or an N-channel transistor is used depending on the distance from the power supply input pad to the input first stage circuit.
By changing the gate length and channel length of the channel transistor or the resistance between the transistor and the power supply line, variations in the minimum value of the H input voltage and the maximum value of the L input voltage between each input pin are reduced. Input first stage circuit of semiconductor device.