JPH0462736A - Latching relay driving circuit - Google Patents

Abstract

PURPOSE:To automatically restore from an erroneous operation by comparing a signal of an input terminal and a signal of an output terminal, so as to detect a mismatch in both signals when a contact should be closed between both terminals, and by providing detecting and restoring means for re-closing the contact corresponding to the detection output. CONSTITUTION:A latching relay 1 is in a reset (Rs) state from a set (St) state by a mechanical shock and so on, or the latching relay 1 is set in the (Rs) state by a control circuit 6. When the relay is erroneously operated to the St state, in the former case, the level of an output signal 23 as well as an output signal A of a comparator 2 are unstable, while, in the latter case, the signal level of an output signal B of the comparator 3 has no relationship with the output signals CH, CL, of comparators 9, 10. In the former case, the input of either AND circuits 15, or 17 becomes H, while in the latter case, L is output from NOR circuits 16, 12 through a NOT circuit 14 and AND circuits 11, 13, so as to actuate transistors 20, 21, and to electrify a set or reset coil L1, L2, and the relay 1 is restored from Rs to St, or from St to Rs, thereby. The erroneous operation can thus be automatically removed for restoration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a latching relay drive circuit that recovers from malfunction caused by mechanical shock or the like in a latching relay.

[Conventional technology]

As described in Japanese Patent Application Laid-open No. 64-62944, the conventional device is equipped with a reset switch, and when the reset switch is operated in the event of a malfunction, a circuit is added to supply a drive current to the reset coil. The method used was to restore the latching relay to its reset state.

[Problem to be solved by the invention]

In the conventional latching relay drive circuit described above, when a malfunction occurs due to mechanical shock, etc., the user must recognize the malfunction before operating the reset switch, and even if a malfunction occurs, the user does not notice it. There is a risk that you will use it without using it.

Moreover, even by operating the reset switch, only the recovery from the set state to the reset state can be performed, and there is no means for recovering from a malfunction to the reset side that occurs in the cent state.

SUMMARY OF THE INVENTION An object of the present invention is to provide a latching relay drive circuit that automatically recognizes malfunction of a latching relay and automatically restores the state to the state before the malfunction.

[Means to solve the problem]

A latching relay drive circuit according to the present invention is a latching relay drive circuit having an input terminal and at least one output terminal, in which a signal at the input terminal and a signal at the output terminal are compared, and a contact is established between the two terminals. The contact is provided with a detecting means for detecting a mismatch between the two signals when the contact should be closed, and a restoring means for closing the contact again according to the detection output of the detecting means.

Another latching relay drive circuit according to the present invention is as follows.

In a drive circuit for a latching relay, the circuit has a first output terminal connected to an input terminal when set, and a second output terminal connected to the input terminal when reset. a first detecting means for comparing the signals of the output terminals and detecting a mismatch between the two signals; a first restoring means for resetting the latching relay based on the detection output of the first detecting means; a second detection means for comparing the signal at the input terminal and the signal at the second output terminal to detect a mismatch between the two signals;
and second recovery means for resetting the latching relay in response to the detection output of the detection means.

Further, the latching relay according to the present invention has a first external terminal connected to the input terminal and a second external terminal connected to at least one of the output terminals, It is characterized by being configured integrally with a drive circuit.

Furthermore, the telephone according to the present invention is characterized in that it incorporates the other latching relay drive circuit.

[Effect]

When the contacts of the latching relay are closed, the signal at the input terminal and the signal at the output terminal match, that is, have the same waveform. Conversely, when the contact is open, both signals have different waveforms.

The detection means compares the signal at the input terminal and the signal at the output terminal of the latching relay, and detects that a mismatch between the two signals occurs when the contact of the latching relay should be closed. This mismatch means the occurrence of malfunction.

In this way, by constantly comparing the input and output signals of the latching relay, it becomes possible to automatically detect malfunctions of the latching relay caused by external factors such as mechanical shock.

When a malfunction is detected, the malfunction state can be restored to a normal state by driving the latching relay by the restoring means so as to return to the original state.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a latching relay drive circuit according to the present invention. In the figure, 1 is a latching relay that has a set coil L1 and a reset coil L2. 2 and 3 compare the set terminal side output signal 23 or the reset terminal side output signal 24 of the latching relay 1 with a reference voltage Ov, and compare it with a reference voltage Ov. “L” when the input is large
This is a comparator that outputs the level. 4 and 5 are pulse generation circuits, and in accordance with the output signal 25 from the control circuit 6, the pulse generation circuit 4 generates xi at the rise of the output signal 25, and the pulse generation circuit 5 generates xi at the fall of the output signal 25.
Generates a pulse at LI+ level.

The pulse generated by the pulse generating circuit S operates the transistor 20 via the NAND circuit 8, and energizes the set coil L1 of the latching relay 1 to set it. In addition, the pulses generated by the pulse generation circuit 4 are NAND
The transistor 21 is operated via the circuit 7, and the reset coil L2 of the latching relay 1 is energized to be in a reset state.

9 is a comparator that outputs at Ht+ level in response to an input higher than the reference voltage 6; 10 is a comparator that outputs "H" level in response to an input lower than reference voltage vL; the output signal C of these two comparators is ) I and CL are input signal 22 v
, 4 and ■, both are at the LL L I+ level.

In the configuration shown in FIG. 1, circuits 15 to 18 constitute a detection means that compares the input signal 22 and the set-side output signal 23 when the latching relay 1 is set, and detects a mismatch between the two. The pre-stage comparators 2.3 and 9.10 are for converting the input/output signals into binary values to facilitate comparison by the detection means. Regarding the comparators 9 and 10, the ground potential is not used as the reference signal, and the voltages V ) I, V C
, is used in order to prevent malfunctions in mismatch detection in the detection means, as will be described later. Similarly, circuit 1
1 to 14 constitute another inspection means that compares the input signal 22 and the reset side output signal 24 at the time of resetting the latching relay 1 and detects a mismatch between the two. Further, the comparators 2, 3, 9, and 10 in the previous stage function in the same manner for this detection means as they do for the aforementioned detection means.

FIG. 2 is a timing chart showing the operation of the latching relay immediate action circuit shown in FIG. In FIG. 1, a falling signal of an output signal 25 of a control circuit 6 causes a pulse generating circuit 5 to generate a pulse for a certain period of time, and a transistor 20 is operated via a NAND circuit 8. The setting coil L1 is energized by the operation of the transistor 2o, and the latching relay 1 is set to the set state. At this time,
The output signals 23 and 24 of the latching relay 1 are compared with the reference voltage Ov by comparators 2 and 3, respectively, and the output signal A
,B is output. The output signal A outputs an "L" level signal when the output signal 22 is higher than the reference voltage ov, and an "H" level signal when the output signal 22 is lower than the reference voltage o■. Since the output signal B is uncertain, it outputs a 'H' or II L' level.

On the other hand, the input signal 22 is input to comparators 9 and 10,
Output signal CM with reference voltage vH2vL, respectively.

Output C, . The output signal 25 of the control circuit 6 is N
The output signal A of the comparison circuit 2 is inputted to the AND circuit 15.17 via the OT circuit 19, and the output signal A of the comparison circuit 2 is input to the AND circuit 15 and
The signal is input to the AND circuit 17 via the OT circuit 18 . The output signal C6 is sent to the AND circuit 15, and the output signal CL
are respectively input to the AND circuit 17. The output signal of the AND circuit 15°17 is input to the NOR circuit 16,
The output signal 26 of this NOR circuit 16 is input to the NAND circuit 8. Reference voltage V of comparator 9 and comparator 10
If H and V are set to values larger than the variation in the threshold level with respect to the reference voltage ○V of the comparator 2, the output signal A of the comparator 2 and the output signal CH of the comparator 9 become #H#l level at the same time. Never. Similarly, the output signal A of the comparator 2 is inverted by the N○T circuit 18 and the comparator 1
The output signal CL of 0 also does not reach the ttH'' level at the same time.

Therefore, the AND circuits 15 and 17 do not output an "H" level, and the transistor 2o is not driven by the output of the NOR circuit 16.

When the latching relay 1 malfunctions from the set state to the reset state due to a mechanical shock or the like during normal operation as described above, the level of the output signal 23 becomes unstable.

Therefore, the output signal A of the comparator 2 also becomes unstable and has no correlation with the output signal CH of the comparator 9 and the output signal CL of the comparator 10.

Therefore, the inputs to either the AND circuit 15 or the AND circuit 17 are all at tL HI+ level, and the NO
When the R circuit 16 outputs "L7 level", the transistor 20 is driven again, energizing the set coil L1, and restoring the latching relay 1 from the reset state to the set state. When the latching relay 1 returns to the set state, The output signal A of the comparator 2 again becomes correlated with the output signal C8 of the comparator 9 and the output signal C of the comparator 10, and the AND circuit 15 or the AND circuit 17 becomes "H".
The level will no longer be output. Therefore, when the latching relay 1 recovers from the malfunctioning state, the drive of the transistor 20 is automatically canceled.

Similarly, when the output signal of the control circuit 6 becomes the it Hrt level and the latching relay 1 is set to the reset state, it malfunctions due to mechanical shock or the like and becomes the set state, the output signal B of the comparator 3 The level has no correlation with the output signal C■ of the comparator 9 and the output signal C,, of the comparator 10, and the II L I+ level is output from the NOR circuit 12 via the NOT circuit 14 and the AND circuit 11.13. 21 and reset coil L2.
is energized to restore the latching relay 1 from the set state to the reset state.

FIG. 3 shows the second latching relay drive circuit according to the present invention.
2 is a circuit diagram showing an embodiment of the present invention, in which the same components as those of the first embodiment shown in FIG. 1 are given the same reference numerals.

The second embodiment differs from the first embodiment in that the latching relay is of a single-winding coil type. The operation of the second embodiment will be explained with reference to the same figure.

The coil L1 of the latching relay 1 has a polarity, and the set state and reset state are determined by the polarity of the operating current. As in the first embodiment, the output of the NAND circuit 8 is “H”
When the level is reached, the transistors 20 and 21 are turned on, and current flows from the transistor 21 to the transistor 20 through the coil L1, resulting in a set state. Also,
When the output of the NAND circuit 7 reaches the LLH" level, the transistors 27 and 28 turn on, and the transistor 2
A current flows from the transistor 27 through the coil L1, resulting in a reset state. Even if a malfunction occurs due to a mechanical shock or the like, it can be recovered by the same operation as in the first embodiment.

FIG. 4 shows a third embodiment of the present invention, and is a circuit diagram of a latching relay incorporating the latching relay drive circuit of the first embodiment (or second embodiment). −
The area inside the dotted chain line is inside the latching relay, and the double circles are the terminals. According to this embodiment, all five drive circuits are built into the latching relay, so the external circuit only needs to directly input signal levels for setting and resetting.

〔Effect of the invention〕

As explained above, the present invention provides a means for detecting a malfunction caused by an external factor such as a mechanical shock by comparing the signals of the input terminals of a latching relay, and a means for restoring the malfunction by the means. It is possible to automatically recover from malfunctions without having to turn on the switch or turn on the power again.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment according to the present invention, FIG. 2 is a time chart explaining the operation of the circuit, and FIG. 3 is a circuit diagram of a second embodiment according to the present invention. FIG. 4 is a circuit diagram showing an embodiment of a latching relay incorporating a latching relay circuit according to the present invention. 1... Latching relay, 2, 3, 9. 10... Comparator, 4, 5... Pulse generation circuit, 6... Control circuit. No.! Akira Akira from darkness

Claims (1)

[Claims] 1. In a latching relay drive circuit having an input terminal and at least one output terminal, a signal at the input terminal and a signal at the output terminal are compared, and a contact is closed between the two terminals. 1. A latching relay drive circuit comprising: a detection means for detecting a mismatch between the two signals when the two signals should be present; and a restoration means for closing the contact again in response to a detection output of the detection means. 2. In a drive circuit for a latching relay having a first output terminal connected to an input terminal when set and a second output terminal connected to the input terminal when reset, the signal of the input terminal and the second output terminal are connected when set. a first detection means that compares the signals of the first output terminal and detects a mismatch between the two signals; a first recovery means that sets the latching relay again based on the detection output of the first detection means; and a reset. a second detection means for comparing the signal at the input terminal and the signal at the second output terminal to detect a mismatch between the two signals; A latching relay drive circuit characterized in that it is provided with a second recovery means for resetting. 3. It has a first external terminal connected to the input terminal and a second external terminal connected to at least one of the output terminals, and is integrated with the latching relay drive circuit according to claim 1 or 2. A latching relay characterized in that it is configured as follows. 4. A telephone set incorporating the latching relay drive circuit according to claim 2.