JPH0462600U - - Google Patents
Info
- Publication number
- JPH0462600U JPH0462600U JP10395490U JP10395490U JPH0462600U JP H0462600 U JPH0462600 U JP H0462600U JP 10395490 U JP10395490 U JP 10395490U JP 10395490 U JP10395490 U JP 10395490U JP H0462600 U JPH0462600 U JP H0462600U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- semiconductor memory
- external terminal
- internal signal
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の半導体メモリの回
路図、第２図は従来の半導体メモリの回路である
。
１……制御回路、２……ヒユーズセル、３，４
，６……インバータ、５……ＮＡＮＤゲート、７
……ＮＯＲゲート、８……高電圧検出回路、９…
…Ｐ型エンハンスメント・トランジスタ、１０…
…Ｎ型エンハンスメント・トランジスタ、Ａ，Ｂ
，Ｅ，Ｆ，Ｇ，Ｈ……内部信号、Ｃ，Ｄ……外部
端子。
FIG. 1 is a circuit diagram of a semiconductor memory according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor memory. 1... Control circuit, 2... Fuse cell, 3, 4
, 6... Inverter, 5... NAND gate, 7
...NOR gate, 8...High voltage detection circuit, 9...
...P-type enhancement transistor, 10...
...N-type enhancement transistor, A, B
, E, F, G, H...Internal signal, C, D...External terminal.
Claims (1)
手段として、フローテイングゲートを有し、かつ
消去可能で電気的書き込み可能な読み出し専用メ
モリセルを用いた半導体メモリにおいて、外部端
子に印加された通常電源電圧より高い電圧を検出
して内部信号のレベルを反転せしめる高電圧検出
回路を設け、反転した前記内部信号により前記ヒ
ユーズセルの情報を前記外部端子に出力する回路
を設けたことを特徴とする半導体メモリ。 In a semiconductor memory equipped with a redundant circuit and using an erasable and electrically writable read-only memory cell having a floating gate as a means for writing redundant cell switching information, the normal power supply voltage applied to an external terminal. A semiconductor memory comprising: a high voltage detection circuit that detects a higher voltage and inverts the level of an internal signal; and a circuit that outputs information of the fuse cell to the external terminal based on the inverted internal signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10395490U JPH0462600U (en) | 1990-10-01 | 1990-10-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10395490U JPH0462600U (en) | 1990-10-01 | 1990-10-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0462600U true JPH0462600U (en) | 1992-05-28 |
Family
ID=31849034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10395490U Pending JPH0462600U (en) | 1990-10-01 | 1990-10-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0462600U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01245497A (en) * | 1988-03-28 | 1989-09-29 | Nec Corp | Semiconductor memory |
-
1990
- 1990-10-01 JP JP10395490U patent/JPH0462600U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01245497A (en) * | 1988-03-28 | 1989-09-29 | Nec Corp | Semiconductor memory |
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