JPH0462594B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention has a plurality of musical tone generation channels,
The present invention relates to an electronic musical instrument that generates the musical tone of an operating key using a specified timbre in a channel assigned to the operating key.

[Prior art]

In conventional electronic musical instruments, when a tone specifying switch is switched while a key is being pressed, all the keys being pressed are turned off, then the tone is changed, and then the key is turned on again. Sound generation starts at the pitch corresponding to the key.

[Problems with conventional technology]

In this way, if you change the tone while a key is being held down, that key will be turned off and a new set tone will be added.For example, when changing the tone during a performance, conventionally the key would be completely turned off and then the new tone would be added. The timbre switch is turned on, but if the interval between notes is short, the timbre switch is often turned on before the key is turned off, causing the problem that unnecessary sounds are emitted.

On the other hand, the same tone is added to all the keys that are being pressed, so it is possible to create unique performances such as adding different tones to the keys that are pressed before and after switching the tone specifying switch. It is impossible to make chords sound.

[Purpose of the invention]

To provide an electronic musical instrument that can quickly switch timbres and can also produce chords with different timbres.

[Key points of the invention]

An electronic musical instrument having a plurality of musical tone generation channels, a tone specifying means for specifying a tone, and assigning the musical tone generating channel to a performance operator and generating a musical tone of the operation key with a tone specified by the tone specifying means. , storage means capable of storing timbres corresponding to the musical sound generation channels, and timbre information provided by the instruction means when a new performance operator is assigned to a predetermined channel, and a position of the storage means corresponding to the assigned channel. means for comparing the timbre information stored in the storage means with the timbre information stored in the storage means and, if they are different, transferring and setting the timbre information by the instruction means to a position corresponding to the assigned channel, corresponding to the assigned channel by the operation key of the storage means. and means for transmitting the tone color information stored at the location where the tone color information is stored to the tone generation channel to generate a tone based on the tone color information.

〔Example〕

Hereinafter, one embodiment will be described with reference to the drawings. FIG. 1 is an overall block diagram of an electronic musical instrument. In the figure,
1 is a CPU (central processing unit), and this CPU 1 has ROM (read only memory) 2, RAM (random access memory) 3,
The tone RAM 4 is connected to the keyboard 6 via the interface 5, the switch input section 8 via the interface 7, the register section 10 and the tone creation section 11 via the interface 9, and the tone register via the interface 12. The sections 13 are connected to each other. The timbre register section 13 is connected to a musical tone generating section 11, and a speaker 15 is connected to the musical tone generating section 11 via an amplifier 14.

The CPU 1 is a device that executes various operations such as arithmetic operations according to a control program stored in the ROM 2. The RAM 3 is a memory that temporarily stores intermediate result data and the like during processing by the CPU 1. The tone RAM 4 is arbitrarily set by various switches of the switch input section 8, which will be described later.
This is a memory that stores different types of tones. In addition to switches for setting tone colors, the switch input section 8 also includes switches for adding effects and rhythms.

The register unit 10 has various registers, which will be described later with reference to FIGS. is a register used by the CPU 1 for arithmetic processing to add the timbre to be switched this time.

On the other hand, the timbre register section 13 has registers such as TONE.Reg., which will be described later with reference to FIG. . In addition, the musical sound creation section 11 is assigned to each of the operation keys of the keyboard 6 to the musical sound creation system for eight channels formed by the arithmetic operations using the time-sharing processing method of the CPU 1, and creates musical sound signals for the operation keys. Then, a synthesized musical tone is emitted through the amplifier 14 and speaker 15.
In that case, the musical tone creation section 11 receives data from the tone color register 13 and adds a different tone to the musical tone of each operation key.

Next, the timbre-related switches on the switch input section 2 will be explained with reference to FIG. In the case of the electronic musical instrument of this embodiment, each data of 20 types of tones that are preset in the tone creation mode by the switch operation described below in the tone RAM 4 will be explained conceptually as shown in FIG. As can be seen from the memory structure of the timbre RAM 4, the timbre RAM 4 is composed of three types of envelope data: volume, harmonic component suppression, and pitch, and waveform data indicating a basic waveform. And the tone RAM4 in Figure 3
In the example of the memory configuration, there are n types of volume envelope data, m types of waveform envelope data, one type of pitch envelope data, and k types of basic waveforms, and registers with a corresponding capacity are prepared. Also, there are x types of tones (however,
In reality, x = 20), and consists of a total of four pointers for each envelope data and waveform data of the volume, harmonic component suppression, and pitch, respectively,
Each one is arbitrarily selected and stored by a switch operation described later.

So, returning to Figure 2, basic waveform memory selection
The SW16 is a switch for presetting the waveform data of the 10 types of basic waveforms in the case of k=10 described above into the corresponding registers (1-k) of the timbre RAM4.
This is a switch that specifies the basic waveform that is available. Switch 17A (11, 21, 31, 4
1, 51) designates one period in the first half, and switch 17B (12, 22, 32, 42, 52) designates one period in the latter half. Here, among the numbers written on the switches in the switches 17A and 17B, the numbers in the 10s are the waveforms shown in FIG. 4, 1, the numbers in the 20s are the waveforms shown in FIG. 4, and the numbers in the 30s are
The waveforms shown in FIG. 4, 40s, and 50s represent the waveforms shown in FIG. 4 and 5, respectively. switch 17c
is an octave modulation switch that alternately specifies the waveform specified in the first half and the waveform specified in the second half every cycle. This switch 17C
When is off, only the waveform specified in the first half is specified. The switch 16A is a write switch for writing the contents set by the switch 17 into the switch 16.

FIG. 4 shows the shapes and data of five types of waveforms that are the basis for forming the ten types of basic waveforms. Figure 5 shows the data structure of the basic waveform data. The upper 3 bits of WAVE FORM are the 3 bit data set in the waveform of Figure 4, and the next 3 bits of OCT.
The 3-bit data shown in FIG. 4 is also set for MODULATION WAVE RORM. The next 1-bit data is data indicating the presence or absence of OCT.MODULATION. Furthermore, 1 bit of the LSB is not used,
becomes invalid.

Returning to Figure 2, volume envelope memory selection
SW 18, harmonic component suppression envelope memory selection SW 19, and pitch envelope memory selection switch 20 are used for the cases where n=10, m=10, and l=10, respectively. This is a switch for specifying registers 1 to n, 1 to m, and 1 to l that store each pitch envelope data.The actual operation is first to adjust the volume, harmonic component suppression, and registers 1 to 1 to store each pitch envelope data. Specify any one of switches 18 to 19, and then select the rate value designation slide SW 21 and level value designation slide SW 21, which are provided eight times each corresponding to the eight steps 0 to 7.
22. Operate the switch at each step of the sustain point designation SW 23, and then turn on the write SW 24, 25, or 26 corresponding to the currently selected envelope of volume, harmonic component suppression, or pitch.

FIG. 6 shows the volume, harmonic component suppression,
This shows the waveform of each envelope of pitch, and slides W21 to W21 according to the eight steps mentioned above.
It consists of eight folded line parts arbitrarily formed by the operation of 23. The height of the end of the broken line part of the envelope (indicated by points A to H in the figure) is the level value, and the distance between each level value is expressed by the rate value (the slope of the broken line part). Ru.

FIG. 7 shows the data structure of the envelope data. In the figure, A to H represent data storage units corresponding to points A to H at the end of the envelope waveform in FIG. 6, each having a capacity of 18 bits. has. The MSB of the upper 8 bits stores 1-bit data indicating the direction of the rate (direction of inclination of the broken line), and becomes the direction when it is "0" and the direction when it is "1". The next 7 bits are rate value data, and the MSB of the lower 8 bits is 1-bit data representing sustain information, and when it is "1" it indicates that the sustain point has been reached. “0”
indicates that it is not the sustain point. The next 7-bit data indicates the level value. In addition, the direction of the rate mentioned above, (〓, 〓)
is automatically determined from the change in level value.

Figure 8 shows an example of an actual envelope, and Figure 9 shows an example of an actual envelope.
The figure shows an example of actual data of the envelope shown in FIG. In this example, point F is the sustain point, and the envelope level of this key remains constant until the next key-off.
At this time, the value of point G becomes irrelevant.

Returning to FIG. 2 again, the timbre memory selection switch 27 is a switch that specifies the registers (registers 1 to x in FIG. 3) in the timbre RAM 4 that store data for 20 types of timbres in the case of x=20. and
In the tone creation mode, the data of the tone currently selected by any combination of the switches 16 to 20 (waveform data of the basic waveform, volume, harmonic component suppression, pitch envelope, 4 numbers for data) are written
It is written into the registers 1 to X when SW28 is turned on. In the normal performance mode, simply by turning on any one of the timbre memory selection SWs 27, the four pointers of the corresponding timbre data are read out from the registers 1 to x, and then based on these pointers, as shown in FIG. 1-n, 1-m, 1-l, 1
The data is read from each register of ~k and processed.

Next, the specific configuration of the musical tone creating section 11 will be explained with reference to FIG. In the figure, 30 is an interface through which data input/output is performed with the CPU 1, and the CPU 1, via this interface 30, controls a volume envelope generation circuit 31, a harmonic component suppression envelope generation circuit 32, and a pitch envelope generation circuit 33. For each envelope data consisting of the rate value, level value, etc. shown in Fig. 7 (as shown in Fig. 10, each data is divided into AMP Ramp, WAVE Ramp, Freg,
(also called Ramp). Each envelope circuit 31, 32, 33 calculates the current value from the rate value and level value, and applies it to the corresponding EXP. (exponential) ROM 34, band limit circuit 35, frequency Give to ROM36. Furthermore, when the current value reaches the rate value at that time, each envelope circuit 31, 32, 33 generates an interrupt signal INT, sends it to the CPU 1 via the interface 30, and executes the next steps 0 to 7 (points). Data AMP Ramp for A to H),
Requests the output of WAVE Ramp and Freq.Ramp (however, in the case of the sustain point mentioned above, the interrupt signal INT is not output).

Freq.ROM36 is pitch envelope circuit 33
Frequency information (phase angle information) according to the output from
FI is generated and applied to the band limit circuit 35 and phase generator 37. This phase generator 37 accumulates the phase angle information FI and provides the resulting data to a division circuit 38. Furthermore, the band limit circuit 35 is a waveform envelope circuit 3.
Based on the output from 2 and the phase angle information, generation of aliasing distortion based on the sampling theorem is prevented, and the output is given to the division circuit 38. Furthermore, this division circuit 3
8 includes an interface 30 and a waveform generation circuit 3.
Predetermined waveform type selection data sent by the CPU 1 via the CPU 9 is also given. Then, the division circuit 38 performs division processing on each output from the phase generator 37, band limit circuit 35, and waveform generation circuit 39, accesses the wave generator 40 according to the resulting data, and outputs the waveform data. is generated and sent to the multiplication circuit 41. In addition,
As for the specific structure of the division circuit 38, it is possible to use an implementation circuit already proposed by the present applicant, for example, described in the patent specification of Japanese Patent Application No. 57-221266.

The multiplication circuit 41 also receives control data read from the EXP.ROM, multiplies the waveform data and control data, and provides the resultant data to the accumulation circuit 42. Every time this accumulation circuit 42 accumulates the result data for 8 channels, it supplies the accumulated data to the DA converter via a DACI/F (DA converter interface) 43. Musical tones will be emitted from the speaker 15.

Next, as shown in FIG. 11, the volume, harmonic component suppression, and pitch envelope circuits 31, 32, 3
The configuration of No. 3 will be specifically explained. Note that since these circuits 31 to 33 have the same configuration, the circuit shown in FIG. 11 is assumed to be, for example, the volume envelope circuit 31.

In the figure, 45 is a shift register group in which 8 stages of shift registers with a capacity of 8 bits are connected in parallel, and the level value sent from the CPU 1 via the transfer gate 46 is input in parallel to the first stage. . Note that the shift register group 45
When configured by connecting shift registers in 8 stages in parallel, this corresponds to the existence of a musical tone creation system for 8 channels. The same applies to other shift register groups to be described later.

The level value inputted to the first stage of the shift register group 45 is then shifted to the subsequent stage and output from the eighth stage, and is passed through the transfer gate 47 to the first stage.
It is returned to the stage and is applied to the B input terminal of the comparator 48. Also, transfer gate 46
is controlled to open and close by applying a preset signal sent from the CPU 1 to its gate via an inverter 49, and the opening and closing of the transfer gate 47 is controlled by applying the preset signal directly to the gate. Note that this preset signal is at the "0" level only when the level value is sent.

On the other hand, the rate value is input to the transfer gate group 50 via the transfer gate 51, and when outputted from the shift register group 50, it is returned to the shift register group 50 via the transfer gate 52, and the rate value is input to the adder/subtracter 53. It is also given to the B input terminal of . The opening and closing of the transfer gates 51 and 52 are controlled by applying the preset signal to the gates through the inverter 54 or directly.

Furthermore, the output data (current value) from itself is input back to the shift register group 55 via the transfer gate 56 and is also applied to the A input terminal of the adder/subtractor 53 . The result data ANS1 of the adder/subtractor 53 is applied to the shift register group 55 via the transfer gate 57, and is also applied to the A input terminal 48 of the comparator 48. The control terminal of the adder/subtractor 53
The MSB data of the rate value output from the shift register group 50 (data indicating the direction of the rate) is input to SUB as a subtraction command.
When this subtraction command is "1", subtraction is performed, and when it is "0", addition is performed. Further, the data of the MSB of the rate value is input as a comparison method selection command to the control terminal ≧ of the comparator 48, and when this comparison method selection command is “1”, if A≦B, the comparison result of the comparator 48 is input. Signal ANS2 is “1”, A
>B is “0”, on the other hand, the comparison method selection command is “0”
In this case, the comparison result signal ANS2 becomes "1" if A≧B, and "0" if A<B. The comparison result signal ANS2 is then transferred to the transfer gate 56,
57 are applied to the gates directly or via an inverter 58 to control opening and closing, and are also applied to one end of a NAND gate 59. On the other hand, the MSB data (sustain information) of the level value output from the shift register group 45 is inverted input to the other end of the NAND gate 59, and the output of the NAND gate 59 is the interrupt signal.
Sent to CPU1 as INT.

Next, various registers will be explained with reference to FIG. FIG. 12 shows a register provided in the register section 10. Each register OP in the diagram
Both Reg, WP Reg, and FP Reg are used for indexing each line (pointing to a channel).

That is, OP Reg holds the value of the channel where the key-on occurred first. WP Reg is a work pointer for a key assigner (this key assigner is a circuit that assigns channels to operation keys through arithmetic processing by the CPU 1). FP Reg retains the value of an empty line when it is found. FOUNDF Reg when there is an empty line
Each data is TRUE, RALSE when absent.
Set by CPU1.

Next, each register in FIG.
is a register within. 8-bit capacity NL Reg
(New Line status) indicates that the 0th bit, 1st bit, ..., 7th bit are channel 0, channel 1, respectively.
Channels, . . . , correspond to 7 channels, and when a new channel is designated, the corresponding bit is turned on. The contents of each bit are turned OFF each time the check of all lines is completed, and the contents of this NL Reg are transferred to the corresponding bits of OL Reg, which will be explained next, in preparation for the next channel assignment.

The OL Reg has a capacity of 8 bits and corresponds to channels 0 to 7 from the lower side, and the NL Reg
The data is then transferred and stored.

TL Reg (Trigger Line Status) similarly has a capacity of 8 bits and corresponds to channels 0 to 7 from the lower side. It turns ON when the key is on and turns OFF when the key is off.

The SC Reg (Scale Code) has eight registers with a capacity of 8 bits, and each register corresponds to channels 0 to 7 and stores the scale code of the key assigned to that channel.

CSC Reg (Current Scale Code) is set to the scale code of the key currently being played.

FIG. 12 shows a register provided in the timbre register section 13 in which data is set according to data from the timbre RAM 4 during performance.

That is, the number corresponding to the tone color memory selection switch 27 is stored in TONE Reg. This number is used as a pointer to the tone data. Further, when the tone color memory selection switch 27 is switched, the data is updated immediately.

LTONE Reg consists of eight registers, and each register corresponds to channels 0 to 7, respectively. When a new channel is designated, the contents of the TONE Reg are copied to the line corresponding to this channel. That is, LTONE Reg indicates the current tone color number of each channel.

Next, taking as an example the case where the musical score shown in FIG. 17 is played, its operation will be explained with reference to the flowcharts shown in FIGS. 13 to 16. It is assumed that 20 types of tones have already been preset in the tone RAM 4 in the tone creation mode.

When the power switch is turned on and performance begins, initialization processing of steps S ₁ and S ₂ , initialization (1) and initialization 2, is performed. In the initialization 1, the flowchart shown in FIG. 15 is executed, and first, the TL, NL, and
The OL register is set to all channels OFF (step _I1 ). SC Reg is then cleared (step I ₂ ) or OP Reg is reset (step I ₃ ).

Next, a predetermined default value (initial value: for example, 1 and the tone is set to piano) is set for TONE Reg (step I ₅ ), and then
A default value of 1 is also set for all channels of LTONE Reg (step I ₆ ). Then, default tone color generation is performed (step _I6 ).

In initialization 2, the data of the NL register is transferred to the OL register according to the flow shown in FIG. 16 (step N ₁ ), and then each channel of the NL register is set to OFF (step N ₂ ).

Next, the CPU 1 outputs a key common signal for the keyboard 6 to the bus line BUS to perform key scanning (step S ₄ ). Therefore, the output of each key on the keyboard 6 is written to the RAM 3 via the interface 5 (step S ₄ ), and the CPU 1 determines whether or not a key has been pressed from the data content in the RAM 3 (step S ₅ ).
If it is determined that no key has been pressed, it is determined whether all keys have been scanned (step S ₆ ), and if "NO", the process returns to step S ₃ and steps S ₃ to _{S 6} are repeated until all keys have been scanned. .

It is assumed that the key of the first musical tone _E3 of the musical score shown in FIG. 17 is turned on. It is assumed that the tone color of the harp is set by turning on any one of the tone color memory selection switches 27 other than 1 (for example, 2) before starting the performance.

As a result, key-on of _E3 is determined in step _S5 , and the scale code _E3 is set in the CSC register (step _S12 ). Also, data “0” of the OP register is set to the WP register,
It becomes "0" (step _S13 ). Also FOUND Reg
Data “FALSE” is written to (step
_S14 ). Then, the process of step _S15 is performed to obtain the contents of SC Reg using the data "0" of WP Reg as an index, and since this is the first key-on, there is no scale code for the 0 channel of SC Reg.

Next, proceed to step _S16 , check the match between the CSC Reg data "E ₃ " and the SC Reg data "0",
Since the answer is “NO”, proceed to step S ₂₆ and complete the WP Reg
Look at the contents of TL Reg (channel 0 is currently “OFF”) using the contents “0” as the index, and
It is determined whether the data of Reg is ON or not (step _S27 ). However, since it is "NO", proceed to step _S20 and check whether the data of FOUND Reg is "FALSE", but since it is "YES",
Proceed to step _S21 and set data "TRUE" in FOUNDF Reg. Also, data "0" of WP Reg is set to FP Reg (step _S22 ).

Next, WP Reg is incremented to "1" and it is determined whether the result is "8" or not, but since it is not, the process proceeds to the next step _S24 with the value of WP Reg remaining at "1". In addition, WP Reg is "8"
When this happens, the process is automatically reset to "0".

Next, in step _S24 , WP Reg data “1”
It is judged whether or not it matches the data “0” that OP Reg has, and since it is “NO”, the next step is
Proceeding to _S15 , from then on, until the WP register is incremented in step _S23 and the current data "1" in the WPP register is returned to "0",
The steps S ₂₄ , S ₁₅ , S ₁₆ , S ₂₆ , S ₂₇ , S ₂₀ ,
S ₂₁ , S ₂₂ , S ₂₃ , and S ₂₄ are repeated seven times. That is, during this period, the value of WP Reg changes as 1, 2, 3, . . . , 7, 0. When the value becomes "0" and a match of data "0" in OP Reg is detected in step _S24 , the process proceeds to step _S25 , where it is determined whether FOUNDF Reg is TRUE or not. However, the answer is “YES”.
Proceeding to step _S28 , data ``E <sub>3</sub> '' of CSC Reg is stored in SC Reg using the content ``0'' of FP Reg as an index. That is, scale code E ₃ keyed on channel 0 of SC Reg has been registered.

Next, NL Reg is turned "ON" using the contents of FP Reg (channel 0) as an index, and data "ON" is set in the 0th channel of NL Reg (step _S29 ). Then, TL using the contents of FP Reg (channel 0) as an index.
Set "ON" to the 0 channel of Reg (step _S30 ). Furthermore, OP Reg data “0”
Transfer to Reg (step S ₃₁ ). This is an update of the key assigner's search start line pointer.

Next, the contents of LTONE Reg are examined using the contents "0" of FP Reg as an index. That is, data "1" of channel 0 of LTONE Reg in the tone register section 13 is detected, and since this is different from data "2" of TONE Reg (step S ₃₃ ), the process advances to step S _{34 and the data ``1''} of channel 0 of LTONE Reg is detected. The tone number "2" is written to the channel (step _S34 ).
Next, the harp tone color data corresponding to the number "2" is sent to the tone generation section (step _S35 ). Next, proceed to step _S36 and enter the CSC Reg data “E ₃ ”.
The key code is sent to the musical sound creation section 11, a key-on instruction is given, and the musical sound creation system of the first channel starts creating a musical sound, and the harp sound of _E3 begins to sound (step _S37 ).

Next, the process returns to step _S6 , and if the key scan is not completed, steps _S6 , _S3 , and _S4 are executed, and the process returns to step _S5 , and the _E3 key remains on. , proceed to step S ₁₂ and CSC
Data "E ₃ " is set in Reg again. and
Data “0” is set in WP Reg (step
S ₁₃ ), and also data "FALSE" in FOUNDF Reg
is set. And in step S ₁₅ , SC
The 0 channel of Reg is seen and the key code E ₃ is obtained. Then, in step _S16 , both match "E ₃ ", so proceed to step _S17 , and set TL Reg to 0.
Channel data "ON" is obtained. Then, in step _S18 , it is determined whether the data is "ON" or not, and since it is "YHS", the process proceeds to step _S19 , and uses the content of WP Reg as "0" as an index.
Set the 0 channel of NL Reg to “ON”.

Next, the process proceeds to step _S6 , and if the process proceeds to step _S7 , the tone color switch, that is, the CPU 1 outputs a key common signal to the switch input section 8. Next, in step _S9 , it is determined whether or not there has been a change in the tone memory selection switch 27. If there has been no change, the process proceeds to step _S11 , where the key-off process is performed, and then step _S2.
Return to

On the other hand, if you leave the E ₃ key on and switch the tone to piano as shown in Figure 13, the step
The determination is made in step _S9 , and the process proceeds to step _S10 , where the piano tone number "1" is set in TONE Reg in the tone color register section 13. Then _{, the process returns to step S2 via} step S11.

Thereafter, when the key for the second musical tone _G3 is turned on, the key code " _G3 " is set in CSC Reg at step _S12 through steps _S2 to _S5 . Then, in step _S13 , data "0" in OP Reg is transferred to WP Reg, and "FALSE" is set in FOUNDF Reg (step _S14 ).

Next, step _S15 sets the WP Reg data to “0”.
Since the data "E ₃ " of channel 0 of SC Reg is obtained from , the result is "NO" in step _S16 , and the process proceeds to step _S26 , where data "0" of WP Reg is obtained.
Data "ON" of channel 0 of TL Reg is obtained, and in step _S27 it becomes "YES" again, and the process proceeds to step _S23 , where WP Reg is incremented by 1 and becomes "1". Since WP Reg does not match OP Reg ("0") (step _S24 ), the process advances to step _S15 , and data "0" for one channel of SC Reg is obtained. Then, in step S ₁₆ , it is "NO",
Return to step _S26 .

Next, TL Reg 1 channel data “OFF”
is detected, the result in step _S27 is "NO", and the process proceeds to step _S20 , and this time also, the result is "YES", and in step _S21 , FOUND is set to "TRUE".

Next, "1" of WP Reg is transferred to FP Reg, and then in step _S23 , WP Reg becomes "2".

Below, steps S ₁₅ , S ₁₆ , S ₂₆ , S ₂₇ , S ₂₀ , S ₂₃ and ₂₄ are repeated until WP Reg returns to "0", and when the value of WP Reg becomes "0" “YES” is obtained in step S ₂₅ via step S ₂₄ , and the step
Proceed to S ₂₈ .

In step _S28 , key code _G3 is set in one channel of the SC register, and then "ON" is set in one channel of NL Reg (step _S29 ). Next, "1" is set in OP Reg (step _S31 ), data "1" of one channel of LTONE Reg is detected ( _S32 ), and TONE
It is determined that there is a match with the data "1" in Rege (step _S23 ), and the tone number "1" remains unchanged in the first channel of LTONE Reg, and the piano tone corresponding to tone number "1" is displayed. The data is sent to the musical tone creation section 11 (step _S35 ), and the CSC
The G ₃ key code in Reg is also sent to the musical tone creation section 11, and a key-on instruction is issued (step _S36 ,
_S37 ). Then return to step _S6 . Therefore, the second key turned on is emitted with the piano tone for which the tone color was changed immediately before. On the other hand, the first on-key emits sound with the initially set harp tone, and as a result, the two keys each emit sound with different tones.

The following is the same, and to explain it according to the score in Figure 17, if you switch the tone to pipe organ while keeping the E ₃ and G ₃ keys on, then turn on the third key of C ₄ , this C The pipe organ tone is applied to the _4th key, so each of the three keys will be sounded with a different tone.

To briefly explain the key-off process in step _S11 with reference to FIG.
Reg is cleared (step F ₁ ) and then this WP
TL Reg, OL using Reg value as index
Obtain the contents of Reg, NL Reg (step F ₂ ), and TL
Determine whether Reg, NL Reg, and OL Reg are ON. If TL Reg is ON and other Regs are not ON, the process advances to step _F6 , where TL Reg is turned OFF and a key-off command is output (step _F7 ). Then in step _F8 WP Reg
is incremented, and if the value is not ``8'', the process returns to step <sub>F2</sub> and the processes of steps <sub>F2</sub> to <sub>F8</sub> are executed again, and if the value is ``8'', the key-off process for eight channels is completed.

〔Effect of the invention〕

As explained above, the present invention provides a unique musical instrument that can easily switch tones even in fast-tempo songs and easily add different tones to each on-key. , if you use it in the intro of a song, etc.
This allows for extremely interesting and highly effective performances.

[Brief explanation of drawings]

FIG. 1 is an overall circuit diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a switch configuration diagram of the key input section, FIG. 3 is a memory configuration diagram of the tone RAM 4, and FIG.
The figure is a waveform diagram of the basic waveform, Figure 5 is a data configuration diagram of the waveform data of the basic waveform, Figure 6 is an envelope waveform diagram, Figure 7 is a data configuration diagram, and Figure 8 is a specific example of the envelope waveform. 9 is a diagram of the data contents, FIG. 10 is a specific circuit diagram of the musical tone creation section 11, and FIG. 11 is a circuit diagram of the envelope circuit.
Figures 12 to 3 are diagrams explaining various registers, Figures 13 to 16 are flowcharts,
FIG. 17 is a diagram showing a musical score. 1...CPU, 2...ROM, 3...RAM, 4...Tone
RAM, 6...Keyboard, 8...Switch input section, 10...
Register section, 11... musical tone creation section, 14... amplifier,
15...Speaker.

Claims (1)

[Claims] 1. Having a plurality of musical sound generation channels, based on pitch information for determining the pitch of a musical sound assigned to this musical sound generation channel and timbre control information for determining the timbre of a musical sound. In an electronic musical instrument, the electronic musical instrument is equipped with a musical tone generating means for generating a musical tone, and a tone color specifying means for specifying a tone of a musical tone, and each time pitch information is newly inputted, this pitch information is transmitted to one of the plurality of musical tone generation channels. a pitch assigning means for allocating pitch information to a musical tone generation channel to which the newly inputted pitch information is assigned; and a tone color assigning means, wherein when the tone color information is switched by the tone color specifying means, only the tone of the musical tone to be produced based on pitch information inputted thereafter becomes the tone specified by the tone color information. An electronic musical instrument featuring