JPH0461353A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To dry etch with a mask having the same size as a metal layer mask and to greatly reduce the area of a source electrode by dry etching a semiconductor substrate having large thickness in depth of half of the substrate with the mask, and burying a part side-etched with the mask with a resist layer. CONSTITUTION:After the thickness of the rear surface of a GaAs semi-insulating board 11 is reduced, an Au layer of a metal layer 13 is vapor-deposited, a region to be formed with a via hole is etched to form an opening 13a. Then, a via hole 15 is formed by etching through the opening 13a by RIE 14. Thereafter, it is covered with a resist layer 16. Only the resist layer is selectively etched by RIE 17, and after the layer 13 is exposed, the layer 16 is vertically etched with the layer 13 as a mask. Further, a via hole 25 reaching a source electrode 12 is formed by the RIE 14. Subsequently, the layers 13, 16 are removed to form via holes 15, 25 of a forwardly tapered shape.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular a field effect transistor (hereinafter abbreviated as FET) for ultra-high frequencies and an FET.
Monolithic microwave IC (MMIC:
The present invention relates to a method for manufacturing a semiconductor device, which is an improved method for forming via holes in a semiconductor substrate for nonolithic microwave ICs.

(Conventional technique v#) In high frequency power FETs, wide band, wide gain,
In order to increase the frequency, it is important to reduce the source inductance, and this is achieved by directly grounding the source electrode using a Pi7 hole (through hole). Therefore, the shape of the Pi7 hole is important to connect the back metal layer to the front electrode with good coverage.
A forward tapered shape is required.

Furthermore, in FETs, it is important to increase the degree of device integration, and the smaller the area of the source electrode that forms the pi-7 hole, the more freedom in device design can be increased.

However, isotropic dry etching is required to form a forward-tapered pie hole, and as a result of this, the opening diameter on the source electrode side increases, making it impossible to reduce the area of the source electrode. It is necessary to establish a technology that allows both the tapered Pi-7 hole and the reduction in the area of the source electrode to be achieved.

The manufacturing process of a conventional FET having a via hole will be described below with reference to process cross-sectional views shown in FIGS. 2(a) to 2(c).

First, a photoresist layer (hereinafter referred to as resist layer) 3 is patterned on the back surface of the semiconductor substrate 1 in alignment with the source electrode 2 formed on the surface of the semiconductor substrate 1 (FIG. 2(a)). Next, using the resist layer 3 as a mask, reactive ion etching (hereinafter referred to as RIE) 4 is performed isotropically up to the source electrode 2 on the surface (FIG. 2(b)). 3 is removed to complete the via hole 5 (FIG. 2(C)).As shown in this figure, the dimensions of the via hole portion are also shown when the thickness of the semiconductor substrate 1 is 150 mm. , the opening diameter of the resist layer 3 is 60-
To illustrate the case of φ, the opening diameter on the back side of the pie 7 hole 5 is 170. φ, diameter on the source electrode side 100. It can be formed to approximately φ, and the area of the source electrode needs to be at least 150Ia×150μ when alignment accuracy is taken into consideration.

(Problem to be solved by the invention!g) In the conventional manufacturing process described above, as illustrated in FIG. Moreover, the diameter on the source electrode side cannot be avoided to be about 273 times the diameter of the opening on the back side. Therefore, the size of the source electrode cannot be made smaller than the diameter of the opening on the back side.

Element design regarding source electrodes is constrained by the thickness of the semiconductor substrate. Moreover, since the substrate is thick, it is not possible to form via holes of the same size with good reproducibility.

The present invention has been made to eliminate the above-mentioned drawbacks.
An object of the present invention is to provide a method for manufacturing an FET that can determine the size of a source electrode without being influenced by the thickness of a semiconductor substrate, and can form a via hole in a forward tapered shape with good reproducibility in accordance with the size.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes the steps of depositing a metal layer on the back surface of a semiconductor substrate and forming a metal layer pattern that exposes a region of the substrate where a through hole is to be formed. a step of isotropically dry etching the semiconductor substrate using the metal layer pattern as a mask to form an opening; a step of depositing a resist layer on the back surface of the semiconductor substrate and filling the opening with the resist; etching the resist layer in the opening of the semiconductor substrate in a direction perpendicular to the semiconductor substrate using the metal layer pattern as a mask, and etching the resist layer so that the semiconductor substrate is left in the side-etched portion. The method is characterized in that it includes the steps of isotropically dry etching the semiconductor substrate using the resist layer as a mask to make openings reach the surface electrodes of the semiconductor substrate, and removing the metal layer and the resist layer.

(Function) The present invention performs isotropic dry etching on a semiconductor substrate using a metal layer mask to a depth of half the thickness of the substrate, and then etches the side-etched portion using a resist layer mask. By filling the semiconductor substrate with the metal layer, dry etching can be performed isotropically on a semiconductor substrate whose thickness has been reduced to half using a mask of the same size as the metal layer mask. As a result, the diameter of the opening on the source electrode side of the via pole can be suppressed to the same size as etching a semiconductor substrate with half the thickness of the substrate, and moreover, it is possible to form a forward-tapered pie-7 hole. Furthermore, the area of the source electrode can be significantly reduced compared to conventional manufacturing methods.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

Figures 1 (a) to (f) show gallium arsenide (G) on a semiconductor substrate.
All of them are cross-sectional views showing a method for manufacturing an FET using aAs) in order of steps.

As shown in FIG. 1 (8), a GaAs semi-insulating substrate 11
The back side of the board is lapped and chemically polished to reduce the substrate thickness to 15mm.
After thinning the GaAs substrate to 04, a metal layer 1 is formed on the back surface of the GaAs substrate
An Au layer of No. 3 was deposited to a thickness of 2,000 layers, and the area where the via hole was to be formed was etched to form an opening 13a.

Next, through the opening 13a of the metal layer 13, RI
Isotropically etching the GaAs substrate 11 using E14; 80. Form a depth of Pi 7 hole 15 (
Figure 1(b)).

Next, as shown in FIG. 1(C), the pie 7 hole 15
The resist layer 16 is coated so that the area is completely buried. Here, LP-10 (trade name: Hoechst Co., Ltd. 11) was used to form the resist layer 16, and its film thickness was set to 30-.

Next, the resist layer 16 is etched by RIE 17 under the conditions that only the resist layer can be selectively etched, and after the metal layer 13 is undulated, the metal M1 is etched.
3 serves as a mask to vertically etch the resist layer 16 in the via hole 15 (FIG. 1(d)).
.

Next, the GaAs substrate 11 is isotropically etched by RIE 14 through the gate part 13a of the metal layer 13 to form a Pi7 hole 25 which is a through hole reaching the source electrode 12 formed on the surface of the substrate. do(
FIG. 1(e)), where the via hole 25 is made of metal [1
The resist layer 16 left on the sidewalls under 3 serves as a mask so that the via hole 15 does not become larger than the previously formed via hole 15.

Next, the metal layer 13 and the resist layer 16 are removed to complete a forward tapered pie hole Is, 25 as shown in FIG. 1(f).

〔Effect of the invention〕

As described above, according to the method for manufacturing a semiconductor device according to the present invention, a semiconductor substrate having a large substrate thickness is isotropically dry-etched using a metal layer mask to, for example, half the depth of the substrate, and then the metal layer is etched. By filling the side-etched portion of the mask with a resist layer, the thickness of the semiconductor substrate can be halved and dry etching can be performed isotropically using a mask of the same size as the metal layer mask.

According to the via hole forming method according to the present invention, FIG.
As is clear by comparing the dimensions shown in f) with the conventional dimensions shown in FIG. Since the size of the source electrode can be kept to the same level, the area of the source electrode can be significantly reduced compared to the conventional manufacturing method. Furthermore, since a forward tapered via hole can be formed with good reproducibility, the back metal layer can be connected to the source electrode with good coverage.

[Brief explanation of drawings]

FIGS. 1(8) to (f) are cross-sectional views showing the FET manufacturing method according to the present invention in the order of steps, and FIGS. 2(a) to (e)
) are sectional views showing the conventional FET manufacturing method in the order of steps. 11... Semiconductor substrate, 12... Source electrode, 13
...Metal layer. 16...Resist layer, I5.25... Via hole. 14.17...RIE. Agent Patent Attorney Norifu Ogo 17: (L di λ meter layer) RIE ll: Muzen Miseizaka 13: Food eyebrows 12: So λt, f &131; Ashic I capital 14: RIE 15: Bia Tsume- ) Shikuki no 2) (vI>1) 1: Ushi J Jun 1- and 3: L-jis 1-layer sauce t & 4: RIE 5: Bahia nail-1

Claims (1)

[Claims] A step of depositing a metal layer on the back surface of the semiconductor substrate and forming a metal layer pattern to expose a region of the substrate where a through hole is to be formed, and isotropically dry etching the semiconductor substrate using the metal layer pattern as a mask. a step of providing an opening;
A step of depositing a resist layer on the back surface of the semiconductor substrate and filling the resist into the opening, and etching the resist layer in the opening of the semiconductor substrate in a direction perpendicular to the semiconductor substrate using the metal layer pattern as a mask. and isotropically dry etching the semiconductor substrate using the resist layer left on the side-etched portion of the semiconductor substrate as a mask to form openings that reach the surface electrodes of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the steps of removing the metal layer and the resist layer.