JP3036451B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to the formation of an offset gate formed by offsetting a gate electrode to a source electrode side in a Schottky barrier gate field effect transistor or the like operating in an ultra-high frequency band. About the method.

[0002]

2. Description of the Related Art Gallium arsenide field effect transistors (GaAs FETs) and heterojunction field effect transistors (HJ FETs) for microwave band amplification have high performance characteristics in an ultra-high frequency band regardless of whether they are for low noise or power. Because it can be realized, it is widely used for communication equipment and radar equipment.

In such gallium arsenide field effect transistors and heterojunction field effect transistors, a groove called a recess is provided between a drain electrode and a source electrode in order to improve performance and increase electric breakdown strength.
In many cases, a structure in which a gate electrode is provided in the recess is employed.

In this field effect transistor having a recess structure, the series resistance Rs between the source electrode and the gate electrode strongly depends on the distance between the recess end on the source electrode side and the gate electrode. Particularly, in a low-noise element operated with a small current, the two-dimensional electron gas concentration immediately below the gate electrode is limited to a low level, and the series resistance Rs below the bottom of the recess increases to such an extent that the noise performance of the element is largely influenced. Therefore, in terms of device design, it is desirable that the distance between the recess end on the source electrode side and the gate electrode is as short as possible.

On the other hand, the distance between the recess end on the drain electrode side and the gate electrode is related to the capacitance Cgd of the gate electrode to the drain electrode. When the distance is small, the Cgd increases. Occurs.

When the reverse breakdown voltage and the drain breakdown voltage of the gate electrode are improved and used as a high-output FET, the distance between the recess end on the drain electrode side and the gate electrode is determined by the distance between the recess end on the source electrode side and the gate electrode. It is desirable to design larger. For this reason, in such a field-effect transistor, studies are being made on an offset gate structure in which a gate electrode is provided at an offset position in a recess.

FIGS. 10A to 10D are cross-sectional views in the order of steps for explaining a conventional method of forming an offset gate.

First, as shown in FIG.
The insulating film 13 is provided on the GaAs substrate 11 provided with the semiconductor substrate 2.
Next, after the resist layer 14 is applied, the resist layer 14 is patterned by an optical exposure method so as to have an opening width corresponding to the width of a recess called a so-called recess.

Next, as shown in FIG. 10B, after the insulating film 13 is selectively removed by etching using the resist layer as a mask, the resist layer is removed and the insulating film 13 is used as a mask. The operation layer 12 is etched to form a recess region 15. Further, in order to form the gate electrode in the recess so as to be offset toward the source, FIG.
As shown in (1), the resist layer 16 is positioned and patterned. At this time, since the gate length is limited to about 0.5 μm when using a normal optical exposure method, it is necessary to use a means such as electron beam exposure to form a finer pattern.

After an opening is formed in the resist layer 16, a gate metal is vapor-deposited and removed together with the resist layer 16 with methyl ethyl ketone (this step and method are referred to as lift-off), and as shown in FIG. Electrode 17
To form

In this case, in order to offset the gate electrode to the source side, the alignment accuracy is ± 0.02 μm.
High precision of about m is required.

The alignment accuracy of both an i-line stepper used for optical exposure and an electron beam exposure machine used for electron beam exposure is about ± 0.05 μm, which is insufficient for forming an offset gate with high accuracy.

In order to solve the problem in the conventional example shown in FIG. 10, the following two methods have been proposed.

A conventional example described in JP-A-3-293732 will be described with reference to FIG.

First, as shown in FIG.
After forming the channel layer 22 and the n ⁺ -type conductive layer 23 on the entire surface of the substrate 21, a pair of ohmic electrodes 24 are formed by AuGe.

Subsequently, as shown in FIG. 11B, an insulating film 25 of SiO ₂ is formed on the entire ohmic electrode 24 and the channel layer 23 by a sputtering method.

Next, as shown in FIG. 11C, a part of the insulating film 25 is thinned by an etching method. At this time, the step caused by the partial thinning of the insulating film 25 substantially corresponds to the position of the gate electrode described later.

Next, as shown in FIG. 11D, a resist layer 26 used for forming a gate is finally formed. Here, the resist layer 26 is patterned into a gate electrode pattern, and the gate electrode formation region is formed so as to include the step formed in the insulating film 25 in the previous step.

By loading the patterned resist layer 26 as described above and subjecting the substrate 1 to a reactive ion etching process, as shown in FIG.
The insulating film 25 is partially removed. At this time, first, the insulating film 25 is vertically etched in a region where the resist layer 26 is deficient, and subsequently, the insulating film 25 located below the resist layer 26 is partially etched by side etching. Select a condition.

As described above, since the insulating film 25 is partially thinned, by performing such etching, the side etching of the insulating film 25 proceeds rapidly in the thinned region, and the resist layer The etching region of the insulating film 25 is formed asymmetrically with respect to the defective region 26.

Next, by using the insulating film 25 asymmetrically etched as described above as a mask, the n ⁺ -type conductive layer 23 and the channel layer 22 are etched to obtain a structure shown in FIG.
As shown in (F), a recess 28 corresponding to the defective region of the insulating film 25 is formed.

Finally, a gate electrode 27 is formed by a lift-off method using the resist layer 26, as shown in FIG. At this time, as described above, the resist layer 2
Since the recess is formed asymmetrically with respect to the defect region 6, the formed gate electrode 27 is
Within, it is formed offset.

Next, a conventional example described in JP-A-5-218090 will be described with reference to FIG.

As shown in FIG. 12A, the second insulating film 3 is formed on the GaAs substrate 31 after the operation layer 32 is formed.
3. A resist layer 35 is formed by patterning an opening for forming the second insulating film 34 and the first recess region. As the first insulating film 33, an SiO ₂ film is used, and as the second insulating film 34, an SiN film is used.

Next, as shown in FIG. 12B, the second insulating film (SiN) 34 and the first insulating film (SiO ₂ ) 33 are etched using the resist layer 35 as a mask. Is formed.

Next, as shown in FIG. 12C, after the resist layer 35 is removed, an opening is formed in the resist layer 37 so as to be offset in one direction (normally, on the source electrode side) of the first recess region. Is provided. Thereafter, a second recess region 38 is formed so as to obtain a desired pinch-off voltage or drain saturation current.

Next, as shown in FIG. 12D, after the first insulating film (SiO ₂ ) 33 is side-etched by wet etching, a gate metal is deposited, and a lift-off method is performed using the resist layer 37. Thus, a gate electrode 39 is formed.

The gate length by this method is the same as that of the resist layer 3
7 and the second insulating film (SiN) 34.

[0029]

The prior art shown in FIG. 11 proposed to solve the problem of the prior art shown in FIG. 10 which is insufficient to form an offset gate with high accuracy. The expected position depends on the alignment accuracy of the exposure process, and the offset amount in the wafer varies, resulting in poor reproducibility.

Further, in the conventional example shown in FIG. 12, since the resist is applied to the first recess region, there is a concern that the bottom surface of the recess is contaminated.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of realizing an offset structure with high accuracy and high reproducibility without causing contamination of the bottom surface of the recess.

[0032]

According to a method of manufacturing a semiconductor device of the present invention, an insulating film is deposited on a surface portion of an active region of a semiconductor substrate and then patterned.
Forming a first insulating film defining the recess width on the substrate, and depositing a second insulating film having a lower etching rate than the first insulating film on a predetermined etching means; , at least a portion of said first insulating film
Forming a resist layer having a first opening exposing the second insulating film so as to be present on an edge ; and etching the second insulating film using the resist layer as a mask. And the first
Forming a second opening in which the edge of the insulating film is exposed in the second insulating film; and forming the second opening on the second insulating film including the inside of the second opening, the same as the second insulating film. Depositing a third type of insulating film, and etching the insulating layer composed of the third and second insulating films from above to the bottom by etching.
And an edge portion of the insulating film and a portion adjacent to the edge portion.
Etching removed so that the insulating layer remains exposed
To, and forming a third opening, and removing all of the first insulating film by etching through said third opening, exposed by removing the first insulating film Forming a recess by etching the active region, forming a gate metal forming a Schottky junction with the active region, and forming a gate electrode by shaping the gate metal by predetermined etching means. And a step of performing

In this case, the first insulating film is a silicon oxide film, the second and third insulating films are silicon nitride films,
The means for etching the insulating film may be wet etching using an HF-based etchant, and the means for etching the second and third insulating films may be dry etching using, for example, a CF ₄ / H ₂ -based gas.

As the second and third insulating films, low dielectric constant films based on a cyclic olefin resin or the like are used.
As the etching means, for example, dry etching using a CF ₄ / H ₂ gas can be used.

Thus, the gate electrode can be provided offset from the recess.

As described above, in the present invention, steps are provided by providing different types of insulating films below the resist layer provided with the gate openings. The offset gate is formed by making the substrate surface exposed to the gate opening asymmetric by utilizing the difference in the etching rate of the two types of insulating films by the predetermined etching means.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIGS. 1 to 9 are views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps, wherein (A) is a plan view and (B) is (A). ) Is a sectional view taken along a cutting line XX ′ and viewed in the direction of the arrow.

First, as shown in FIGS. 1A and 1B, an n-type GaAs is formed on the surface of an active region of a semi-insulating GaAs substrate 1.
A GaAs substrate 1 on which an operation layer 2 made of an s layer is formed is prepared. Next, by plasma CVD, for example, a thickness of 50
The first insulating film 3 is deposited by depositing a first insulating film 3 such as a silicon oxide film having a thickness of 10 nm and performing wet etching with an HF-based etchant using the resist layer as a mask.
Are partially arranged on the operation layer 2.

Next, as shown in FIGS. 2A and 2B, a second insulating film 4 such as a silicon nitride film having a thickness of 300 nm is deposited by a CVD method.

Next, as shown in FIGS. 3A and 3B, a resist layer 5 is formed on the second insulating film, and an opening (first opening) is formed in the resist layer 5 by i-line exposure. Form 5A. At this time, the resist opening 5A is made to overlap the edge of the first insulating film 3 partially arranged above the operation layer region.

Next, as shown in FIGS. 4A and 4B, the second insulating film 4 is anisotropically dry-etched with, for example, a CF ₄ / H ₂ -based gas to form a gate opening 4A (second Opening)
To form At this time, the amount of etching of the second insulating film 4 is such that the second insulating film 4 is not completely removed and the first insulating film 3 is not removed.
Is set to, for example, 330 nm so as to be exposed.

Next, as shown in FIGS. 5A and 5B, on the second insulating film 4 including the formed gate opening 4A,
A third insulating film 6 (in this case, silicon nitride film) of the same type as the second insulating film 4 is deposited, for example, to a thickness of 300 nm.

Next, as shown in FIGS. 6A and 6B,
The insulating film composed of the second and third insulating films is formed by
A gate opening (third opening) 6A having a forward tapered shape, which is a head portion of the gate electrode, is formed by anisotropic dry etching with F ₄ / H ₂ gas. At this time, at this time, the amount of etching the second and third insulating films 4 and 6 and side wall processing is such that the second and third insulating films 4 and 6 are not completely removed and the inside of the gate opening 6A is not removed. Is used to expose a portion (tip) of the first insulating film 3.

The gate length is determined by the edge of the first insulating film 3 disposed on the operation layer 2 and the edge of the gate opening 6A formed by side wall processing.

Next, as shown in FIGS. 7A and 7B,
All of the first insulating film 3 such as a silicon oxide film partially disposed on the operation layer 2 is disposed thereon.
A second and third insulating film 4 such as a silicon nitride film,
If the etching rate is higher than that of No. 6, it is removed by wet etching using an etchant such as HF to form a cavity 3A.

Next, as shown in FIGS. 8A and 8B,
The active layer 2 exposed in the cavity 3A due to the removal of the first insulating film 3 is etched with a mixed solution of H ₂ SO ₄ and H ₂ O ₂ to form a recess 7.

Thereafter, a first gate metal 8 for forming a Schottky junction with the operation layer 2 is deposited by a sputtering method, and then a second gate metal 9 is deposited by a sputtering method.

Next, as shown in FIGS. 9A and 9B,
A resist layer is patterned at a position where a gate head is to be formed, and first and second gate metals are processed by ion milling or the like to form a gate electrode 10.

The relative positional relationship between the joint surface of the gate electrode 10 on the source side and the recess 7 is determined not by the alignment accuracy of the exposure apparatus but by the etching amount for forming the recess 7. The accuracy of the etching is ±
It is about 0.02 μm, and the accuracy is higher than that of the method of alignment (the conventional example in FIG. 10).

Next, a second embodiment will be described.

The difference from the first embodiment will be described. A low dielectric constant film based on a cyclic olefin resin, for example, 300 nm in thickness, as second and third insulating films for forming openings by dry etching of CF ₄ / H ₂ gas
Is formed, and a gate opening is provided by photolithography. Subsequent steps are the same as in the first embodiment. The polyolefin film is not etched by the HF-based etchant.

Since the dielectric constant of the polyolefin film is 2.4, which is lower than the dielectric constant of silicon nitride of 5, the gate parasitic capacitance can be further reduced. For example, the FE according to the first embodiment can be used.
If the cutoff frequency of T is 20 GHz, 30 GHz
Can be improved to the extent.

The above description has been made on the case where GaAs is used as the semiconductor material. However, F such as InP or InGaAs is used.
It is clear that the present invention can be applied to those using other semiconductor materials used as ET.

[0055]

As described above, according to the present invention, different types of insulating films are provided below a resist layer provided with a gate opening to provide steps, and two types of insulating films are formed by predetermined etching means. An offset gate is formed by making the substrate surface exposed to the gate opening asymmetric by utilizing the difference in the etching rate. The relative positional relationship between the junction surface of the gate electrode on the source side and the recess 7 is determined not by the alignment accuracy of the exposure machine but by the etching amount for forming the recess.

Therefore, the offset gate can be formed accurately without being affected by the alignment accuracy of the exposure process, and there is no inconvenience that the bottom surface of the recess is contaminated by applying the resist to the recess region.

[Brief description of the drawings]

FIGS. 1A and 1B are views showing one step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG.
FIG. 3 is a cross-sectional view of (A) taken along a cutting line XX ′ and viewed in a direction of an arrow.

FIGS. 2A and 2B are diagrams showing a process subsequent to FIG. 1; FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view of FIG. 1A cut along a cutting line XX ′ and viewed in a direction of an arrow; .

3A and 3B are views showing a step subsequent to FIG. 2; FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view of FIG. .

FIG. 4 is a view showing a step subsequent to FIG. 3, wherein (A) is a plan view, and (B) is a cross-sectional view of (A) taken along a cutting line XX ′ and viewed in a direction of an arrow. .

5A and 5B are views showing a step subsequent to FIG. 4, wherein FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view of FIG. .

FIG. 6 is a view showing a step subsequent to FIG. 5, wherein (A) is a plan view, and (B) is a cross-sectional view of (A) cut along a cutting line XX ′ and viewed in a direction of an arrow. .

7A and 7B are views showing a step subsequent to FIG. 6; FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view of FIG. .

8A and 8B are views showing a step subsequent to that of FIG. 7; FIG. 8A is a plan view, and FIG. 8B is a cross-sectional view of FIG. .

9A and 9B are views showing a step subsequent to FIG. 8, wherein FIG. 9A is a plan view, and FIG. 9B is a cross-sectional view of FIG. 8A cut along a cutting line XX ′ and viewed in the direction of an arrow. .

FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique in the order of steps.

FIG. 11 is a cross-sectional view showing a method of manufacturing another conventional semiconductor device in the order of steps.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing another conventional semiconductor device in the order of steps;

[Explanation of symbols]

Reference Signs List 1 GaAs substrate 2 working layer 3 first insulating film 3A cavity 4 second insulating film 4A second opening 5 resist layer 5A first opening 6 third insulating film 6A third opening 7 recess 8 First gate metal 9 Second gate metal 10 Gate electrode 11 GaAs substrate 12 Active layer 13 Insulating film 14 Resist layer 15 Recess 16 Resist layer 17 Gate metal 21 GaAs substrate 22 Channel layer 23 n ⁺ type conductive film 24 Ohmic electrode 25 Insulating film 26 Resist layer 27 Gate electrode 28 Recess 31 GaAs substrate 32 Operating layer 33 First insulating film 34 Second insulating film 35 Resist layer 36 First recess region 37 Resist layer 38 Second recess region 39 Gate electrode

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (5)

(57) [Claims] Forming a first insulating film defining a recess width on the substrate by patterning the insulating film after depositing the insulating film on a surface portion of an active region of the semiconductor substrate; Depositing a second insulating film having an etching rate smaller than that of the first insulating film with respect to a predetermined etching means, and causing at least a part of the second insulating film to be present on an edge of the first insulating film. wherein the step of forming a resist layer having a first opening exposing the second insulating film, by then the resist layer as a mask for etching the second insulating film, a gate forming region
The second opening where the edge of the first insulating film is exposed is formed in the second opening.
Forming a third insulating film of the same type as the second insulating film on the second insulating film including the inside of the second opening.
Depositing an insulating film, and etching the insulating layer composed of the third and second insulating films from above to the bottom.
An edge portion of the first insulating film and adjacent to the edge portion
Etching so that the portion of the insulating layer
Removing a third opening to form a third opening;
Removing all of the first insulating film by etching through the opening, etching the active region exposed by removing the first insulating film to form a recess, A method of manufacturing a semiconductor device, comprising: depositing a gate metal forming a Schottky junction with a region; and forming a gate electrode by shaping the gate metal by a predetermined etching means. 2. The method according to claim 1, wherein the first insulating film is a silicon oxide film, and the second and third insulating films are silicon nitride films. 3. The semiconductor device according to claim 1, wherein said first insulating film is a silicon oxide film, and said second and third insulating films are films having a dielectric constant lower than that of silicon nitride. Manufacturing method. 4. The method according to claim 3, wherein the low dielectric constant film is a cyclic olefin resin film. 5. The method according to claim 1, wherein the first insulating film is etched by a wet etching method, and the second and third insulating films are etched by a dry etching method. .