JP2891212B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a field-effect transistor in which a gate is formed by opening an insulating film and burying a gate metal.

[0002]

2. Description of the Related Art In recent years, a Schottky junction field effect transistor (MESFET) having a structure in which a gate electrode is formed directly on a conductive layer on the surface of a compound semiconductor substrate such as GaAs.
And a microwave monolithic integrated circuit (MMIC) using this MESFET.
ted Circuit) is used in various fields such as mobile communication.

The above-mentioned FETs are required not only to have a large power gain but also to have a small variation in gain between FETs. In particular, in the case of an MMIC which is designed on the same GaAs substrate, that is, in one chip, by designing the frequency matching circuit based on the gain characteristics and the like of the FET described above,
Variations in the gain characteristics of the ET greatly affect the yield of the MMIC.

It is known that the power gain is expressed by the following equation.

[0005]

(Equation 1) Here, f is the signal frequency, ft is the current cutoff frequency, and g ₀
Is a drain conductance, Rg is a gate resistance, Ri is a channel resistance, Rs is a source resistance, Ls is a source inductance, and Cgd is a gate-drain capacitance.

Conventionally, the above FET is manufactured as shown in FIG. First, as shown in FIG.
An insulating thin film (SiO ₂ ) 22 is deposited on a substrate 21, a photoresist 23 is applied thereon, and a gate forming region is exposed and developed to form an opening 24.

Next, as shown in FIG.
An opening 25 is formed in the insulating thin film 22 by dry etching using the photoresist 23 on which the substrate 4 is formed as a mask. Next, as shown in FIG.
After gold is deposited, a gold plating position is defined by a photoresist 27 in order to perform gold plating for reducing gate resistance. Then, after forming the gate low resistance portion 28 using the photoresist 27 as a mask, the photoresist 27 is removed to manufacture an FET having a structure shown in FIG.

[0008]

However, in the above-described conventional method for manufacturing a semiconductor device, the step of defining the gold plating position shown in FIG. , And a gate sectional structure as shown in FIG. If the gate low-resistance portion 28 shifts to the drain side as shown in the cross-sectional structure of FIG. 3D, the parasitic capacitance (Cgd) between the gate and the drain increases, and the power gain is calculated according to the equation (1). Decrease.

That is, the gate low resistance portion 28 is
If there is misalignment with respect to the Schottky portion, there is a problem that the gate-drain capacitance Cgd changes, the gain characteristics of the FET greatly vary, and it is difficult to design the MMIC with high yield.

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide a method of manufacturing a semiconductor device which enables a low-resistance gate portion to be formed in a self-aligned manner without alignment with a gate Schottky portion.

[0011]

In order to achieve the above object, the present invention provides a method for manufacturing a gate insulating film on a substrate.
A first step of laminating and forming a resist and a gate formation assisting metal having an opening in order, a second step of ashing and side-etching the resist through the opening of the gate formation assisting metal, and a gate formation assisting metal Forming an opening in the gate-forming insulating thin film using the opening as a window, removing the gate-forming auxiliary metal, and forming a gate metal through the opening in the gate-forming insulating thin film.
The method includes a fourth step of removing the resist and a fifth step of selectively removing the insulating thin film for gate formation.

In the present invention, the gate forming auxiliary metal is
Since it is also used as a mask for side etching of a resist for arranging a gate metal on the insulating thin film for gate formation and a mask for forming an opening of the insulating thin film for gate formation,
The gate metal can be made self-aligned to the substrate.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 and FIG. 2 are cross-sectional views of an apparatus for explaining each step of an embodiment of a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1A, a silicon oxide film 12 is deposited on a GaAs epitaxial substrate 11 as an insulating thin film for forming a gate, for example, to a thickness of 500 nm, and a resist 13 is applied thereon to a thickness of about 1.2 μm. 1
Tungsten silicide WSi is formed on gate electrode 3 as gate formation auxiliary metal 14 to a thickness of about 50 nm. Further, as shown in FIG.
After applying a resist 15 on the resist 4, an area 16 where a gate is to be formed is exposed and developed to form an opening 16
5 is formed.

Subsequently, as shown in FIG.
An opening 17 is formed in the gate formation assisting metal (WSi) 14 by dry etching using the resist 15 having 6 as a mask.

Subsequently, a gate formation assisting metal (WSi)
Using the opening 17 of 14 as a window, the resist 13 is ashed by oxygen plasma treatment and side-etched to form an opening in the resist 13 as shown by 18 in FIG. The resist 15 is incinerated and disappears during this process.

Next, as shown in FIG. 2D, the opening 17 of the gate formation auxiliary metal (WSi) 14 is used as a window.
An opening 19 is formed in the gate-forming insulating thin film (silicon oxide film) 12 by dry etching. Subsequently, FIG.
As shown in (e), metal for assisting gate formation (WSi)
14 is removed.

Next, as shown in FIG.
A gate metal 20 having a structure in which t and Au are stacked in this order is deposited on the device. Thereafter, as shown in FIG. 2G, the resist 13 and the resist 1 are lifted off.
After the gate metal 20 on the substrate 3 is removed, the insulating thin film (silicon oxide film) 12 for gate formation is selectively removed by etching using buffered hydrofluoric acid, and the GaAs substrate 11 is removed.
The gate metal 20 is left as a gate electrode (gate low-resistance portion) on the top. After that, the source 21 and the drain 2
2 is formed, and an ohmic electrode 23 is deposited to manufacture an FET.

According to such a manufacturing method, 5 lots of F
ET was manufactured, and 10 FEs for each lot, a total of 50 FEs
As a result of measuring the gain characteristic of T (maximum oscillation frequency: f _max ), the maximum oscillation frequency was within a narrow range of 60 GHz ± 5 GHz, and very good results with little variation were obtained. Note that five lots of FETs were manufactured by the conventional manufacturing method shown in FIG. 3, and the gain characteristics (maximum oscillation frequency: f _max ) of a total of 50 FETs were measured for each lot. The frequency was in a wide range of 60 GHz ± 30 GHz, and a result with large variation was obtained.

Next, another embodiment of the present invention will be described. In this alternative embodiment, the thickness of 50nm approximately A as a gate forming auxiliary metal 14 shown in FIGS. 1 (a)
using l, thereon the resist 15 coated after exposure and developed to form an opening 16. Then, FIG. 1 (b),
(C), an FET is manufactured through each of the manufacturing steps described with reference to FIGS. 2 (d) to (g).

In this other embodiment, five lots of FETs were manufactured, and the gain characteristics (maximum oscillation frequency: f _max ) of a total of 50 FETs were measured. The frequency was within a narrow range of 60 GHz ± 5 GHz, and extremely good results were obtained.

In the above embodiment, the MESFET using the GaAs epitaxial substrate 11 has been described as an example, but the MESFET formed by ion implantation into a semi-insulating substrate is described.
Of course, the same effect can be obtained in the SFET,
Heterojunction FE with HEMT structure epitaxial substrate
It was confirmed that a similar effect was obtained in the case of T.

[0023]

As described above, according to the present invention,
In the present invention, the gate-forming auxiliary metal is used also as a mask for forming a gate metal on the insulating thin film for forming a gate and a mask for forming an opening of the insulating thin film for forming a gate. Since the metal can be manufactured in a self-aligned manner without alignment with the substrate, variation in gain characteristics of the field effect transistor due to misalignment can be significantly reduced, and the field effect transistor can be manufactured at low cost.

Further, according to the present invention, since there is little variation in gain characteristics, a frequency matching circuit is designed based on the gain characteristics and the like, and the yield of the MMIC in which a plurality of field effect transistors are formed in one chip is reduced. Can be greatly improved as compared with

[Brief description of the drawings]

FIG. 1 is a sectional view (part 1) of an apparatus for explaining each manufacturing process according to an embodiment of the method of the present invention.

FIG. 2 is a sectional view (part 2) of an apparatus for explaining each manufacturing process according to an embodiment of the method of the present invention.

FIG. 3 is a cross-sectional view of an example of a conventional method for explaining manufacturing steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 GaAs epitaxial substrate 12 Insulating thin film (silicon oxide film) for gate formation 13, 15 Resist 14 Gate formation auxiliary metal 20 Gate metal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (3)

(57) [Claims] A first step of forming an insulating thin film for forming a gate, a resist, and a metal for forming a gate having an opening on a substrate in this order; and depositing the resist through the opening of the metal for forming a gate. A second step of forming an opening in the insulating thin film for gate formation using the opening of the metal for assisting gate formation as a window, and then removing the metal for assisting gate formation. A fourth step of removing the resist after forming a gate metal through an opening in the gate-forming insulating thin film; and a fifth step of selectively removing the gate-forming insulating thin film. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the substrate is a compound semiconductor substrate, and the gate formation assisting metal is formed of a metal material removed by dry etching in the third step. A method for manufacturing a semiconductor device. 3. The substrate according to claim 1, wherein the substrate is a compound semiconductor substrate, and the gate formation assisting metal is formed of a metal material removed by wet etching in the third step. A method for manufacturing a semiconductor device.