JPH0461129A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a HEMT with an improved noise figure without the decrease in source-gate and source-drain breakdown voltage by forming a thin p-type GaAs layer, with a limited hole concentration, between a semi-insulating GaAs substrate and an undoped GaAs layer. CONSTITUTION:A Be-doped p-type GaAs layer 12, an undoped GaAs layer 13 and an Si-doped AlGaAs layer 15 are sequentially formed on a semi- insulating GaAs substrate 11. The AlGaAs layer 15 includes a two-dimensional electron gas region 14, as an electron source, near the heterojunction with the undoped GaAs layer 13. To provide a HEMT, an aluminum gate electrode 16 is formed on the Si-doped AlGaAs layer 15, and a source electrode 17 and a drain electrode 18 are formed on opposite sides of the gate electrode. The carrier concentration of the Be-doped p-type GaAs layer 12 is in a range of 2X10<11> to 1X10<12>cm<-2>. This HEMT is prevented from the decrease in source- gate and source-drain breakdown voltage and the decrease in gm near the pinch-off point.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and in particular to a high electron mobility transistor (High Electron Transistor) using a two-dimensional electron gas.
tron Mobility Transistor,
The present invention relates to improvements in the HEMT (hereinafter abbreviated as HEMT).

(Conventional technology) In the advanced technology, a heterojunction is formed using two types of semiconductors with different band gaps, and the electron concentration of the two-dimensional electron gas formed at the heterojunction interface is controlled by the voltage applied to the control electrode. This is a three-terminal active semiconductor device based on this principle of operation.

An example of the structure of a conventional IEMT is shown in cross-section in FIG. The example HEMT shown in FIG.
Undoped GaAsM formed on aAs substrate 101
102, and a high impurity concentration AlGaAs layer 104 which is laminated on this undoped GaAs layer 102 and forms a heterojunction with the undoped GaAs layer 102, this high impurity concentration AlGaAs layer 104 serves as an electron supply layer,
An electron transit layer 103 is formed on the undoped GaAs layer 102 side of the Peter junction interface. Further, a gate electrode 105 serving as a control electrode is provided on the AlGaAs layer 104, and a source electrode 105 is provided on the AlGaAs layer 104 to sandwich the gate electrode 105.
06 and a drain electrode 107 are provided to constitute an MT.

(Problems to be Solved by the Invention)) The characteristics of IEMT are that the AlGaAs layer 104, which is the electron supply layer, and the electron transport layer 103 are separated by a heterojunction, and the carriers and the two-dimensional electric f-gas in L2 are free from impurities. Since it runs on the less undoped GaAs Jil 102 side, impurity scattering is suppressed and high electron mobility can be obtained. Therefore, HEMT is expected to be used as a low-noise device at high frequencies. In order to further improve the high frequency characteristics of the HEMT, shortening the gate length is an effective step. By shortening the gate length, the source-gate capacitance Cgm is reduced and the mutual conductance g is increased, and the noise characteristics are improved by increasing the cutoff frequency ft. However, due to the short channel effect that occurs with the shortening of the gate length, a problem arises in that the low F of g near the pinch-off becomes noticeable in the static characteristics of the MT. For example, the gate length prototyped by the present inventors is 0.
．． HEIIT No. 254 exhibited static characteristics as shown in FIG. This decrease in g near the pinch-off worsens the noise characteristics. Therefore, the effect of improving noise characteristics by shortening the gate length was not necessarily sufficient.

In order to prevent a decrease in R in the vicinity of pinch-off, undoped G
Approximately 1000 A from the electric T running layer 103 in the aAs layer 102
A method has been reported in which a 1] type GaAs layer with a zero layer thickness of about 1000 Å is inserted at the position (IEICE technical research report ED87-159 p., 43). Normal HE M
In T, do you use mesa etching for element isolation? Electrode pads for the source, 1-rain, and gate electrodes are formed on the etched undoped GaAs layer 102. 1- In the previously reported structure, depending on the depth of mesa etching, this electrode pad may be a p-type Ga
If the As layer is formed in the As layer or the distance to the p-type layer is too short, the withstand voltage between the electrode pads, for example between the source and the drain, decreases and a leakage current flows. Therefore, in order to prevent a drop in breakdown voltage between the electrode pads, the mesa etching depth must be precisely controlled, resulting in a problem of low yield in device manufacturing.

Therefore, as shown in FIG.
The thickness of the aAs layer 1.02 is set to 5000 A, for example, and the electrode pad is separated from the P-type layer to ensure that the undoped GaAs
We proceeded with the experiment thinking that if we formed the pads in layers, leakage between the pads could be suppressed. Here, 104 is an AlGaAs layer with high impurity concentration which is an electron supply layer, and 103 is an electron transport layer 6A1. The GaAs layer 104'' has a gate electrode 1.05, which is a control electrode, and an Al layer sandwiching the gate electrode 1.05, which is a control electrode.
A source electrode 106 and a drain electrode 107 are provided on the GaAs layer 104. The inventors have determined that the layer thickness is 10
When we prototyped a HEMT using a crystal in which a p-type GaAs layer with a p-type carrier concentration of 3 x 10"cm-' was inserted, as shown in Figure 6, the g
It was found that the decrease in , was alleviated, and it was found that inserting a P-type GaAs layer between the substrate and the undoped GaAs layer is also effective. However, even in the EMT shown in FIG. 5, the effect of improving noise characteristics was not necessarily sufficient.

In order to investigate the cause, we investigated the leakage current between the source and gate, and found that while the leakage current in a HEMT without a p-type GaAs layer was 10μA at 6V, it was 10μA at 1.5V in this element. In addition, a decrease in breakdown voltage was observed between the source and drain. Furthermore, it was found that these reductions in breakdown voltage were caused by leakage current between the electrode pads due to the insertion of the P-type GaAs layer. Therefore,
The present inventors focused on the relationship between the breakdown voltage of the GaAs buffer layer and the sheet carrier concentration of the p-type layer and investigated the dependence. As shown in FIG. It was found that these reductions in withstand voltage become significant when exceeding ``cm-''.From the results shown in Fig. 7, when weighing the structure shown in Fig. 5, the sheet carrier of the p-type layer to be inserted is There is an upper limit value for the concentration from the viewpoint of preventing low pressure resistance, and that value is approximately] x 1012 cm-
It turned out to be 2.

Next, in order to investigate the effect of inserting a p-type GaAs layer from the viewpoint of suppressing the short channel effect, the relationship between the p-type sheet carrier concentration and g near the pinch-off (Ins = 5 mA) was investigated. The results are shown in FIG. As shown in the figure, when the sheet carrier concentration is 1X 10"Icm-", g = 17mS, and when it is 2XIO"cm-" or more, it is 30
It was between 5 m and 35 m5. From this result, it was found that when the sheet carrier concentration is 2×101101 l” or less, there is almost no effect of suppressing the short channel effect.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a semiconductor device with an improved structure.

[Structure of the invention]

(Means for Solving the Problems) A semiconductor device according to the present invention is formed by sequentially stacking layers on a single insulating compound semiconductor substrate, and has a hole concentration of 2×101.
A p-type semiconductor thin layer within the range of 1 to I x 1012 cm-2, an undoped electron supply layer provided on the p-type semiconductor layer, and a gate, source, and drain provided on the electron supply layer. It is characterized by having each electrode.

(Function) The HEMT according to the semiconductor device of the present invention has a gate length of O,
Even if it is shortened to 254 or less, the withstand voltage between the source and gate and between the source and drain inevitably decreases. Moreover, it is possible to improve the noise characteristics of RENT by also improving the decrease in g near the pinch-off.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a sectional view of an MT according to an embodiment of the present invention. The crystal layer is formed by molecular-line crystal growth (Mol) using the following method.
ecular Bearn Epitaxy; MBE
) grown by the law. Semi-insulating GaAs substrate 1
1,, J-, an i3e-doped P-type GaAs layer 12 with a layer thickness of 100A, and then an undoped GaAs layer 13 with a layer thickness of 500A.
0A, and Si-doped A1GaAs layer 15 with a layer thickness of 30A.
0A is sequentially laminated. The carrier concentration of the A1GaAs layer 15 is 2 x 10"cm", and this AlGaAs
115 is an undoped GaAs layer 13 as a current T-supply layer.
2 on the undoped GaAsM13 side near the hetero interface with
A dimensional electron gas 14 is formed.

Next, Si-doped A1. A gate electrode 16 made of A1 is formed on the GaAs layer 15, and a Ni/Au layer is sandwiched therebetween.
A HEMT includes a source electrode 17 and a drain electrode 18 made of Ge.

The carrier concentration of the Be-doped P-type GaAs layer 12 is 8XI
O17c [1, that is, the sheet carrier concentration is also 8×
Fig. 2 shows the static characteristics of an MT with a gate length of 0.25 mm and a gate length of 104.1c[2. Compared to the static characteristics of the conventional structure shown in FIG. 4, it can be seen that there is a significant improvement in the reduction of h at low drain currents. For example, VD=3V.

The gl at IDS" 5 raA is 35 m5 compared to 16 m5 in the conventional structure. Also, compared to the leakage current of 10 μA at a source-gate voltage of 6 V in the conventional structure, the RENT in the present invention In this case, the leakage current is 10μA when the voltage between the source and gate is 5μ, and the GaAs
The breakdown voltage of the buffer layer was 25 µA (the breakdown voltage at which the leakage current was 10 μA).Therefore, no deterioration in the breakdown voltage of the GaAs buffer layer due to the insertion of the p-type GaAs thin layer and no deterioration in the breakdown voltage between the electrode pads was observed.

Furthermore, the noise figure at 18 GHz at this time is O,
8 clB, which is approximately 0.2 dB lower than that of the FIEMT with the conventional structure shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, P is formed between the semi-insulating GaAs substrate and the undoped GaAs layer which is the buffer layer.
In HEMTs with a thin GaAs layer inserted, p-type GaAs
By setting the hole surface concentration of the As thin layer to 2 x 1011cm"-" or more and lx10'em-" or less, it is possible to reduce the pressure near the pinch-off without lowering the voltage between the source and gate and between the source and drain. It is possible to suppress low g, and improve noise characteristics.

Note that in the example described in "-", the film thickness of the p-type GaAs layer was 100A.
, the carrier concentration is 8 x 10"cm, but the present invention is not limited to this value, and the hole surface concentration of the P-type GaAs layer is 2 x 10"cm.
-2 to 1-1l It may be a recessed structure, and further AlG
A structure may be employed in which a spacer layer made of undoped AlGaAs is provided between the aAs power supply layer and the undoped GaAs layer.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of the HEMT according to the present invention, FIG. 2 is a diagram showing the static characteristics of the HEMT according to the present invention, and FIG.
Figure 4 is a cross-sectional view showing the structure of a conventional HEMT, Figure 4 is a diagram showing the static characteristics of the conventional HEMT shown in Figure 3, and Figure 5 is a diagram showing the structure of a T in the HEMT according to the conventional example. The cross-sectional view shown in FIG. 6 is the old EM according to the conventional example shown in FIG.
Figure 7 is a diagram showing the relationship between the sheet carrier concentration of the p-type GaAs layer and the breakdown voltage of the GaAs buffer layer, and Figure 8 is a diagram showing the relationship between the sheet carrier concentration of the p-type GaAs layer and the MT g near the pinch-off of , which relationship l indicates
It is an iA diagram. 1.1.Semi-insulating GaAS substrate, 12..p-type GaAs
Layer, 13... Undoped GaAs layer, 14... Two-dimensional electron gas, 15- Si doped AlGaAs layer, 1
6. Gate electrode, 17... Source electrode, 18... Drain electrode or agent Patent attorney Norio Ogo 101: 102: 104: 106; YuAs layer 103°5iF-7”
AffieaAs layer 105: Pass the source*
107: 3rd figure 2n5; t=? 3 small] “Skate 1L layer do L it, k V[) S - Fig. 4?l 2'Hl!g: a2, yesterday^5JIJt Do in 1
1k 0S 108: P 纺GαAs 体 [mA] OS Flute 6

Claims (1)

[Claims] Hole concentration formed by sequentially stacking layers on a single insulating compound semiconductor substrate is 2 x 10^1^1 to 1 x 10^1^2 cm
A p-type semiconductor thin layer within the range of ^-^2, an undoped semiconductor layer provided on the p-type semiconductor thin layer, and an impurity doped on the undoped semiconductor layer with a band gap larger than this. A semiconductor device comprising an electron supply layer and gate, source, and drain electrodes provided on the electron supply layer.