JPH0460744A - Digital microcomputer - Google Patents

Abstract

PURPOSE:To speed up access between CPU by providing a function discriminating, detecting or specifying the period of the stop state of sub-CPU on a main CPU-side in an electronic musical instrument and the like having plural CPU. CONSTITUTION:A master central processing unit (MCPU) 10, a slave central processing unit (SCPU) 20, a timer interruption generation means, a sub-CPU mode control means and a sub-CPU mode discrimination means are provided in the electronic musical instrument and the like. MCPU 10 controls the input/ output device and executes a sound source processing. SCPU 20 executes the sound source processing. MCPU 10 and SCPU 20 execute the sound source processing in parallel by timer interruption. SCPU 20 is shifted to a reset state when an operation terminates and transmits a termination signal to MCPU 10. MCPU 10 accesses to an internal memory by the termination signal while SCPU 20 stops and reads a waveform which SCPU 20 generates.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital microcomputer, and more particularly to a digital microcomputer having a plurality of CPUs that can operate in parallel.

BACKGROUND OF THE INVENTION Digital microcomputers having multiple CPUs are known. Generally, the purpose of providing multiple CPUs is to improve the performance of a computer system. Unfortunately, even if the number of CPUs is increased to N, the performance of the system cannot be increased to N times that of a system with one CPU.

One of the causes of degrading the performance of a digital microcomputer with multiple CPUs is the problem of access between the CPUs.

Conventionally, access between CPUs is performed as follows. First, the CPU requesting access
Sends an access request signal to the PU. On the other hand, the CPU that receives the access request signal completes the operation being executed, and then releases the internal memory so that it can be accessed by an external device (in this case, the CPU that requested access). It sends an approval signal to the CPU that requested access and transitions to a stopped state. After receiving this approval signal, the CPU that requested access
Performs the actual access operation to U's internal memory.

Therefore, the conventional access method between CPUs has the problem that the access procedure takes a long time.Especially in an environment where frequent access between CPUs is required, access processing becomes a bottleneck for CPU operation. Efficiency will drop significantly.

[Object of the Invention] Therefore, an object of the present invention is to provide a digital microcomputer having a plurality of CPUs that can process access between CPUs at high speed.

[Structure and operation of the invention] According to the present invention, a main CPU, at least one sub CPU, an operation start signal generating means for generating an operation start signal, and an operation start signal generating means for generating an operation start signal, and an operation start signal generating means for generating an operation start signal.
a sub-CPU that controls switching of the mode of the sub-CPU from a stopped state to an operating state in which a program is executed, and controls the sub-CPU to return to the stopped state in response to completion of execution of the program;
a mode control means, a sub CPU mode determination means provided in the main CPU and for determining whether the mode of the sub CPU controlled by the sub CPU mode control means is in a stopped state; and sub-CPU access means for accessing an internal memory of the sub-CPU while the mode of the sub-CPU is in a stopped state as determined by the sub-CPU mode discrimination means. provided.

The basic feature of this configuration is that a sub CPU is installed on the main CPU side.
A function is provided to determine the period during which the PU is in a stopped state. Since the main CPU accesses the internal memory of the sub CPU when the sub CPU is in a stopped state,
As in the past, access is requested to the sub-CPU, and the sub-C
There is no need to wait for access approval from the PU, and the sub-CPU's internal memory can be accessed quickly (in the same manner as the main CPU's own internal memory is accessed).

In a preferred configuration example, a main CPU, at least one sub-CPU, interrupt generation means for generating a timer interrupt signal every predetermined time period, and a main program being executed in the main CPU in response to the timer interrupt signal. The mode of the main CPU is switched to a mode for executing an interrupt processing routine, and in response to the completion of execution of the interrupt processing routine, the interrupted main program is restarted and the mode of the main CPU is changed to a mode for executing an interrupt processing routine. main CPU mode control means for controlling a return to a mode for executing a program; and a main CPU mode control means for controlling switching of a mode of the sub CPU from a stopped state to a mode for executing a program in response to the timer interrupt signal, and responding to completion of execution of the program. sub-CPU mode control means for controlling the mode of the sub-CPU to return to a stopped state again; and sub-CPU mode signal generation means, provided in the sub-CPU mode control means, for generating a signal representing the mode of the sub-CPU; , provided in the main CPU, receiving the signal from the sub CPU mode signal generating means and transmitting the signal to the sub CPU.
sub-CPU mode detection means for detecting a mode of the sub-CPU; and a sub-CPU mode detection means provided in the main CPU, accessing an internal memory of the sub-CPU while the sub-CPU mode detection means detects a stopped state of the sub-CPU. A digital microcomputer is provided, characterized in that it has a sub-CPU access means.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

Summary> This embodiment applies this invention to an electronic musical instrument.
This embodiment (FIGS. 1 to 34) includes various features. The first feature is that multiple microcomputer processing units (
CPU), and there is no need for a dedicated hardware sound source like in the past. One CPU acts as the main CPU or master CPU (10),
Input devices (keyboards, function keys, etc.) and output devices (D
AC, etc.) (Figures 4 and 5), and other CPUs are sub CPUs or slave CPUs for the master CPU.
It functions as U (20) and executes sound source processing (FIG. 6).Therefore, the burden of sound source processing is shared between each CPU.

The second feature is related to the mechanism by which the sub CPU starts and ends its operation, and according to this embodiment, the sub CPU
The operation starts in response to a timer interrupt that requests sound source processing to the master CPU, and as a result, sound source processing is executed in parallel in the master CPU and sub CPU. When the operation (sound source processing) of the sub CPU is completed, the sub CPU is transferred to the reset state (stop state S) by the completion signal, and the completion signal is sent to the master CPU.
This feature allows the master CPU to effectively manage and keep track of the operating period of the sub-CPUs. Furthermore, this feature allows efficient execution of sound source processing tasks (generating digital samples of musical tone signals) that require high-speed processing.

The third feature of this embodiment relates to the problem of updating (transferring) data passed from the main program to the timer interrupt processing routine. As a result of the execution of the interrupt processing routine, it becomes necessary to update a plurality of data to be referenced in the interrupt processing routine (for example, envelope parameters such as an envelope target value and an envelope plate). The execution instructions for updating this plurality of data are included in the main program. That is, this plurality of data is updated by the main program and referenced by the timer interrupt processing routine. Since such multiple pieces of data constitute meaningful information as a whole, control must not be transferred to the interrupt processing routine before all of the multiple pieces of data have been updated in the main program. As a method, a method has been disclosed in which the interrupt is masked and the transition to the interrupt processing routine is prohibited until the data update is completed (Part 1).
6 and 17), and as a second method, a method is disclosed in which multiple data updates (transfers) are executed with a single instruction in the main program (Figs. 18 to 21). , the processing results (samples of musical tone signals) of the interrupt processing routine indicate correct behavior, and correct operation is guaranteed.

The fourth feature of this embodiment is that from the master CPU to the slave C
Concerning data access issues for PUs. In conventional multi-CPU microcomputer systems, C
Data transfer between PUs is performed through a series of sequences and takes a considerable amount of time.6 Typically, a CPU requesting data access sends an access request signal to the CPU to which access is requested. In response to this access request signal, the CPU to which access is requested completes the operation being executed, and then sends an acknowledge signal to the CPU.
and enters the stopped state. After the access request signal is sent, the requesting CPU is in a waiting state until the approval signal is received. Upon receiving the approval signal, the requesting CPU performs actual data access to the internal memory of the requested CPU. As described above, the conventional inter-CPU data access method is time-consuming and is not suitable for applications such as electronic musical instruments where high-speed processing is desired. To solve this problem, in this embodiment, as the first data access method,
Utilizing the second feature above, when the sub CPU is in a stopped state, the master CPU uses the sub CPU's internal memory (20
6), a stop mode control method for reading/writing (accessing) the pig is disclosed (Fig. 22), and as a second data access method, the master CPU accesses data from the sub CPU without waiting state (the sub CPU An instantaneous data access method (forcibly stopped only during data access) is disclosed (FIGS. 23 to 25).

The fifth feature of this embodiment is that the CPU external memory as a data source is shared by multiple CPUs.
According to this embodiment, by providing a memory device conflict avoidance circuit (50) to be described later, conflicts in access to the shared memory are resolved, and after a certain waiting time, the shared memory is Allows data to be retrieved from memory.

The sixth feature of this embodiment relates to speeding up data conversion processing (shifting, inversion, partial extraction, etc.).

Conventionally, data in a data memory such as the above-mentioned CPU external memory is transferred to the CPU internal memory (5iF
In order to obtain the converted data on the calculation memory, a transfer (read access) command is used to move the data in the data memory to the calculation memory, and then a conversion command is used to transfer the data in the calculation memory to the calculation memory. Convert. It is also often necessary to execute multiple conversion instructions to effect the desired data conversion. As described above, there has been a problem in the past that data conversion processing takes time, which is a particularly serious problem in applications that require high-speed processing, such as sound source processing. To solve this problem, this embodiment uses data address translation hardware (
60, 70), and by executing a special transfer instruction (transfer with conversion instruction), the data in response to that instruction can be transferred.
Data that has been subjected to desired data conversion via the address conversion hardware is loaded into the calculation memory (106, 206). Therefore, in order to obtain desired conversion data, it is sufficient to execute a single instruction instead of a plurality of instructions, and the processing speed can be increased.

Figure 1 is a sub-block diagram showing the overall configuration of this embodiment configured as a processing device for an electronic musical instrument. 5CP for the other
(denoted as U20).

Each CPU10120 has a built-in program, and 1MCPU10, which operates according to each program, controls the entire system in addition to sound source processing (Fig. 5), such as λ
processing of input information from an input device H (for example, a keyboard, function keys, etc.) connected to the port 118 and the output port 120;
DAC that converts digital musical tone signals to analog musical tone signals
loo control etc. (!$4 figure), whereas 5C
The PU 20 is dedicated to sound source processing (FIG. 6).

A memory 90 serves as a data source for sound source control data, waveform data, and the like. The data memory 90 is an LSI
It consists of a ROM externally attached to a chip (which carries the remaining devices in Figure 1). If the degree of integration is high, data memory 90 can be formed as an internal memory on a single LSI chip. External memory 90 is MCPU
10 and 5 CPU20. Address information from MCPUIO is transferred to address bus M that couples to MCPUIO.
A. MCPU external memory address latch 30M of external memory address switch 30, address switching circuit 40,
It is applied to the address input of external data memory 90 via address conversion circuit 60. On the other hand, the address information from the 5 CPU 20 is transferred to the address bus S connected to the 5 CPU 20.
It is applied to the address input of the external data memory 90 through the A, 5 CPU external memory address latch 3O3, address switching circuit 40, and address conversion circuit 60. The data transmission path from the external data memory 90 to the MCPUIO is constituted by the data output of the external data memory 90, the data conversion circuit 70, the MCPU external memory data latch 80M of the external memory data latch 80, and the data bus MD coupled to the MCPUIO. On the other hand, the data transmission path from the external data memory 90 to the 5 CPU 20 is the data output of the external data memory 90, the data conversion circuit 70.
3 CPU external memory data latch 8°S, 5 CPU 20
It is constituted by a data bus SD coupled to the data bus SD.

The memory device conflict avoidance circuit 5o includes MCPUIO and 5CPU
This is to control access to the external memory 9o by both CPUs 20 and avoid conflicts. The memory device conflict avoidance circuit 50 controls the address switching circuit 40 in response to the signal roma requesting external memory access from MCPUIO and the signal roma requesting external memory access from the 5 CPUs.
selects either the address from MCPUIO or the address from 5CPU 20 as the address to external memory 90. For this purpose, the address switching circuit 40 receives the selection signal MSEL from the memory device conflict avoidance circuit 50.
When the address to the external memory 90 is determined, the memory device contention avoidance circuit 50 selects a select signal GE and an output enable signal OE for the external memory 90.
Activate. This causes data to be output from external memory 90 and appear on the input bus of external memory latch 80 through data conversion circuit 70 . Here, the memory device contention avoidance circuit 5° operates either the MCPU external memory data latch 80M or the 5CPU external memory data switch SO5 to latch the data in order to send the data to the CPU that has requested the data access. For this purpose, the MCPU external memory data latch 80M performs a latch operation based on the latch signal MDL from the memory device contention avoidance circuit 50, and the 5CPU external memory data latch 80S
is the latch signal SDL from the memory device contention avoidance circuit 50.
It is designed to latch.

The address conversion circuit 60 and the data conversion circuit 70 convert the data of the external data memory 90 into the CPU10.
This is a conversion device for importing into 20. The address conversion circuit 60 is the address switching circuit 40.
The address passed through the CPU (MCPUIO or 5C
The data conversion circuit 7 selectively changes the address (logical address) output from the PU 20) to form an address that is actually input to the external data memory 90.
0 selectively changes the data output from the external data memory 9o to form data actually input to the CPU (MCPUIO or 5CPU 20). In order to specify the conversion mode in each conversion circuit 6o, 7o,
Control signals are used. In each CPU10120,
Data access to external data memory 90 is performed by executing a transfer command. CP based on transfer instruction
The control signals generated at U are MHI, MR2, MR3 (M
CPUIO), SRI, SR2, SR3 (SCP
In the case of U20). These signals are called signals R1, R2, and R3 after passing through an external memory addressr 7ch 30 and an address switching circuit 40 (MRi
+LMRi→Rf or SRi+LsRi+Ri), control signals R1 and R2 are input to the address conversion circuit 60 to specify the conversion mode. Furthermore, the data conversion circuit 7
0, the control signal R1,
R2, R3, address bit 12 signal A12 from address conversion circuit 60, and address bit 15 signal A15
is added to the data conversion circuit 70. Details of the address conversion circuit 6o and the data conversion circuit 70 will be described later.

In order to define the interface between MCPUIO and 5 CPUs 20, #I signals are transmitted between both CPUs.

Signal A is 5C sent from MCPUIO to 5CPU20
A signal indicating the start of processing of PU20, signal B is 5CPU2
0 to the MCPUIO indicating the end of processing of the 5CPU 20, Ma is the internal memory of the 5CPU 20 sent from the MCPUIO to the 5CPU 20 (206 in Figure 3)
address information, signal C is from MCPUIO to 5CPU2
0 is the internal memory read/write control signal of the 5CFU20, Din is the read data from the internal memory of the 5CPU20 sent from the 5CPU20 to the MCPUIO, D
o+++ is sent from MCPUIO to 5CPU205
Represents data written to the internal memory of the CPU 20,
Details of the inter-CPU interface will be described later.

As mentioned above, MCPUIO and 5 CPU
20, a digital musical tone signal is generated. The generated result is M
From CPUlo, right DAC100R and left DAC100L
The signal is sent to a digital-to-analog converter (DAC) 100 consisting of a digital-to-analog converter (DAC) 100, where it is converted into an analog tone signal and output to the outside.

<Configuration of MCPU and 5CPU (Figs. 2 and 3)> Fig. 2 shows the internal structure of MCPUIO, and Fig. 3 shows the structure of 5CPU2.
The internal structure of 0 is shown.

In FIG. 2, the control ROM 102 stores a main program for processing various control inputs of the musical instrument and an interrupt processing program for generating musical tones. Program words (commands) in
In the specific embodiment, the program word length is 28 bits, and part of the program word is an address for storing the program word to be read next. ROM address control unit 1 as the lower part (intra-page address) of
14, but the program counter method may be used instead.
When the operand of the instruction from the control ROM 102 specifies a register, the AM address control unit 114
Specifies the address of the corresponding register in AM106. The RAM 106 is a group of registers constituting a calculation memory, and is used for general-purpose calculations, flag calculations, musical tone calculations, and the like. The ALU section (addition/subtractor and logic operation section) 108 and multiplier 110 are used when the instruction from the control ROMIO 2 is an operation instruction.

In particular, the multiplier 110 is used to calculate musical waveforms, and as an optimization for this purpose, it multiplies the first and second data inputs (for example, 16-bit data) to obtain data of the same length (16 bits) as the input. It is designed to be output. Above RA
M106, adder/subtractor lO8, and multiplier 110 constitute an arithmetic circuit. The operation control circuit 112 decodes the operation code of the command from the control R0M2O3 and sends control signals (indicated by CNTR) to each part of the circuit in order to execute the instructed operation. In addition, when executing a conditional branch instruction, the operation control circuit 112
detects the establishment of a branch condition based on the status signal S (for example, an overflow signal, a zero flag signal, etc.) from the ALU unit 108 and jumps the address to the branch destination address via the ROM address control unit 114.

In order to execute the musical tone generation program in the control ROM 102 at predetermined intervals, this embodiment employs a timer interrupt. That is, the interrupt generation section 116 having a timer (hardware counter) sends a control signal IN to the ROM address control section 114 at regular intervals.
T (interrupt request signal) is sent, and in response to this signal, the ROM address control unit 114 saves (holds) the address of the next main program instruction, and returns the address to the beginning of the interrupt processing program (subroutine) in which musical tones are generated. Set the address instead. This starts the interrupt processing program. Since there is a return instruction at the end of the interrupt processing program, when this return instruction is decoded by the operation control circuit 112, the ROM address control section 114 sets the saved address again and returns to the main program. . Furthermore, the control signal INT from the interrupt generating section 116 is D.
It is supplied to DACloo to determine the digital/analog conversion sampling rate of musical tone signals in AC100. Note that the interrupt generation unit 116 is M in the diagram.
Although it is depicted as an internal element of CPUIO, MCPUI
It requests O to stop the work it is currently doing and perform special processing, and is logically an external element (peripheral device) of the MCPU 10.

The clock generation circuit 136 is a master clock generation circuit (
2-phase master clocks CKI and CK from (not shown)
2, various timing signals (T1, T2) are applied to each part of the circuit including the operation control circuit 112.
, T3, TlCK1, T2CK2, T3CK3, etc.).

The remaining elements of FIG. 2 relate to the interface of MCPU 20 with external devices. 122 represents a gate as a path interface for connecting the MCPU internal path to the external memory access address MA (FIG. 1), and 124 represents a gate for connecting the MCPU internal bus to the external memory data bus MD. 126 is DA
It also represents a gate for connecting the MCPU internal bus to the C data transfer bus, and also includes an input port 118 and an output port 1.
120 is an interface for coupling the MCPU internal bus to an external input device. 128 is 5 CPU internal R
132 is a gate for connecting the MCPU internal bus to the AM addressing bus; 130 is a gate for connecting the MCPU internal path to the 5CPU internal RAM write data bus;
represents a gate for connecting the 5CPU internal RAM read data bus to the MCPU internal bus.

The 5CPU reset control unit 134 is a device for managing the operating period of the 5CPU 20. According to this embodiment, the 5CPU reset control unit 134 responds to the interrupt signal INT from the interrupt generation unit 116, and
A signal A indicating the start of processing by the PU 20 is generated. This signal A is the ROM address control unit 214 (third
ROM address control unit 214.
The address update operation starts, and the operation of the 5 CPU 20 (including sound source processing) starts. When the operation of the 5CPU 20 is completed, a signal B indicating the end of processing is generated from the operation control circuit 212 of the 5CPU 20, and this signal B is transmitted to the 5CP
It is sent to the U reset control unit 134. On the other hand, 5C
The PU reset control unit 134 inverts the signal A to stop the operation of the 5CPU 20, thereby stopping the operation of the ROM address control unit 214 of the 5CPU 20, and also outputs the 5CP signal indicating that the 5CPU 20 is stopped.
A U status flag signal is sent to the operation control circuit 112. The operation control circuit 112 is a control ROM 10
When executing the 5CPU status inspection command from 2, this 5C
By reading the PU status flag signal, the status of the 5 CPUs 20 can be detected.

In the block diagram of the 5 CPU 20 in FIG.
2.202a, 204.205.206.208.21
2.214.222, 224°236 are the second
Element 102.1 in the block diagram of MCPUIO in FIG.
02a, 104.105.106.108.110.1
This is an element corresponding to 12.114.122.124.136. However, the control ROM 202 of the 5 CPU 20 basically stores only a program for sound source processing, and allows the 5 CPU 20 to function as a processing device exclusively for sound source processing.

240 is RAM2 as a memory for calculation of 5CPU20
The data input to 06 is the data from MCPUIO (M
From CPUIO to gate 130, data bus D OUT
This is a RAM data-in switching unit that selects from data generated (computed) by the 5CPU 20 (data on the data bus DB from the ALU unit 208 or the multiplier 210). RAM data-in switching section 240
Its selection mode is controlled by signal A, and when signal A indicates "5CPU 20 in operation", 5CP
Select the data calculated by U20 and signal A is “5CPU
20 "Stopping", data from MCPUIO is selected.

The mode of the RAM address control unit 205 is also controlled by the signal A, and when the signal A indicates "5 CPU 20 in operation", the RAM address control unit 205 inputs the information on the path SA from the instruction output latch 202a of the control ROM.
Selected as the address of AM206, signal A is "5CP"
When "U20 is stopped" is displayed, information from the MCPUIO on the bus Ma is transferred from the MCPUIO to the RAM 20 via the bus game) 128 (opened by signal A).
Select it as address 6. Similarly, the mode of the write signal switching unit 242 is controlled by the signal A,
When the signal A indicates "5 CPU 20 in operation", the RAM read/write signal from the operation control circuit 212 of the 5 CPU 20 is selected and coupled to the read/write input R/W of the RAM 206, and the signal A indicates "5 CPU 20 in operation".
When "stopped" is displayed, the S from the MCPUIO operation control circuit 112 instead of the 5CPU 20 is displayed.
Select CPURAM read/write signal and write to RAM206
It is coupled to the read/write input R/W of.

Below, various features of this embodiment will be explained in more detail.

Multiple CPU sound source function (Figures 1 to 7, 9th to 11th
i! J)> FIG. 4 is a flowchart showing the operation of MCPUIO by the main program (background program) of MCPUIO, and FIG. 5 is a flowchart showing the operation of MCPUIO by the interrupt processing routine of MCPUIO activated by the timer interrupt signal INT.
FIG. 6 is a flowchart showing the operation of the 5CPU 20 by the program of the 5CPU 20 activated by the timer interrupt signal INT, and FIG. 7 shows the MCPUIO and 5C
It is a flowchart of the sound source processing which each PU20 performs.

As described with reference to FIGS. 1 to 3, the electronic musical instrument processing system of this embodiment is equipped with a plurality of CPUs consisting of an MCPUIO and 5 CPUs 20, and both CPUs cooperate to execute processing for the electronic musical instrument. do. In particular, the MCPUIO processes sound sources using an interrupt processing routine as shown in FIG. 5, and the 5CPU 20 processes sound sources using a program as shown in FIG. Perform various tasks for control.

In the main program flow shown in Figure 4, 4-1 is a process to initialize the system when the power is turned on, and the MCP
UIO clears RAM106 and RAM206, sets initial values such as rhythm tempo, etc. MCPU at 4-2
IO outputs a signal for key scanning from the output port 120, and receives the status of input devices such as W'll and function switches from the input port il8, thereby scanning the function key 1.
! Store the state of the Iwa key in the key buffer area of RAMI O6. In 4-3, the function key whose state has changed is identified from the new state of the function key obtained in 4-2 and the previous state, and the instructed function is executed (for example, setting the musical tone number, setting the envelope number) set, rhythm number set, etc.), 4-4 has changed from the latest state of the t11 board obtained in 4-2 and the previous state! ! In the 0th order 4-5, which identifies (key press, key release), key assignment processing for the sound generation process 4-9 is performed from the processing result of 4-4.In 4-6, the demo performance key is assigned using the function key. External memory 9 when a key is pressed
By sequentially reading and processing demo performance data (sequencer data) from 0 to 1, key assignment processing and the like for one sound generation processing 4-9 are performed.

In step 4-7, when the rhythm start key is pressed, rhythm data is sequentially read out from the external memory 90, and sound generation processing 4 is performed.
Flow-period timer processing 4-8 performs key assignment processing for Flow-period timer processing 4-8, which performs key assignment processing for Flow-period timer processing 4-8. This is obtained by counting the number of timer interrupts (this counting process is performed in interrupt timer processing 5-2, which will be described later). 0 sound processing to obtain the reference value In 4-9, 4-
5. From the data set in 4-6.4-7, perform various calculations to actually produce musical tones, and store the results in RAM.
106, set in the sound source processing register (FIG. 11) in the RAM 206. 4-10 is a preparation process for the next main flow pass, in which the NEW ON state indicating a change to the key pressed state obtained in the current pass is set to ON, or the NEW indicating a change to the key released state is set to ON. Processing such as changing the OFF state to OFF is performed.

Interrupt signal INT from interrupt generation section 116
When this occurs, the MCPUIO interrupts the main program being executed and executes the interrupt processing routine shown in FIG. 5, and the 5CPU 20 executes the program shown in FIG. Here, the MCPUIO generates a musical tone signal in the flow shown in FIG. 5, and the 5CPU 20 generates a musical tone signal in the flow shown in FIG.

Specifically, the MCPUIO generates, accumulates, and stores musical waveform data for each channel at 5-1. Previously, horizontal and vertical processing was performed using sound source circuit hardware.
MCPUIO in the next interrupt processing timer processing 5-2
takes advantage of the fact that interrupts occur at regular intervals, and increments the flow cycle timer register (in RAM 106) by 1 each time it passes. MCPUIO at 5-3
checks whether the sound source processing 6-1 of the 5CPU 20 has been completed, and if it has been completed, proceeds to 5-4 and processes the 5CP
The musical tone waveform data on the RAM 206 generated in U20 is read into the RAM 106.

Then, at 5-5, the MCPUIO outputs the musical tone waveform data generated by the MCPU 10 and the musical tone waveform data generated by the 5CPU 20 to the DACl 00.

Details of the sound source processing 5-1.6-1 are shown in FIG. 7. In this example, each CPU (MCPUIO 1 SCPU 20) can generate musical waveform data for 8 channels,
As a whole, the system can generate musical waveform data for 16 channels. 7-1, remove the waveform addition RAM area (in RAM 106, RAM 206)! , +7L,
In steps 7-2 to 7-9, sound source processing for each channel from the first channel to the eighth channel is sequentially executed. At the end of each channel sound source processing, the tone waveform value of the channel is added to the data in the waveform addition RAM area.

Next, an example of channel sound source processing will be described with reference to FIGS. 9 to 11. In this example, the PC to read out the waveform
M) method of musical sound synthesis is adopted (other musical sound synthesis methods, such as FM synthesis, are also possible, and this invention is not limited to a specific musical sound synthesis method). Channel sound source processing can be broadly divided into envelope and Processing (9-1 to 9-7)
and waveform processing including envelope addition (9-8 to 9-2
1). Each CPU (MCPUIO1SCPU
20) is a group of sound source processing registers for the channel when executing channel sound source processing, that is, as shown in FIG.
y, current envelope, address addition value, loop address, end address, start address and current address, and update the desired register. The envelope should be added to the basic waveform for amplitude modulation, and consists of several segments (steps) as a whole. Envelope ΔX timer and I
In the sound generation process 4-9 of the MCPUIO main program (Figure 4), this information is updated each time the envelope value reaches the target value of the segment, and in the interrupt processing routine (Figures 5 and 6). These envelope parameters are only referenced, except for the timer for envelope Δχ. The envelope ΔX represents the envelope calculation cycle, the target envelope represents the target value of the envelope in the current segment, the envelope Δy with addition/subtraction flag represents the change in the envelope for each calculation cycle, and the current envelope represents the current envelope value. The addition value, loop address, end address, and start address/current address are address information for the basic waveform stored in the external memory 90, the start address is the start address of the basic waveform memory (in the external memory 90), and the loop address is the basic waveform Return destination address when repeatedly reading (first
(same as the start address in the θ diagram), the end address represents the end address of the basic waveform, the current address is the address representing the current phase of the basic waveform, and the integer part is the storage location that actually exists in the basic waveform memory. , the decimal part of which represents the deviation from this memory location,
The address addition value is directly proportional to the pitch of the four musical tones generated by the value to be added to the current address at each time interval of the timer interrupt processing routine.

In detail, in 9-1, the envelope foot calculation period ΔX
Increment the timer register for comparison with each interrupt, and when it matches △X in 9-2,
Test the addition/subtraction flag (sign bit) of the envelope displacement data Δy to determine whether the envelope is rising or falling, and subtract or add the current envelope in steps 9-4 and 9-5, respectively.9- At step 6, check whether the current envelope has reached the target envelope value,
If it has been reached, set the target level in the current envelope. This causes the next envelope step data to be set in the main program's sound generation process 4-9. Furthermore, when the current envelope of zero is read in the sound generation process 4-9, it is processed as the end of sound generation.

Next, waveform processing 9-8 to 9-21 will be described. In waveform processing, the integer part of the current address is used to read the waveform data of two adjacent addresses from the basic waveform memory.
The expected waveform value for the current address indicated by (integer part to decimal part) is obtained by interpolation. The reason why interpolation is necessary is that the waveform sampling period due to timer interrupt is constant, and the address addition value (pitch data) spans a certain range in application to musical instruments. (If waveform data is prepared for the original sound, there is no need for interpolation, but this would result in an unacceptable increase in storage capacity.) Since the timbre deterioration and distortion caused by interpolation is more pronounced in the high frequency range, it is necessary to record the original sound at a faster rate than the recording sampling rate of the original sound. In this embodiment, it is preferable to reproduce the original sound (4-4
) The playback cycle is doubled (Figure 10), so when the address addition value is 0.5, an A4 sound can be obtained. In this case, the address addition value is 0.529 for A#4, and 1 for A3. These address addition values are stored as pitch data in the control data/waveform external memory 90, and when a key is pressed, in the sound generation process 4-9, the pitch data corresponding to the key and the waveform start address of the selected tone, The waveform end address and the waveform loop address are set in corresponding registers of RAM 106 or RAM 206, ie, address addition value register, start address/current address register, end address register, and loop address register.

For reference, in Figure 1O which shows interpolated waveform data with respect to time, white circles indicate waveform data values stored in the storage location of the basic waveform memory, and X marks indicate output samples containing interpolated values.

There are various interpolation methods, but here we use linear interpolation. In detail, first, in step 9-8, an address addition value is added to the current address to obtain a new current address. At 9-9, compare the current address and end address,
If current address>end address, 9-10.9-
By 11.

When the current address is the end address, the next physical (address) or logical (operational) address is calculated in steps 9-12, and the basic waveform memory is accessed using the integer part in steps 9-14, and the next address is accessed in steps 9-14. Obtain waveform data. The loop address is operationally the next address after the end address. That is, in the case of FIG. 10, the illustrated waveform is repeatedly read out. Therefore, when the current address = end address, read the waveform data of the loop address as the next address (9-13), 9-15.9-16,
Access the basic waveform using the integer part of the current address and read the current waveform data. Next, subtract the current waveform value from the next waveform value in steps 9-17, and add the decimal part of the current address to the difference in steps 9-18. By multiplying and adding the result to the current waveform value in step 9-19, a linearly interpolated value of the waveform is obtained. This linearly interpolated data is multiplied by the current envelope value to obtain the musical tone data value of the channel (9-20), and it is added to the contents of the waveform addition register to accumulate the musical tone data (9-21). The digital musical tone data accumulated in the register is sent to DACloo in step 5-5 of the timer interrupt processing routine (FIG. 5). In this regard, in FIG. 1 the DAC 100 is connected to the right DA to obtain stereo output.
It consists of C100R and left DAC100L.

In this case, it is preferable to decide which of the left and right DACs to assign each of the sound source channels processed by the MCPUIO and 5CPUs 20. Specifically, the sound source data for each channel is stored on the internal RAM 106.206 and the selected DAC It also has two waveform addition areas, namely, a waveform addition area for the left DAC and a waveform addition area for the left DAC.
Provide an area for waveform addition. In addition, in the step corresponding to 7-1, each waveform addition area for the left and right DACs is cleared, and after the processing in 9-20, the DAC assigned to the processing channel is determined from the selected DAC instruction data, and the corresponding Add the musical waveform data of the processing channel to the waveform addition area. Then, in a step corresponding to step 5-4 of the interrupt processing routine of the MCPUIO (FIG. 5), the musical waveform data for the left DAC and the musical waveform data for the right DAC generated by the 5 CPU 20 are respectively transferred to the musical waveform data for the left DAC generated by the MCPUIO. Add the musical waveform data to the musical waveform data for the right DAC, and add the addition results for the left DAC and right DA.
C musical tone waveform data in steps corresponding to 5-5,
The signals are sent to the left DAC 100L and right DAC 100R, respectively.

In this way, the electronic musical instrument processing device of this embodiment uses the MCPU
It has multiple (7) CPUs, IO and 5 CPUs, and 20 CPUs.
Each CPU can execute sound source processing according to a built-in program. In addition, in the example, one 5
Although it uses a CPU, multiple 5CPs perform sound source processing.
You may make it provide U.

<5CPU operation start/end function (FIGS. 12 to 15, FIGS. 2 to 6, and FIG. 8)> If not yet implemented, the MCPUIO has a function of managing and grasping the operation period of the 5CPU 20.

For this purpose, (a) MCPUIO is the timer interrupt generator 11.
When an interrupt signal is generated from the SCPU 6, the operation of the 5CPU 20 is started using this as a signal, and the 5CPU status flag referred to by the operation control circuit 112 of the MCPUIO is set to "SCPU in operation".

(b) When the SCPU 20 completes the operation (sound S process), it responds to this and shifts to the stopped state, and the MCPUloi
, m operation completion signal is sent, and the 5cPU status flag referred to by the operation control circuit 112 of MCPUIO is set to “5”.
Set to "CPU stopped".

Referring to FIGS. 2 to 6, MCPUlo interrupts the interrupt generation section 1 during execution of the main program (FIG. 4).
When an interrupt signal is received from 16 (Fig. 2), RO
The main program is interrupted via the M address control unit 114, and a timer interrupt processing routine shown in FIG. 5 is executed to generate musical tones. Furthermore, in response to the interrupt signal, the MCPUIO sends a 5CPU operation start signal A to the 5CPU 20 via the 5CPU reset control unit 134,
In response to this, the 5CPU 20 controls the ROM address control unit 21.
4 to execute the program for musical tone generation shown in FIG.
The M address control section 204, the RAM data-in switching section 240, and the write signal switching section 242 also have 5 CPUs 20.
(set for its own operation), upon completion of this program, the 5CPU 20 starts the operation control circuit 2.
12 generates an operation end signal B. This signal B is 5C
It is sent to the PU reset control unit 134, and in response, the 5C
The PU reset control unit 134 inverts the signals A and B to stop the operation of the 5 CPU 20. Upon receiving the inverted 0 signal A, the PU reset control unit 134 inverts the 5 CPU 20's 1'? OM address control unit 214
The address update operation of 5 CPU 20 stops and the 5 CPU 20 stops. Also, signal B is M as a signal indicating "5 CPU is stopped".
It is given to the CPUIO operation control circuit 112. When executing the 5CPU status check command shown in 5-3 of the MCPUIO interrupt processing routine (Figure 5),
The operation control circuit 112 of MCPUIO is 5CP
Read U status flag B, flag B is “5 CPUs are stopped”
Therefore, the sound source processing by the 5th CPU 20 (6th
When step (FIG.) has been completed, the MCPUIO advances to 5-4 and reads the tone waveform data generated by the 5CPU 20.

MCPUIO gives a return command signal to the main program from the operation control circuit 112 to the ROM address control section 114 when the interrupt processing routine shown in FIG.

FIG. 8 shows the flow of the operation of this embodiment along the flow of time, and A to F are fragments of the main program. 5A~5
F represents the MCPU interrupt processing routine in FIG. 5, and 6A to 6F represent the 5CPU interrupt processing routine in FIG.
When T occurs, MCPUIO interrupts the program being executed, interrupt processing is started in each CPU10120, and parallel processing of sound sources is executed.

Figure 12 shows in detail the configuration for realizing the operation start and end functions of the 5 CPUs mentioned above, and Figures 13 to 15 show time charts of the operations.In the time chart of Figure 13, CKI, CR2 are MCPUIO and 5CPU2
This is a two-phase master clock input to clock generation circuits 136 and 236 at 0, and from these master clocks CK1 and CR2, the clock generation circuit 136
Three-phase clocks Tl, T2, and T3 are generated that provide basic timing for UIO operations. The repetition period of this three-phase U-tsuku is a machine cycle (the shortest instruction execution time)
Establish. Clocks TlCK1, T2CK2, T3CK
3 are respectively T1 and CKI, T2 and CR2, T3 and C
This is an AND signal of R3. The operation latch signal is a signal for causing the instruction output latch 102a of the control ROM 102 of the MCPUIO to latch an instruction from the ROM 102.

Although not shown in FIG. 13, the clock circuit 236 of the 5CPU20 also generates a similar clock signal (see FIGS. 3 and 25). Note that a common clock generation circuit may be used for the MCPUIO and the 5CPtJ20. .

In FIG. 12, the right side of the dotted line 16 is the 5 CPU 20, and the left side is the MCPUIO. Among the elements on the left, latch Ll, latch L2, and gates 1142 to 1154 are MC
This is a circuit element included in the ROM address control unit 114 of the PUIO (FIG. 2). Latch L1 contains ROM102 address information AN of the next instruction to be executed by MCPUIO.
(information contained in the current instruction from ROM 102) is latched with clock TICKI. Main program (4th
During the execution of FIG. 2, the output of latch Ll is input to the ROM address decoder 104 of MCPUIO as the next address BN. That is, the output of latch L1 is output from inverter 1144.
．． The address input BN passes through tri-state inverter gate 1146 (enabled) to ROM address decoder 104. Here, the interrupt generation unit 116
When an interrupt signal INT is generated from
From the OR gate 1154 receiving NT, the inverter 11
48 is applied to turn off (high impedance) the tri-state input gate 1146 at the output of latch L1, and in turn, a signal from OR gate 1154 turns off the interrupt low/return address selection gate. )115
The 3-state input/-1 target gate) 1152 on the output side of the gate 1150 transfers the output of the gate 1150 to the ROM address decoder 104.
1150 is the interrupt signal INT and latch L passed through the address input BN.
It consists of a group of NOR gates that receive output signals from 2,
Entry point of the interrupt processing routine (Figure 5) when the "H" interrupt signal INT is generated.
It outputs a signal of all "0" representing
” is input to the ROM address decoder 104 of the MCPU as the signal BN. Then, the next operation latch signal causes the instruction to be sent from the control ROM 102.
The first instruction of the interrupt processing routine is fetched into the output latch 102a.
Control passes to the interrupt handling routine.

Further, the interrupt signal INT from the interrupt generating section 116 passes through the AND gate (AND gate) 1142 at the timing of the clock T2CK2, and operates the latch L2 as a latch signal. As a result, latch L2 latches (saves) the address of the next instruction of the main program on bus AN.
to interrupt the main program.

Furthermore, the interrupt signal INT from the interrupt generation section 116 is supplied to the 5 CPU reset control section 134.

The 5 CPU reset control unit 134 includes a D flip-flop 1342 and a NAND gate 134 coupled as shown in the figure.
4, R-S flip-flop 1346. During main program execution, R-S flip-flop 1346
is in the reset state (Q==“L”). Although not shown, the R-S flip-flop 1346 is initialized to the reset state when the system is powered on.

The interrupt signal INT is taken into the D flip-flop 1342 at the timing of the clock T2CK1, and the NAND gate)1 is taken in at the timing of the next clock TICKI.
344 and is inverted and outputted, setting an R-S flip-flop 1346. As a result, the Q output of the R-S flip-flop 1346, that is, the signal A changes from "H" to "L".
”, and the Q output, that is, the 5 CPU status flag, becomes “L”.
” (indicates that the SCPU is stopped) to “H” (SCP
(U indicates in operation). Signal A is 5 CPU 20
It is input as a reset release signal (enable signal of latch L3) to latch L3 for latching the address SAN of the next instruction in . As a result, the latch L3 inputs the address of the first instruction of the 5 CPU program (FIG. 6) on the bus SAN to the ROM address decoder 204 of the 5 CPU 20 as SBN at the timing of the next claw 2 TlCK1. In this manner, the operation of the 5 CPU 20 is started in response to the interrupt signal INT from the interrupt generating section 116, and the sound source processing shown in FIG. 6 is executed.

When the 5 CPU 20 executes the last command of sound source processing, the 5
An operation end signal (return command signal) SRT is generated inside the operation control circuit l12 of the CPU 20. This signal SRT is taken into the D flip-flop 2122 at the timing of clock 72CK1, and then the primary TI
It is inverted by the NAND gate 2124 operating at the CKI timing (latch timing of the next dummy instruction), and resets the R-S flip-flop 1346 of the 5 CPU reset control unit 134 as a low pulse operation end signal B. As a result, the output of the R-S flip-flop 1346, that is, the signal A switches from "L" to "H", and Q
The output, that is, the 5CPU status flag switches from "H" indicating that the 5CPU is in operation to "L" indicating that the 5CPU 20 is stopped. The “H” level signal A (reset signal) inhibits the operation of the second circuit L3, latches it, and outputs three outputs, that is,
The input of the address decoder 204 is the dummy instruction (Nor
(instruction) address. At this time, the input bus SAN of latch L3 is connected to the 5 CPU sound source processing program (6th
The address information (included in the Nor instruction word) of the first instruction in FIG.

The MCPUIO checks the level of the 5CPU status flag via the operation control circuit 112 when executing the 5CPU status check instruction 5-3 of the interrupt processing routine (FIG. 5), and determines whether the 5CPU is stopped, that is, the sound source processing of the 5CPU 20 is completed. After checking, the musical sound waveform data that is the processing result of the 5 CPU 20 is read from the RAM 206 to the RAM 106 (5-4), so that the MCPUIO
20 correct processing results can be efficiently obtained.

MCPUIO generates a pulse of the return command signal RT from the operation control circuit 112 when executing the last instruction of the interrupt processing routine. This signal pulse R
T passes through the OR gate) 1654 and the inverter 1148 to temporarily turn off the address gate) 1146 on the output side of the latch Ll, and instead outputs the interrupt input logic connected to the latch L2.
The address gate (1152) on the output side of the return address selection gate (1150) is temporarily opened. At this point, the interrupter/return address selection gate (1150) is connected to the interrupted main It works as an inverter that inverts the address of the program's instructions and passes it through (this game)
The inverted output of 1150 is again inverted by signal pulse RT in a three-state gate 1152 which acts as an inverter. As a result, the address of the instruction of the interrupted main program is input to the ROM address decoder 104 of the MCPUIO, and the instruction is taken out from the control ROM 102 via the instruction output latch 102a in response to the next operation latch signal. In this way, control of MCPUIO returns to the main program.

As described above, the electronic musical instrument processing device of this embodiment has the MCP
5 CPUs manage the operation period of 5 CPUs 20 by UIO.
By providing a simple management interface configuration such as the reset control unit 134, this can be done efficiently and reliably.

Multiple data transfer> In certain applications that use the CPU,
updates multiple data during execution of the main program (first program), and updates the interrupt processing routine (
When the second program) is executed, these multiple pieces of data are referenced for the purpose of processing. This is the problem of passing data from the main program to the interrupt processing routine. Such multiple data must be updated in the main program before the main program is interrupted by the interrupt handling routine, or interrupted when the main program has updated only part of the multiple data. If the CPU control is transferred to the interrupt processing routine, the processing result of the interrupt processing routine will be incorrect.

In the case of the electronic musical instrument processing device of this embodiment as well, a plurality of messages are passed from the MCPUIO main program (Fig. 4) to the MCPUIO timer interrupt processing routine (Fig. 5) (and the 5 CPU 20 timer interrupt processing routine shown in Fig. 6). Data calculation 6. Envelope ΔX (Enhero 7' performance XM period), Envelope Δ with adjustment/subtraction
An example is an envelope parameter consisting of F (envelope change) target envelope. The external data memory 90, which is a data source, stores envelope parameters for each envelope segment (eg, attack segment, decay segment, sustain segment, etc.). The main program of MCPUlo, in the sound generation process 4-9, reaches the target value of the envelope detected in the key press (note-on) or channel sound source processing (Figure 9) of the interrupt processing routine (9-6,
9-7), the envelope parameters (new target envelope, envelope Δy with addition/subtraction flag for envelope ΔX1) for a predetermined segment are retrieved from the external data memory 90 and stored in the MCPU internal RAM 1.
It is necessary to update the envelope parameter consisting of a plurality of data by setting it in the corresponding channel sound source processing register of 06 (or 5 CPU internal RAM 206). Such a plurality of data must be updated in the main program before the main program is interrupted by the interrupt signal 411NT from the interrupt generating section 116.

In order to solve the problem of multiple data transfers (updates), this embodiment discloses two solutions. 1st
The solution to this problem is an interrupt masking method that masks interrupts during data updating so that the execution of the main program's data update instructions is not interrupted.
The solution to this problem is a one-instruction method that utilizes the ability to execute multiple data transfers with one instruction.

Interrupt mask method (16th, 17th, 2nd to 7th
(Figure) According to this method, the interrupt from the interrupt generation unit 116 is masked while data is set in the channel sound source register group of the internal RAM by the data update command group in the main program, especially in the sound generation process 4-9, and the interrupt from the MCPUIO The main program is to control (Figure 4)
The transition to the interrupt processing routine (FIG. 5) is prohibited.

Figure 17 shows envelope processing including multiple data transfers (
Fig. 16 shows the hardware related to the interrupt mask.

In FIG. 17, the MCPUIO checks in step 17-1 whether the current envelope of the designated sound source channel has reached the target envelope. If this is reached, the MCPUIO proceeds to step 17-2, retrieves the envelope parameters related to the next envelope parameters from the external data memory 90 (FIG. 1), that is, the new target envelope, the envelope Δy with addition/subtraction flag, and the envelope ΔX, and stores them in the internal fiRAM 106. mode into the transfer buffer.

Here, the transfer buffer is an intermediate storage unit between the data source and the data destination, and is used by the interrupt handling routine (9th
Since this is a RAM area that is not referenced by (Figure), an interrupt mask is not required at this point. The reason for providing the transfer buffer is that the data source memory 90 is the MCPU.
This is because the external memory is shared by the IO and the five CPUs 20, and its data access time is longer than the data transfer time between internal RAMs. The function of block 172 is processed by sequentially executing a plurality of data transfer instructions from external data memory 90 to internal RAM 100.

Data transfer from the transfer buffer to the channel sound source register group (referenced in the interrupt processing routine) is executed in block 17-4. To prevent MCPUIO control from shifting to the timer interrupt processing routine (Figure 5) during this data transfer (or
In order to prevent control of the CPU 20 from transferring to the program of FIG. 6), MCPUlo executes an interrupt masking instruction in block 17-3 prior to block 17-4. During execution of this interrupt mask command, a low active mask signal MASK is generated from the operation control circuit 112 of the MCPUIO. This mask signal MASK acts to mask the interrupt signal INT from the interrupt generating section 116 and prohibits control from shifting to the interrupt processing routine (FIGS. 5 and 6). For this purpose, in Figure 16,
A mask release special unit 150 coupled to the interrupt generating unit 116 is provided. The mask release special unit 150 includes an R-S flip-flop 1502 and an AN
It includes a D gate 1504 and a D flip-flop 1506.

When the mask signal MASK is at the "H" level indicating mask release, the R-S flip-flop 1502 is set by the interrupt signal INT from the interrupt generating section 116, and its output is the AND enabled by the "H" MASK. It passes through the gate and is taken into the D flip-flop 1506 at the timing of TICKI, and the output of the D flip-flop 1506 is input to the ROM address control unit 114 of the MCPUIO as the actual interrupt signal A-INT. As a result, as described in the 5 CPU operation start/end functions, an interrupt processing routine (see FIG. 5) is sent from the gate 1152 of the ROM address control unit 114 to the ROM address decoder 104.
The address of the entry point is entered, and
The address of the next main program instruction is saved from path AN to latch L2, control of MCPUIO is transferred to an interrupt processing routine, and the main program is interrupted. Further, the signal A-INT is input to the 5CPU reset control section 134, and as a result, the program (FIG. 7) operation of the 5CPU 20 is started as described in the 5CPU operation start/end function. D flip flop 150
The H level output from 6 is the R-S flip flow, P1
502 is reset, and as a result, the output of the D flip flow 1506 (output of the mask release special unit 150) is switched to the L level at the next TICKI timing.

On the other hand, when the low active mask signal MASK is input from the operation control circuit 112 to the mask release special unit 150 by executing the interrupt mask command as shown in 17-3 in FIG. 17, an interrupt occurs. The interrupt signal from section 116 is masked by AND gate 1504. As a result, the mask release special unit 1504 sets its output A-I NT to the "L" interrupt disable level while the mask signal MASK is low active, allows the ROM address control circuit 114 to continue its normal operation, and controls the MCPUIO. Allows control of the main program to continue.

Therefore, the execution of the transfer command group (and the clear command for the envelope Δχ timer) shown in block 17-4 is as follows:
Even if the interrupt signal INT is generated from the interrupt generation unit 116 during execution, the interrupt processing routine is not interrupted (FIGS. 5 and 6).
can refer to envelope parameters that have been updated correctly, and can obtain correct calculation results (music waveform data).

Thereafter, MCPUIO executes the interrupt mask release instruction shown in block 17-5. As a result, the signal MASK supplied from the operation control circuit 112 to the mask release special unit 150 switches to the "H" level indicating mask release. Block 17- containing multiple data transfers
4, if an interrupt signal is generated from the interrupt generation unit 116, the output of the R-S flip-flop 1502 of the mask cancellation special unit 150 causes an interrupt request to be issued after the mask cancellation command is executed. If accepted, the main program is interrupted as described above, and control is transferred to the interrupt processing routine.

One-instruction method (Figures 18 to 21) This method stores multiple data in the main program (Figure 4) from the internal RA referenced by the interrupt processing routine.
To set it in the M area, a single instruction called a long instruction for bulk transfer of multiple data is used, and the MC is sent to the interrupt processing routine until the execution of the long instruction is completed.
This is to prevent PUIO control from shifting.

A CPU capable of transferring a plurality of data with a single instruction (long instruction) is disclosed, for example, in Japanese Patent Publication No. 47612/1983, and this technique can be applied to this embodiment. Special Public Service 1986-
According to No. 47612, long instructions can be applied to transfer between multiple registers at consecutive addresses (e.g., registers AO to A3 to registers BO to B3) (here, register means one memory location in RAM). and A and B are R
Represents the upper address of AM, that is, the row address, and is 0.3
represents the lower address of RAM, that is, the column address),
The long instruction word from the control ROM (corresponding to element 102 in this embodiment) includes the source register row address (A in the above example), the destination register row address (B), and the first data transfer. The information includes the column address (0) of the register related to the last data transfer and the column address (3) of the register related to the last data transfer. The RAM address control unit (corresponding to element 105 in this embodiment) is configured to be suitable for executing long instructions, and is configured to change one column address from the column address of the first transfer to the column address of the last transfer every time data is transferred. A counter that updates increments (its output is stored in RAM)
(sequentially added to the column address input of ) and the column address value of the last data transfer to detect that all data transfers have been completed. When they match, a long instruction execution completion signal is generated. and a matching circuit.

In the following description, it is assumed that the main program of the control ROM 102 of this embodiment includes the above-mentioned long instructions, and the RAM address control W units 105, 205
It is assumed that the configuration is such that the execution of long instructions can be applied as described above.

Figure 18 shows that during the execution of a long instruction, the interrupt signal IN
A block diagram of the hardware including a circuit that prohibits interruption of the main program by T is shown in Figure 19.
A memory map of AM is shown, and FIG. 20 shows a comparison of operations between a long instruction (single transfer instruction) and multiple transfer instructions.
FIG. 21 shows a flowchart related to envelope parameter transfer using a long instruction.

In FIG. 18, a transfer termination special unit 152 is coupled to the interrupt generating unit 116. This circuit 152 prohibits interruption of the main program by an interrupt signal during execution of a long instruction. The transfer end special unit 152 includes an RS flip-flop 1522 and an AN connected as shown in the figure.
Consisting of a D gate 1524 and a D flip-flop 1526, the output of the D flip-flop 1526 (output of the transfer end special unit 152) actually acts on the interrupt signal A.
- ROM address control unit 214 and 5 CPU as INT
It is coupled to the reset control section 134. AND game) 1
While the signal ~LONG input to the D flip-flop 1524 is "L", even if the interrupt signal INT is generated from the interrupt generating section l16, the output of the D flip-flop 1526 is "L".
”, and the ROM address control unit 214 and 5CP
The U reset control unit 134 is not affected by the interrupt signal INT. Here, the signal ~LONG is a signal that becomes “L” during the execution of a long instruction, and the RAM address control unit 104 is activated upon completion of execution of the long instruction. It returns to "H" in response to the long instruction execution completion signal generated from the matching circuit. When the level of @#~LONG is “H”, the interrupt signal INT from the interrupt generation unit 116
is 41 at the end of transfer! It acts on the ROM address control section 214 and the 5 CPU reset control section 134 through ts2,
The CPUIO control is transferred from the main program (Figure 4) to the interrupt processing routine (Figure 5), and the 5CP
The program operation of U20 (FIG. 6) is started.

When applying the one-instruction method to update envelope parameters, the channel sound source processing subroutine (Fig. 9) of the interrupt processing routine (Figs. 5 and 6) refers to the envelope processing subroutine (Fig. 21) of the main program. The envelope parameters set (updated) by (Figure 1)
When updating the envelope parameters in (21-
1), from external data memory 90 to internal RAM 106.2
Since direct transfer to the channel sound source data area of channel 06 is not desirable, the envelope parameters from the external data memory 90 are temporarily transferred to the transfer buffer area in the internal RAM 106 (2l-2), and then transferred from the transfer buffer area. Move to channel sound source data area (21-3)
.

The above-mentioned long command is used in the data transfer process 21-3 from the transfer buffer area to the channel sound source data area. In order to apply the long command, the transfer buffer area needs to be a continuous area on the RAM, and similarly the channel sound source data area of the envelope parameter needs to be a continuous area. An example of this is shown in FIG. 19. Here, the envelope parameter transfer buffer area is mapped to the continuous area of registers x4 to X7 (7), and the 1-channel sound source data area for the envelope parameters is mapped to the registers A4 to A7.
mapped to a continuous area. Therefore, when it is necessary to update envelope parameters in one channel, it is sufficient to execute a long instruction to transfer registers x4 to x7 to registers A4 to A7 at 21-3.
While this instruction is being executed, even if the interrupt signal INT is generated from the interrupt generation unit 116 as described above, the long instruction completion wait function of the transfer end special unit 152 will not interrupt the interrupt until the long instruction is completed. The effect of the signal does not affect the ROM address control unit 114.5 CPU reset control control unit 4 (see FIG. 20(B)).
As a result, the interrupt processing routine starts after all the envelope parameters in the channel sound source data area have been changed to the correct update values, so the calculation result (music waveform data) shows the correct value and error-free operation is guaranteed. Ru.

On the other hand, if you try to perform the transfer processing function shown in 21-3 by executing multiple transfer instructions (one envelope parameter is transferred for each - instruction),
During the transfer, for example, if an interrupt signal INT occurs during the execution of transfer instruction 1 as shown in FIG. 20(A), the first instruction of the interrupt processing routine will be executed instead of transfer instruction 2 in the next machine cycle. As a result, the processing result (music waveform data) of the interrupt processing routine becomes an incorrect value.

- 1 for multiple data transfer (update) processing using command method
There is also the advantage that there is no need to execute an interrupt mask instruction or an interrupt release instruction as shown in 7-3.17-5, and transfer processing can be executed in the shortest possible time without overhead.

As a modified example, a transfer termination special unit 1 as shown in FIG.
52, the control ROM 10 is used during execution of a long instruction.
2. Means for inhibiting the operation of the instruction output latch 102a that fetches instructions from the control ROM 102 may be used.
By the mode signal (indicating that the instruction is long) included in the long instruction word given via a,
If a circuit is provided in the operation control circuit 112 that prohibits the generation of the operation latch signal applied to the instruction output latches 102a and 202a and generates the operation latch signal in the next machine cycle in response to the execution completion signal of the long instruction. Interrupt signal IN
Even if T occurs during the execution of a long instruction, the control ROM 10
2. Since the first instruction word of the interrupt processing routine from 202 is not fetched into the instruction output latches 102a, 202a (and therefore not executed) until the execution of the long instruction is completed, the same effect as in the embodiment can be obtained.

<5 CPU access function from MCPU> The device of this embodiment has access from MCPUIO to internal RAM 206 of SCPU 20.
It has the ability to access (read or write) data at high speed.

This problem is generally understood as a data access problem between a plurality of CPUs.In the 0GE technology, this kind of inter-CPU data access takes a long time. In the prior art, a request signal is given from a CPU requesting access to a CPU requesting access. In response to this request signal, the CPU to which access is requested cannot immediately generate an acknowledge signal that permits data access from the requesting CPU, but delays generation of the acknowledge signal until the operation in progress is completed. Therefore, the conventional inter-CPU data access method has become one of the obstacles in applications requiring high-speed processing.

This embodiment discloses two solutions for high-speed inter-CPU data access, namely, a 5CFU stop mode usage method and an instantaneous forced access method.

5-CPU stop mode utilization method (FIGS. 22, 2, and 3) This method utilizes the 5-CPU operation start/end function described above. With this function, the program operation of the 5CPU 20 (Fig. 6) starts simultaneously with the start of the interrupt processing routine (Fig. 5) in the MCPUIO, and
It ends before the PUIO interrupt processing routine ends. Therefore, while the main program (FIG. 4) is operating in the MCPUIO, the 5 CPU 20 is in the stop mode (reset state). In the stop mode as shown in FIG.
goes to "H" level indicating "5 CPUs are stopped". This signal A stops the operation of the ROM address control unit 214 in the 5 CPU 20 (FIG. 3), and the RAM address control unit 204 controls the RAM address control unit 202 from the control ROM 202 of the 5 CPU 20.
The operating mode is set so that the designated address of the 5 CPU internal RAM 206 is received from the MCPUIO by coupling it to the RAM address bus Ma via the pass gate 128 from the MCPUIO, instead of A to the M address 8th, and the switching unit 240 to RAM data 5 CPU 20 (7) The RAM 206 (7) is connected to the data bus D OUT which carries data from MCPUIO instead of the data bus DB which carries the operation result (ALU unit 208 output or multiplier 210 output).
), and the write signal switch 242 selects the read/write control signal C from the operation control circuit 112 instead of the read/write control signal from the CPU operation control circuit 212. Set to operating mode coupled to read/write control input. When stopped like this,
The 5 CPU 20 is placed in a state where it can access data by the MCPUIO.

Therefore, according to this embodiment, the MCPUIO can freely access the internal RAM 206 of the 5 CPUs 20 in the main program. This situation is shown in FIG. 22. Confirmation of the stopped state (sound source processing completion) of the 5 CPU 20, that is, inspection of the 5 CPU status flag from the 5 CPU reset control unit 134 in the MCPU operation control circuit 112, is performed by the interrupt processing routine of the MCPUIO (see FIG. 5). ), you only need to do it once (see 53),
Once the stop state is confirmed, the MCPUIO can access the internal RAM 206 of the 5 CPU 20 by executing the - instruction without needing to confirm again until the next interrupt signal INT is generated. Therefore, the time required for data access to the five CPUs 20 is significantly reduced compared to the conventional case.

Instant forced access method (Figures 23 to 25) This method allows 5 CPU data to be accessed from MCPUIO without going through the conventional procedure of requesting and approving access between MCPUIO and 5 CPU 20 for data access. Forcibly suspends the operation of 5 CPU 20 at the time of access,
Meanwhile, MCPUIO is 5 CPU 20 internal RAM 20
6. According to this method.

The MCPUIO can access the 5 CPUs 20 at high speed (by executing -instructions) without having to check the status of the 5 CPUs 20 at any time.

Block diagram of MCPUIO with such features and 5
The block diagrams of the CPU 20 are shown in FIGS. 23 and 24, respectively. This MCPU and 5CPU are the 5C
Elements related to the PU operation start/end function (5 CPUs in Figure 2)
23 and 24), but their illustration is omitted for simplification in FIGS. 23 and 24. In this case, it is sufficient to supply the 5CPU operation start/stop signal A from the reset control circuit 134 only to the ROM address control unit 214 of the 5CPU 20 (FIG. 24). FIG. 25 shows a time chart of operations related to instantaneous forced access of the MCPUIO and 5 CPU 20 shown in FIGS. 23 and 24.

When using the instantaneous forced access method, MCPUIO and 5CPU20 are separate clock generation circuits 136.236
Requires M. 5 Clock generation circuit 23 of CPU 20
6M stops its operation in response to a high active 5CPU access signal output from the operation-on control circuit 112M of MCPUIO when a data access command to 5CPU 20 is executed. In this regard, MCPUI
The clock generation circuit 136 of the CPU 20 and the clock generation circuit 236M of the 5 CPU 20 use a common two-phase master clock signal C.
K1. Although it receives CK2, the timing of the output clock is independent. In MCPUIO, clock generation circuit 1
Three-phase clock signals T1, T2 . One cycle of T3 defines a machine cycle (the shortest one instruction execution time), and in the 5 CPU 20, one cycle of three-phase clock signals STI, ST2, and Sr1 from the clock generation circuit 236M defines the machine cycle. .

In FIG. 25, before the 5CPU access signal is generated, the timing of the clock TI regarding MCPUIO matches the timing of the clock Sr1, not the clock STI regarding 5CPU20.
Other possible timing relationships between them are TI matching STI and T1 matching Sr1.

The 5 CPU access signal output from the operation control circuit 112 during execution of the 5 CPU access instruction in MCPUIO is generated by the clock generation circuit 23 of the 5 CPU 20.
In order to stop the 6M and stop the operation being executed by the 5 CPU 20, and to allow the MCPUIO to access the internal RAM 20B of the 5 CPU 20 during the stop, the bus gate 128.
It has a function of switching the operation mode of the address control unit 204, data-in switching unit 240, and write signal switching unit 242 from the ``MSCPU side'' to the ``MCPU side'' for the 5 CPU access signals. 204.240.242, D free, pflop 250 and A are used as control inputs to select the operating mode of 242.
The ND gate 252 is coupled to the ND gate 252 via a delay circuit. Under such accessible state, the MCPUI
O addresses the 5 CPU internal RAM 206 via the bus gate 128 and the RAM address control unit 204,
In the case of read access, the data output from the 5CPU internal RAM 206 is sent to the MCP via the bus gate 132.
The data is read into the U internal RAM 106, and in the case of write access, the write data is transferred to the data bus D OUT via the pass gate) 130, and then transferred to the 5 CPU internal RAM 206.
A write signal C is given to write data.

5 by the 5 CPU access signal from MCPUIO
When interrupting the operation of the CPU 20, it is necessary to ensure that the intermediate result of the operation is not lost, and after the 5CPU access signal is released, the 5CPU 20 can execute the remaining part of the operation using the intermediate result held in advance. It is necessary to do so. For this,
Latches 206a and 206b are provided to temporarily store data output from the 5CPU internal RAM 206. latch 2
06a is the operation number from RAM206 (@1 operand)
is latched at the timing of 5TICKI, and the latch 206
b checks the operand (second operand) from the RAM 206 at the timing of 5T2CK1.

An operation example will be described with reference to FIG. 25. In this example, M
CPUlo executes write access to the internal RAM 206 of the 5 CPU 20 while the 5 CPU access signal is at a high active level. In MCPUlo, the first time slot TI of this data write operation
During this period, transfer data (R
At the 0th time slot T2 to retrieve data (to be written to AM206), MCPUIO writes data to the 5CPU internal RAM.
Add and sing 206. At the last time slot T3, MCPUIO gives write signal C to 5 CPU internal RAM 206 and writes data to RAM 206, 5
On the CPU 20 side, the 5CPU access signal from MCPUIO changes to active when the 5CPU 20 (7) operation 2 moves to time slot ST2. This operation 2 is 5 CPU 20 RAM 2
This may be an instruction operation in which the operands and operands in 06 are operated on by the ALU unit 208 or the multiplier 210. The timeslot just before the 5CPU access time of MCPUlo (the first timeslot of John 2) STI-t'5CPU20 is the RAM
If no 5CPU access signal is generated from 0MCPUl0, which takes out the data of the arithmetic operation from IO6 and latches the data into the arithmetic operation latch 106a using TICKI, the 5CPU20 will read the data from the RAM 106 in the next time slot ST2. The operand is taken out and latched into the operand latch lOb, and in the last time slot ST3, the operation is executed by the ALU unit 108 or the multiplier 110 and written to the operand register of the RAM 106.Actually, as shown in the figure. In the first time slot of operation 2), 5 CPU access signals from MCPUIO are generated following STI. In this case, one solution is to use the remaining two time slots ST2 and S of operation 2.
The process to be executed at T3 is suspended until the 5CPU access signal is removed, that is, until the 5CPU access operation of MCPUIO is completed. Even with this method, MCPUIO performs operations that access 5 CPUs 20 for the shortest time (fflR in MCPUIO (7)).
It can be executed within FIIJ at the same time as accessing AM106, but it is optimal for 5CPU20 and M
Every time there is a 5 CPU access operation from CPUIO, the 5 CPU 20 operation is in time slot 3.
There will be a delay of one minute. Conveniently, MCP
The process executed in the first time slot TI of the UIO 5CPU access operation is a process that does not affect the 5CPU 20. By utilizing this feature, in the embodiment, even if a 5CPU access signal is given from MCPUIO, the 5C
The operation delay of the 5 CPUs 20 is made as short as possible by allowing the PU 20 to continue its own operation. In the example of Fig. 25, 5 CPU 20 is MCPU 1
At the opening of the first time slot T1 of the 5CPU data write operation of 0, the RAM 206 also takes out the data of the operand, and the clock 5T2CK1
is given to latch the operand. After that, 5CP
The operation of the U clock generation circuit 236 is stopped until the 5CPU access signal is removed, and the 5CPU 20 is placed in a wait state. During this waiting state, the elements 128, 264, 240 and 242 of the 5CPU 20 are switched to the "MCPU side" by the 5CPU 7 access signal.
Uloo) Time slot in SCPU data write operation) Processing related to T2 and T3 is executed and 5
Data from MCPUIO is written to the CPU internal RAM 206.

When the 5CPU access signal from MCPUIO is removed, the 5CPU clock generation circuit 236 resumes operation and changes the clock ST3 to "H".
By removing the U access signal, element 1 of 5 CPU 20
28.204.240.242 is returned to the kSCPU side, and the 5CPU 20 itself becomes operable.Then, the SCPU 20 returns to the kSCPU side in this time slot Sr1.
The calculation output of the ALU unit 208 or the multiplier 210 is stored in the RAM.
206 to perform the remainder of Operation 2.

As shown in the time chart of Figure 25, 5cPU20
(7) Each time an operation is accessed from MCPUl 0 to (7) SCPU7, the interruption is only for two time slots.

In addition, MCPUIO is 5CPU20 internal RAM206
For a read access operation to read data from the SCP
U internal RAM 206 is dressed 7 times, MCPU internal RAM 106 is addressed at time slot T3, and data from SCPU internal RAM 206 is taken into MCPU internal RAM 106 via bus gate 132.

As described above, according to the instantaneous forced access method, the MCPU
IO can access the internal RAM 206 of the 5CPU 20 in the same way as access to the MCPU's own RAM 106, and there is no need to execute a waiting time instruction.Furthermore, according to the instantaneous forced access method, the 5C
Interrupt the PU20 operation midway and open the MCPUI.
After O's 5 CPU access operations, the operation can be resumed from where it was interrupted. therefore,
MCPUIO does not need to check the status of 5CPU 20 before accessing 5CPU 20, and can freely access 5CPU 20 at any time, for example, during the included processing routine (FIG. 5).

Shared memory access conflict resolution function (Figures 26, 27, and 1) In Figure ls1, the external memory 90 is
It is a data memory shared by the MCPUIO and the 5 CPUs 20. Therefore, means for supporting multiple accesses to the external data memory 90, ie, accesses to the external data memory 90 from the MCPUIO and from the 5 CPUs 20, is required.

Furthermore, when the external data memory 90 is shared, it is desirable to allow MCPUI o and 5cptrzo to attempt to access the external data memory 90 at the same time. MCPUlo and 5CPU20. ! :(7) By providing a function to exchange usage rights (tokens) for the external data memory 90 between MCPUIO and 5CPU
20 may not access the external data memory 90 at the same time, but since the token procedure occupies the preparation time for accessing the external data memory, the total time required for accessing the external data memory becomes longer, which reduces efficiency. On the other hand, MCPUIO and 5CPU20
When allowing simultaneous access to the external data memory 90 by the external data memory 90, since the memory 90 itself cannot be physically accessed at the same time, a means is required to resolve access conflicts caused by simultaneous access.

In order to realize these means, as shown in Figure 1, MC
External memory address information from PUIO is coupled to the address input of external memory 90 via address bus MA, MCPU external memory address latch 30M, address switching circuit 40, and address conversion circuit 60, and data output from external memory 9o. is the data conversion circuit 70, M
CPU external memory data latch 80M, data bus MD
is coupled to MCPUIO via. On the other hand, 5CP
External memory address information from U20 is sent to address bus S.
A, 5 CPU external memory address switch 30S, address switching circuit 40, and address conversion circuit 60 are connected to the address input of external memory 90. Data output from external memory 90 is connected to data conversion circuit 70, SC
The PU external memory data latch 80S is coupled to the 5 CPU 20 via the data bus SD. And M.C.P.
Signals MCPU-roma and SCPU-ro representing external data memory access requests from UIO and 5CPU 20
The MCPU external memory address latch 30M is controlled by the memory device contention avoidance circuit 50 that receives the
External memory address switch 30S, address switching circuit 40, MCPU external memory data latch 80M, 5C
The PU external memory data latch 80S is controlled. This memory device conflict avoidance circuit 5° includes a function to avoid the above-mentioned access conflict.

FIG. 26 shows a block diagram of the memory device conflict avoidance circuit 5o, and FIG. 27 shows a time chart of operations regarding access conflicts.

In FIG. 26, the memory device contention avoidance circuit 50 receives an access request signal MCPU from MCPUIO as an input.
-roma, access request signal SC from 5 CPU 20
PU-roma, furthermore, MCPU reset signal MRES
and 5CPU reset signal 5RES (not shown in FIG. 1) are coupled. MCPU reset signal MRES
is set-reset circuit (R-S flip-flop) 50
2 and its output, and the signal MCPU-roma sets the set-reset circuit 502. The set/reset circuit 502 temporarily stores access requests from the MCPUIO, and output side set/reset? ) circuit 506 in the set state, the MC
Similarly, the 5CPU reset signal 5RES, which indicates that an access request from the PUIO has been accepted and an access operation is being executed via the external memory data access control signal generation circuit 510, is coupled to the set reset circuit 504 and its output. Set reset circuit 508
The signal SCPU-roma sets the set-reset circuit 504. Set reset circuit 504
temporarily stores the access request from the 5CPU 20, and the output side set reset circuit 508 outputs the 5C in the set state.
This indicates that the access request from the PU 20 has been accepted and the access operation is being executed.

Specifically, the output “H” in the set state of the MCPU access request set reset circuit 502 is conditional on the condition that the 5 CPU access execution set reset circuit 508 is not in the set state, that is, on the condition that the access operation of the 5 CPU 20 is not being executed. as (value input is 5
A signal that sets the MCPU access execution set reset circuit 506 to the MCPU access execution state (via an AND gate 524 coupled to an inverting input via an inverter 522 from 08). OR game) 512
MCPU access request set reset circuit 502 (value input is coupled to reset signal MRES). Similarly, the output “H” in the set state of the 5CPU access request set reset circuit 504 is set on the condition that the MCPU access execution set reset circuit 506 is not in the set state, that is, on the condition that no MCPUIO access operation is being executed (value Sets the 5 CPU access execution set reset circuit 508 to the 5 CPU access execution state through an AND gate 526 ), one of whose inputs is coupled to an inverting input from 506 via an inverter 520 , and sets the 5 CPU access execution set reset circuit 508 to the 5 CPU access execution state. one or more configurations that reset the 5CPU access request set reset circuit 504 via the OR gate 516 (value input is coupled to the reset signal 5RES) by a signal that
Even if there is an access request from a CPU (for example, 5CPU2o), if an access operation related to the other CPU (MCPUIO) is being executed, the CPU that requested the access (SCPU20) will wait until the execution is completed.
No access operations are performed, which essentially avoids access conflicts.

Furthermore, MCPUIO and 5 CPUs 20 may request access completely simultaneously. In response to this access conflict, in the embodiment, priority is given to the access request from MCPUIO, and after the access operation of MCPUIO is executed, the access operation of 5 CPUs 20 is executed. For this reason, when the MCPU access request set reset circuit 502 is in the set state, its output signal "
AND gate 52 via inverter 525 due to
6 is prohibited, and when the set reset circuit 502 is setting, 5 CPU access request set reset circuit 5
Even if 04 is set, the 5 CPU access execution set reset circuit 508 is prevented from being set.

The external memory data access control signal generation circuit 510 includes:
is coupled to the outputs from set-reset circuits 506 and 508 such that the output of either set-reset circuit is in the set state "
When it changes to "H", the CPU access operation indicated by the set state is executed in a series of sequences.The signals CE and OE output from the external memory data access control signal generation circuit 510 are used to output data from the external memory 7. The signal MDL is a control signal for latching data from the external memory 90 into the MCPU external memory data latch 80M, and the signal SDL is a control signal for latching data from the external memory 90 into the SCPU external memory data latch 80S.
This is a control signal for latching data starting from 0. The external memory data access control signal generation circuit 510 generates an END signal when the execution of the access operation is completed. This END signal resets the access execution set reset circuit that was in the set state. That is, the END signal is reset by the extraction input.

An AND gate 528 is coupled to the output of the set reset circuit 506 and an extract input is coupled to the reset input of the set reset circuit 506 via an OR gate 514 whose extract input is coupled to the MCPU reset signal MRES.
AND gate 530 coupled to the output of 8 and the input input is 5C
OR gate 518 coupled to PU reset signal 5RES
to the reset input of the set-reset circuit 508.

The output of the 5CPU access execution set reset circuit 508 is sent to the address switching circuit 40 via the inverter 532.
An address selection signal MSEL is generated for the address selection signal MSEL. Therefore, when the access operation of the 5 CPUs 20 is being executed, the address switching circuit 40 switches the 5 CPUs from the address latch 305 for SCPU external memory access.
In other cases, the MCPU address from the MCPU external memory access address latch 30M is selected.

In the case of Fig. 27, MCPUIO and 5CPU20 are “MC
The PU operation roma requests access to the external memory 90 at the same time as shown in "5CPU operation roma". This r o
In the operation of the ma instruction, MCPUIO sends address information to the address bus MA and outputs the signal MCPUIO.
-roma to cause the MCPU external memory access address latch 30M to latch the address information, and similarly, the 5CPU 20 sends address information to the address bus SA, outputs the signal SCPU-roma, and sets the 5CPU external memory access address latch 30M. 30S to latch the address information. The MCPU access request set reset circuit 502 and the 5CPU access request set reset circuit 50 of the memory device contention avoidance circuit 50 are activated by the MCPU-roma signal and the SCPU-roma signal that are generated simultaneously.
4 are set at the same time. On the other hand, the MCP mentioned above
According to the U access priority logic, the MCPU access execution set reset circuit 506 immediately changes to the set state;
Thereby, the external memory data access control signal generation circuit 510 executes the MCPUIO access operation to the external memory 90. At this point, the address switching circuit 40 has selected the address information from MCPUIO. The period of the access operation of MCPUlo is indicated by the period MsL on the left side of FIG.
0 is the two-phase master clock CK1. CK2 (although not shown in FIG. 26), the external memory data access control signal generation circuit 510 operates with CK2 in period n,
The output enable signal CE is made low active, and the output enable signal OE is made low active during the second half period m of one period n. Therefore, during this period m, the external memory 9
The data requested by MCPU I O is output from 0,
This output data is latched into the MCPU external memory data latch 80M by the signal MDL generated from the external memory data access request signal generation circuit 510 within this period m. As a result, the access operation for MCPUIO of the external memory data access request signal generation circuit 510 is completed, so that the circuit 510 receives the end signal E.
Output ND. As a result, the MCPU access execution reset circuit 506 is reset and the 5C
The PU access execution set reset circuit 508 is set. As a result, the signal MSEL changes to the "L" level indicating selection of the 5 CPU address, and the address switching circuit 4
0 selects an address from the 5 CPU 20 to address the external memory 90. Further, in response to a set signal from the 5 CPU access execution set reset circuit 508, the external memory data access control signal generation circuit 510 executes an access operation for the 5 CPU 20. This period is shown by the period sentence on the right side of FIG. 27. In this operation, the external memory data access control signal generation circuit 510 makes the signal CE low active, and in the latter half of the period, the PI signal OE is made low active and 5C.
The data requested by the PU 20 is outputted from the external memory 90, and during the output, a signal SDL is generated to cause the 5CPU external memory data latch 803 to latch the data requested by the 5CPU 20. As a result, the access operation for the 5 CPU 20 of the external memory data access control signal generation circuit 510 is completed, so the circuit 510 outputs the end signal END and returns the 5 cPU access execution set reset circuit 508 to the reset state.

After this, MCPUIO and 5CPU 20 can obtain the requested data by reading the output data of external memory data latches 80M and 80S on data buses MD and SD, respectively.

In this way, after each CPU 10120 executes the r o m a instruction (external memory access request instruction), the memory device contention avoidance circuit 50 waits for a predetermined period of two sentences to execute the access operation for both CPUs. data can be obtained, and the problem of access contention is resolved. Furthermore, since the standby time is constant (2 cycles), each CPU
10120 can use this period to execute other instructions, optimizing the execution efficiency of program instructions.

In addition, the MCPU-roma signal and the 5CPU
Cases in which the timing relationship of the roma signal is other timing relationships are not shown in the diagram, but in any case, each CPU 10120 has already executed each CPU if it waits two sentences for a predetermined period after executing the roma instruction. CPU
Since the requested data is latched in the external data latch, the data can be obtained.

Address/data conversion/＼-ware (28th to 3rd
In general, in a microcomputer system including a CPU, converted data (desired information extracted from the original data) is created on the calculation memory from the original data in the data memory. is often desired. Particularly for this type of data, conversion is necessary to compensate for efficient use of the storage capacity of the data memory. For this purpose, conventionally, a transfer instruction from the data memory to the calculation memory is executed to move the original data in the data memory to the calculation memory, and then one or more conversion instructions are executed to transfer the original data from the data memory to the calculation memory. Converts the data in the ALU via the ALU. Therefore, in the conventional case, the data conversion procedure to obtain the desired data on the calculation memory takes time;
This is one of the obstacles in applications that require high-speed processing.

In this embodiment, the CPU 10120 is connected from the external memory 90, which is a data memory, to the internal RAM 106, which is a calculation memory.
Alternatively, simply by executing an instruction (roma instruction) to transfer data to the RAM 206, data that has been subjected to desired conversion is read into the internal RAM 106, 206, thereby speeding up data conversion processing. To achieve this purpose, an address conversion circuit 60 is provided on the address path between the CPU 10120 and the external memory 90, and a data conversion circuit 70 is provided on the data path between the external memory 90 and the CPU 10120. Each conversion circuit 60.
70 executes a desired conversion in response to a control signal given from CPU 10120 when executing the roma instruction.

FIG. 28 shows a list of external memory access instructions roma. The first instruction romaO is a transfer instruction without conversion, whereas the address translation circuit 60 uses C
The input address given from PU10.20 is directly passed to the external data memory 90 as an output address, and the data conversion circuit 70 also converts the data from the external data memory 90 (
16-bit data) to the CPU10120 without conversion.
give it to

In this non-conversion transfer instruction romao, the conversion control signal R given from the CPU10120 to the conversion circuit 60.70
1, R2, and R3 are all at "L" level.

The second instruction romal is an instruction suitable for reading a special waveform. In response to this instruction, the address conversion circuit 60
The 13th input address sent from PUl0120
When bit A12 is "O", the lower 12 bits are passed through without conversion, but when the 13th bit A12 is "1", the lower 12 bits are passed through without conversion.
Invert the bits. Note that the 13th bit of the output address of the address conversion circuit 6o is fixed at "θ" regardless of the value of the 13th bit (A12) of the input address.

In addition, in response to this instruction, the data conversion circuit 70
The 13th bit A12 of the input address sent from 0120 is set as the 13th bit 012 of the data sent to CPU10, 20, and when Al1 is "1", the lower 12
The data from the external memory 90 is converted in a format that inverts the bit data. Therefore, special waveform data (o o o) having 12 effective data bits as shown in FIG. 28 is stored in the address area 0000 to 0FFF of the external memory 90.

~0FFF), when CP[Jlo, 20 repeatedly executes this instruction for the specified address range 0000 to IFFF, the external memory address output from the address translation circuit 60 will once advance from 0000 to 0FFF. , During this time, the data conversion circuit 70 passes the data from the external memory 90 as is, and then, due to the inversion operation of the address conversion circuit 60, the address to the external memory 90 is reversed from 0FFF to oooo, and during this time,
The data conversion circuit 70 also inverts the lower 12 bits of the data output from the external memory 9o, and converts the 13th data bit D
12 to 1'' and output the converted data.In the end,
CPU10120 moves the address from 0000 to IFFF and executes the instruction r.

When m a 1 is repeatedly executed, CPUl012
The waveform actually received by 0 is the waveform shown on the right side of the rOnlLl column in FIG. This converted waveform is a repetitive waveform (a waveform that is symmetrical about the address 0FFF and data 0FFF points) obtained by extending the original waveform in the external memory 90 shown on the left in a predetermined manner.As a result, in terms of storage capacity, This method has the advantage that the waveform data storage capacity is halved compared to a method in which the converted waveform data itself is stored in advance in the external data memory 90. This command r o m a
In the case of 1, only R1 among the control signals R1, R2, and R3 becomes "H" level.

The third instruction ROMA2 is an instruction to read a part (half word) of external memory data. For this command,
Only R2 becomes "H" level.

The storage capacity of one address (one word) of external data memory 90 is 16 bits. For this command roma2,
When the 16th bit (A15) of the address from the CPU 10120 is "0", the data conversion circuit 70 leaves the lower 8 bits of the 16-bit data from the external data memory 9o and converts the upper 8 bits to "0". ”, and when A15 is “1'', shift the upper 8 bits of the 16-bit data from the external data memory 90 to the lower 8 bits (the remaining upper 8 bits are masked). Execute. Furthermore, since the data conversion circuit 70 uses the 16th bit A15 of the input address as a control signal, the address conversion circuit 60 sets the 16th bit of the output address to a predetermined value "θ" regardless of the value of A15.
In this case, the relationship between the upper 8 bits and lower bits of the 16-bit information from the external data memory 90 is one data (for example, phase data).
The relationship may be between the upper data part (for example, the integer part) and the lower data part (for example, the decimal number m),
An independent relationship such as two different types of 8-bit data (for example, rate data and level data) may be used.

The fourth instruction ROMA3 is an instruction to shift external memory data and read a part of it. In the case of this instruction, only R3 becomes "H" level. In response to this command, the data conversion circuit 70 converts the 16-bit data from the external memory 90 into
Leave bit 15 as is and use bit 1 of the upper 12 bits.
Shift bits 5 to 4 to bits 14 to 3, and perform conversion to mask the lower 3 bits bits 2 to 0 to 0. Here, of the 16 bits of data in the external memory 90, the upper 12 bits, for example, set bit 15 as the sign bit. In this case, the above conversion allows CPU 10120 to quickly read waveform data in a format suitable for use on internal RAM 106.206.

FIG. 29 shows a block diagram of the address conversion circuit 60.
This address conversion circuit 60 includes MCPU1O or 5C.
Of the 16-bit address input from the PU 20 via the address latches 30M, 30S and the address switching circuit 40, the lower 12 bits (bit O~bit
ll) is input to an inverting circuit 610 whose details are shown in FIG. This inverting circuit 610 receives the signal R1 as the command romal.
When A12 of the address is “1” with “l” representing
It is operated by a signal from the D-game) 612 and inverts the lower 12 bits of the input address. Also, the command r
The signal R1, which becomes "L" when omal is executed, disables the AND gate 604 through the inverter 602, and turns the corresponding bit (bit 12) of the output address "ON" regardless of the value of A12 of the input address.Input address A of
l1 and A14 are the corresponding pins of the output address as they are) (b
it13, bit14). A15 (MSB) of the input address becomes the corresponding beat (btt15) of the output address via an AND gate 608, and a signal R2 of "1" indicating that the instruction r o m a 2 is being executed.
is occurring, this signal R2 is output to the inverter 606
and masks the output address bft15 (MSB) to 0''.

Therefore, the address conversion circuit 6o converts the non-conversion instruction r o
For mao and shift read command r o m a 3, R1 = "0" and R2 = "0", so the input address is passed through as the output address, and for the special waveform read command romal, R1 = "l". The lower 12 bits of the input address are masked in bitlZt″θ″′ of the output address, and the lower 12 bits of the input address are masked by the scale rotation circuit 610 of A12="l")
(bit.

~bitll) is inverted and used as the output address.

Furthermore, for the partial read instruction roma2, R2="
1", so bit 15 of the output address is masked to "0". In this way, the function of the address conversion circuit described in connection with FIG. 28 is realized.

FIG. 31 shows a block diagram of the data conversion circuit 70, and FIG. 32 shows its details. In these figures, data input is data supplied from the external memory 9o in FIG. MIJ1. ! @32 In the diagram, a 3-state gate circuit 702 that connects to the upper 8 bits of input data and a 3-state gate circuit 704 that connects to the lower 8 bits of input data output the input data as the lower 8 bits of the data. The upper 8 bits are selected, but this is for determining whether to select the lower 8 bits of input data. R2=“l”(rom
a2 instruction) When fA15=1, the “l” output signal of the AND gate 706 and the inverter 708 which is its inverted signal
The output signal “0” causes the gate circuit 702 to conduct.
Gate circuit 704 is turned off and the upper 8 bits of the input data are selected as the lower 8 bits of the output data. In other cases, gate circuit 702 is turned off and gate circuit 70
4 becomes conductive, so the lower 8 bits of the input data are output as they are as the lower 8 bits of the output data. Furthermore R2
When ="1" (r o m a 2 instruction), the AND gate circuit 71 connects to the upper 8 bits of the input data.
0 is prohibited and the upper 8 bits of the output data are masked to 0''.In other words, when R2="1", the inverter 712
A prohibition signal is applied to the AND gate circuit 71O via the NOR gate 714, and passage of the upper 8 beats 2 of the input data in the AND gate circuit 710 is prevented. Also,
The AND gate element connected to the upper 3 bits of the input data in the AND gate circuit 710 has R1="1" (r
oma1 instruction), it is inhibited via the NOR gate 714, and the upper three bits of the output data are masked to "0".

EX-OR gate circuit 716 is a circuit for selectively inverting the lower 12 bits of input data. EX-OR
The gate circuit 716 has R1="l" (r o m a 1
When A12=1+7) in the AND gate 718, the lower 12 bits of data are inverted, and in other cases, the AND gate element in the 0 circuit 710, which passes the lower 12 bits as is, is activated. State gate 722 is coupled to bit 12 of the input data via R1=
When “l” (roma 1 instruction), the signal “O” is applied via the input 720 which is coupled to the signal R1.
Instead, the three-state gate 724 coupled to A12 is turned on by the signal R1 and the bit of output data is turned off by R1.
12 is generated. The shift mask circuit 726 selectively shifts bits 15 to 4 of the input data to bits 14 to 3 of the output data.
This is a circuit for masking 2 to bi10 to “0”,
This conversion is performed by the signal "l" from inverter 728 coupled to signal R3 when R3="l" (roma3 instruction).

Therefore, the data conversion circuit 70 converts the non-conversion instruction ROM
When aO (R1=R2=R3="0"), the input 16-bit data is passed through as is, and when the special waveform read command romal (R1-"l") is, the upper 4 bits of the input address (bits 15 to 15) are passed through. bit12) is “o”
ooo'' (when A12=0) or 0001'' (A12
= 1), the lower 12 bits of the output data are used as the lower 12 bits of the input data (AI2
= 0), or the lower 12 of the output data and the lower 12 of the input data? ) is inverted data (AI2 = 1), and when the partial read command roma2 (R2 = ``1''), the upper 8 bits of the output data are all zeros, and the lower 8 bits of the output data are bits are the lower 8 bits of the input data (AI5
=O), or perform data conversion so that the upper 8 bits of the output data are all zeros a, and the lower 8 bits of the output data are the upper 8 bits of the input data (AI5=1 and 9), Shift read command roma3 (R3=
1), the lower 3 bits of output data y)(bitO
~b it 2) are all zeros, and the output data bi
t3 to bit14 are input data bits t4 to bit1
In step 5, data conversion is performed so that bit 15 (MSB) of the output data becomes bit 15 (MSB) of the input data. In this way, the data conversion function described in FIG. 28 is achieved. .

As described above, the address conversion circuit 60 and the data conversion circuit 7
The advantage of providing 0 is obvious. That is, C
For the PU1012o, simply by executing the access command roma to the external memory 90, which is a data memory, the conversion function of the circuits 60 and 70 can immediately obtain the data that has undergone the desired conversion.
The data in the external memory 90 is transferred to the internal RA which is a calculation memory.
There is no need to perform conversion via an ALU such as the ALU unit 108, 208 after the data is once imported into the M106, 206, which has the advantage of speeding up the processing.

Note that the list of access commands rOm& shown in FIG. 28 is merely an example, and can be easily expanded and modified.

<DAC Sampling (FIGS. 33 and 34)> In this embodiment, the DAC 100 converts the digital musical tone signal generated by the MCPUIO and the 5 CPU 20 into an analog musical tone signal. As shown in 5-5 in Figure 5, the MCPU
IO is performed by MC in the timer interrupt processing routine.
The sample of the digital musical tone signal generated by PUIO and 5CPU 20 is set to DAC:100. This process 5-
Although the execution interval of No. 5 is on average equal to the generation interval of the interrupt signal INT generated by the timer interrupt generation section 116, the actual execution interval varies due to the program operation. Therefore, if D/A conversion is performed using the execution interval of process 5-5 as the conversion period of D/A conversion, a large distortion will occur in the analog musical tone signal.

FIG. 33 shows an example of the configuration of the right DAC 100R or left DAC 100L. In the configuration shown in FIG. 33(A), when processing 5-5 is executed, the internal RAM 106 is The waveform addition register is designated, and the latest digital tone data stored there is taken out and placed on the data bus.

Then, at the timing when the digital musical tone data is on the data bus, a strobe program control signal is input to the clock input of the latch 1004 to the operation control circuit 11.
2, the data on the data bus is set, and new digital musical tone data is input from latch 1004 to D/A converter 1002. Therefore, Fig. 34 (A
), the digital musical tone data input to the D/A converter [1ii 1002 is switched at an unstable cycle due to program control. D/All device 1002
Unless the conversion period (sampling period) of is very stable, large distortions will occur in the conversion.

This problem can be solved by adopting a configuration as shown in FIG. 33(B). That is, between the soft control latch 1004 controlled by the program control signal from the operation control circuit 112 and the D/A converter 1002 that converts the digital musical tone signal into an analog musical tone signal,
An interrupt control latch 1006 is provided which is controlled by an interrupt signal INT which is a precise timing signal of the interrupt generating section 116. The generation period of the interrupt signal follows the stability of the clock oscillator, so it is extremely stable. The output of latch 1006 is switched in synchronization with the timing of the interrupt signal. That is, the generation cycle of the interrupt signal becomes the conversion (sampling) cycle of the D/A converter 1002. As shown in FIG. 34(B), which is a time chart for the configuration of FIG. Although it varies depending on the time required for the change (length of the shaded part), since there is a latch 1006 that operates with the interrupt signal, the timing at which the input data of the D/A converter 1002 switches is synchronized with the interrupt signal. This solves the distortion problem in the configuration of FIG. 33(A).

[Modifications] This concludes the description of the embodiments, but various modifications and changes are possible within the scope of the present invention.

The invention comprises a main CPU and at least one CPU.
The present invention relates to a technology for speeding up access from a main CPU to a sub CPU in a digital microcomputer having a PU. Therefore, the application to which the digital microcomputer is applied (in the case of the embodiment, electronic musical instruments) is not particularly limited.

In the embodiment, the main CPU 10 receives the 5CPU state quantity from the 5CPU reset control unit 30 in the operation control circuit 112 in order to determine that the sub CPU 20 is in the stopped state, and the interrupt processing routine (FIG. 5) 5 -3 means this 5 CPUCPU state quantity CPU20
Waiting until it shows a stopped status. However, the main CPU can determine or define the period in which the sub CPU 20 is in a stopped state without necessarily having to measure the state of the sub CPU 20.
Considering the longest time required to execute the program (FIG. 6), the sub CPU 20 should be stopped after the longest time has elapsed. Therefore, the purpose can be achieved if the access from the main CPU 10 to the internal memory of the sub CPU 20 occurs only after the above-mentioned maximum time has elapsed. Specifically, instead of the 5-CPU state detection process in 5-3, for example, a standby routine may be executed until the longest time elapses in the main CPU.

[Effects of the Invention j As described in detail above, according to the present invention, the main CPU side is provided with a function of determining, detecting, or regulating the period in which the sub CPU is stopped, and the main CPU
Since the internal memory of the sub-CPU is accessed when the PU is in a stopped state, the conventional time-consuming access procedure is no longer necessary, resulting in faster access.

[Brief explanation of the drawing]

Figure 81 is an overall configuration diagram of an electronic musical instrument processing device to which the present invention is applied, Figure 2 is a block diagram of the MCPU in Figure 1, and Figure 3 is a block diagram of the MCPU in Figure 1.
Figure 4 is a flowchart of the main program executed by the MCPU, Figure 5 is a flowchart of the interrupt processing routine executed by the MCPU, Figure 6 is a flowchart of the program executed by the 5CPU, and Figure 4 is a flowchart of the main program executed by the MCPU. is a flowchart of sound source processing, FIG. 8 is a flowchart of the operation of the embodiment over time, and FIG. 9 is a flowchart of channel sound source processing. Fig. 1θ is a diagram showing waveform data, Fig. 11 is a diagram showing a RAM table for sound source processing, Fig. 12 is a block diagram of a circuit related to the 5 CPU operation start termination function, Figs. Figure 15 is a time chart of the operation of the circuit in Figure 12, Figure 16 is a block diagram of a circuit with an interrupt mask function, Figure 17 is a flowchart of envelope setting processing using the interrupt mask method, and Figure 18 is a single instruction FIG. 19 is a block diagram of a circuit having a function of prohibiting interruption of the main program by an interrupt signal while transferring multiple pieces of data.
FIG. 20 is a diagram showing an example of a transfer command, and FIG.
The figure is a flowchart of envelope setting processing using the single transfer command method, and FIG. 22 is a flowchart used to explain the 5CPU access function from the MCPU using the 5CPU stop mode. FIG. 23 is a flowchart of an MCPU having an instantaneous forced access function for 5 CPUs, and FIG. 24 is a block diagram of 5 CPUs suitable for an instantaneous forced access function for 5 CPUs. FIG. 25 is a time chart of the operation when writing data from the MCPU to the fiRAM of the 5 CPUs. 26 is a block diagram of the memory device contention avoidance circuit of FIG. 1, and FIG. 27 is a time chart of the operation of the circuit of FIG. 26. FIG. 28 is a diagram showing a list of external memory access instructions including instructions to convert and import data from external memory, FIG. 29 is a block diagram of the address modification circuit in FIG. 1, and FIG. Figure 31 is a block diagram of the data conversion circuit in Figure 1. Figure 32 is a circuit diagram of the data conversion circuit. Figure 33 is a diagram comparing a configuration in which the sampling cycle of the DAC shown in Figure 1 becomes unstable and a configuration in which the sampling cycle is stabilized. FIG. 34 is a diagram showing a comparison of a time chart when the sampling period of the DAC is unstable and a time chart when the sampling period is stable. 206...RAM (internal memory of sub CPU) Casio Computer Co., Ltd. IO...MCPU (main CPU) 20...
... 5 CPU (sub CPU) 116 ... Interrupt generation section (operation start signal generation means, interrupt generation means) 134 ... 5 CPU reset control section 214 ...
...ROM address control section 134,214...
...(Sub CPU mode control means) 114...ROM address control section (Main CPU mode control means)
U mode control means) 112...Operating control circuit (sub CP
U mode discrimination means, sub CPU access means, sub CPU mode detection means)

Claims (2)

[Claims] (1) A main CPU, at least one sub-CPU, an operation start signal generation means for generating an operation start signal, and an operation state in which the mode of the sub CPU is changed from a stopped state to a program execution state in response to the operation start signal. and in response to the end of execution of the program, the sub CP
a sub-CPU mode control means for controlling the U to return to a stopped state; and a sub-CPU mode control means provided in the main CPU for determining whether the mode of the sub-CPU controlled by the sub-CPU mode control means is in a stopped state. CPU mode determining means; sub-CPU access means provided in the main CPU and accessing internal memory of the sub-CPU while the mode of the sub-CPU is in a stopped state as determined by the sub-CPU mode determining means; A digital microcomputer characterized by having the following. (2) a main CPU, at least one sub-CPU, an interrupt generating means that generates a timer interrupt signal every predetermined time period; and a main CPU that responds to the timer interrupt signal.
interrupting the main program being executed in U, switching the mode of the main CPU to a mode for executing an interrupt processing routine, and restarting the interrupted main program in response to the completion of execution of the interrupt processing routine; main CPU mode control means for controlling the mode of the main CPU to return to a mode for executing a main program;
sub-CPU mode control means for controlling switching of the mode of the sub-CPU from a stopped state to a mode for executing a program, and controlling the mode of the sub-CPU to return to the stopped state in response to completion of execution of the program; a sub-CPU mode signal generating means provided within the means and generating a signal representing the mode of the sub-CPU; and a sub-CPU mode signal generating means provided within the main CPU receiving the signal from the sub-CPU mode signal generating means and generating a signal representing the mode of the sub-CPU.
sub-CPU mode detecting means for detecting a mode of U; and sub-CPU mode detecting means provided in the main CPU, and accessing an internal memory of the sub-CPU while the sub-CPU mode detecting means detects a stopped state of the sub-CPU. A digital microcomputer characterized by comprising: a sub-CPU access means for accessing a sub-CPU;