JPH0460722A - Digital microcomputer - Google Patents

Abstract

PURPOSE:To set the processing result of an interruption processing routine to be accurate by preventing the control of CPU from shifting to an interruption mode while plural pieces of data are written into a memory for interruption processing. CONSTITUTION:MCPU executes an instruction masking interruption prior to the transfer of data for preventing the control of MSPU from shifting a timer interruption processing routine while data is transferred from a transfer buffer to register group for channel sound source. The mask signal MSK of low active is generated from the operation control circuit of MSPU while the interruption mask instruction is executed. The mask signal MSK operates in such a way that it masks an interruption signal INT from an interruption generation part and prohibits the shift of control for the interruption processing routine.

Description

[Detailed description of the invention] Technical field of E invention] This invention relates to a digital microcomputer.

[Background of the Invention] Recently, the applicant has proposed a device that not only processes control inputs for electronic musical instruments but also generates musical tone signals through microcomputer program processing (Japanese Patent Application No. 63-334).
．． No. 158), the CPU of this microcomputer executes an interrupt processing routine in response to an interrupt signal from a timer in order to generate execution of the main program.

This microcomputer has problems related to data transfer from the main program to the interrupt processing routine. That is, the processing in the main program of the CPU includes data update processing for setting a plurality of data to be referenced in the interrupt processing routine in the interrupt processing memory. An interrupt signal can also be generated during such data update processing. In that case, C.P.
Control of U is transferred from the main program to the interrupt processing routine. As a result, errors occur in the processing results (music waveform data) of the interrupt processing routine.1 For example, taking an envelope as an example, when updating an envelope step, the main program updates multiple envelope parameters (envelope 7 period between calculations, envelope difference value, envelope mill s, etc.) is attempted to be written to the corresponding area of the interrupt processing memory. If an interrupt signal is generated and CPU control is transferred to the interrupt processing routine before all envelopes and parameters have been written, the interrupt processing routine will write the updated envelope parameters and the envelope parameters before the update (therefore, the incorrect values). The envelope peak value is calculated using the data), and a musical tone signal is generated based on the envelope peak value. Therefore, the generated envelope peak value and musical tone signal end up being unintended values.

Above, we have explained the problem of passing multiple pieces of data from the main program to the interrupt processing routine using a microcomputer applied to an electronic musical instrument as an example.This invention, which will be explained below, is suitable for all microcomputers facing this type of problem. It provides an effective solution.

[Object of the Invention] That is, an object of the present invention is to provide a microcomputer that guarantees writing processing of multiple data in a main program passed to an interrupt processing routine so that the processing results of the interrupt processing routine are always correct. The goal is to provide the following.

[Structure 1 of the Invention] In order to achieve the above object, the present invention includes a CPU having a main program mode for executing a main program and an interrupt mode for executing an interrupt processing routine, and an interrupt generator for generating an interrupt signal. means, and said C in response to said interrupt signal.
The main program running on the PU is interrupted and the CPU
CP that controls switching of the mode of the mode to the interrupt mode.
In the digital microcomputer, the digital microcomputer has a U-mode control means, in which a plurality of data are written in the interrupt processing memory in the main program mode of the CPU, and the plurality of data stored in the interrupt processing memory are written in the interrupt processing memory in the interrupt mode. referring means; and while the writing process of the plurality of data to the interrupt processing memory is executed by the means in the main program mode F, the operation of the CPU mode control means is controlled by masking the interrupt signal. There is provided a digital microcomputer characterized in that it has interrupt mask means for prohibiting interruption of the write process.

According to this configuration, while a plurality of pieces of data are written to the interrupt processing memory in the main program mode, the interrupt signal is masked and the operation of the CPU mode control means for shifting control of the CPU to the interrupt mode is prohibited. Therefore, write processing can be guaranteed, and the processing results of the included processing routine can be made correct.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

Summary> This embodiment applies this invention to an electronic musical instrument.
This embodiment (FIGS. 1 to 34) includes various features. The first feature is a plurality of microcomputer processing devices 1 that operate according to a program as a sound source that generates musical tone signals.
(CPU), and there is no need for a /\-toware sound source with a dedicated structure like in the past. One CPU functions as the main CPU or master CPU (10) and not only processes sound sources, but also input devices (W'1. function keys, etc.) and output devices according to the application (in this case, a musical instrument)!
(DAC etc.) (Figure 4, Figure 5), other C
The PU works as a sub-CPU or slave CPU (20) for the master CPU and executes sound source processing (
(FIG. 6), the configuration is such that the burden of sound source processing is shared between each CPU.

The second feature is related to the mechanism by which the sub-CPU starts and ends its operation, and according to this embodiment, the sub-CPU
The operation starts in response to a tire interrupt that requests sound source processing to the master CPU, and as a result, sound source processing is executed in parallel in the master CPU and sub CPU. When the operation (sound source processing) of the sub CPU is completed, the sub CPU is transferred to the reset state (stop state) by the end signal, and the end signal is sent to the master CPU.
It is transmitted to U (Fig. 8, Fig. 16). This feature allows the master CPU to effectively manage and understand the operating period of the sub CPU. Furthermore, this feature allows efficient execution of sound source processing tasks (generating digital samples of musical tone signals) that require high-speed processing.

The third feature of this embodiment relates to the problem of updating (transferring) data passed from the main program to the timer interrupt processing routine. As a result of the execution of the interrupt processing routine, it becomes necessary to update a plurality of data (eg, enthrope target value, enthrope parameters such as envelope plate) to be referenced in the interrupt processing routine. The execution instructions for updating this plurality of data are included in the main program. That is, this plurality of data is updated by the main program and referenced by the timer interrupt processing routine. Since such multiple pieces of data constitute meaningful information as a whole, control must not be transferred to the interrupt processing routine before all of the multiple pieces of data have been updated in the main program. As a method, a method has been disclosed in which the interrupt is masked and the transition to the interrupt processing routine is prohibited until the data update is completed (Part 1).
6 and 17), and as a second method, a method is disclosed in which multiple data updates (transfers) are executed with a single instruction in the main program (Figs. 18 to 21). , the processing results (samples of musical tone signals) of the interrupt processing routine show correct numbers, and correct operation is guaranteed.

The fourth feature of this embodiment is that from the master CPU to the slave C
Concerning data access issues for PUs. In conventional multi-CPU microcomputer systems, C
Data transfer between PUs is performed through a series of sequences and takes a considerable amount of time. Typically, a CPU requesting data access sends an access request signal to the CPU requesting access. In response to this access request signal, the CPU to which access is requested completes the operation being executed, and then sends an approval (acknowledgement) signal to the CPU.
and enters the stopped state. After the access request signal is sent, the requesting CPU is in a waiting state until the approval signal is received. Upon receiving the approval signal, the requesting CPU performs actual data access to the internal memory of the requested CPU. As described above, the conventional inter-CPU data access method takes time and is therefore not suitable for applications such as electronic musical instruments that require high-speed processing. To solve this problem, in this embodiment, as the first data access method,
Utilizing the second feature above, when the sub CPU is in a stopped state, the master CPU uses the sub CPU's internal memory (20
6), a stop mode control method for reading/writing (accessing) data has been disclosed (Fig. 22), and as a second data access method, the master CPU accesses data to the sub CPU without waiting state (the sub CPU An instantaneous data access method (forcibly stopped only during data access) is disclosed (FIGS. 23 to 25).

The fifth feature of this embodiment is that the CPU external memory as a data source is shared by multiple CPUs.
According to this embodiment, by providing a memory device conflict avoidance circuit (50) to be described later, conflicts in access to the shared memory are resolved, and after a certain waiting time, the shared memory is Allows data to be retrieved from memory.

The sixth feature of this embodiment relates to speeding up FJ (shift, inversion, partial extraction, etc.) other than data conversion.

Conventionally, in order to obtain data converted from data in a data memory such as the above-mentioned CPU external memory onto the CPU internal memory (computation memory), a transfer (read access) command is used to transfer the data in the data memory. is transferred to the arithmetic memory, and then the data in the arithmetic memory is converted via the ALU by a conversion instruction. It is also often necessary to execute multiple conversion instructions to effect the desired data conversion. As described above, there has been a problem in the past that data conversion processing takes time, which is a particularly serious problem in applications that require high-speed processing, such as sound source processing. To solve this, according to this embodiment, data address translation hardware (60
, 70).

By executing a special transfer instruction (transfer with conversion instruction), data that has been subjected to the desired data conversion is loaded into the calculation memory (106, 206) via the data address conversion hardware that responds to the instruction. I'm trying to make it happen. Therefore, in order to obtain desired conversion data, it is sufficient to execute a single instruction instead of a plurality of instructions, and the processing speed can be increased.

Overall Configuration (Figure 1) Figure 1 is a block diagram showing the overall configuration of this embodiment configured as a processing device for an electronic musical instrument.
(denoted as U20).

Each CPU 10120 has a built-in program, and the 0MCPU 10, which operates according to the respective program, controls the entire system in addition to sound source processing (Fig. 5). processing of input information from keyboards, function keys, etc.);
DAC that converts digital musical tone signals to analog musical tone signals
100 control etc. (Figure 4), whereas 5CP
U20 is dedicated to sound source processing (FIG. 6).

A memory 90 serves as a data source for sound source control data, waveform data, and the like. The data memory 90 is an LSI
It consists of a ROM externally attached to a chip (which carries the remaining devices in Figure 1). If the degree of integration is high, data memory 90 can be formed as an internal memory on a single LSI chip. External memory 90 is MCPU
Address information from 0MCPU10, which is shared by CPUs 10 and 5, is transferred to address bus M, which couples to MCPUIO.
A. MCPU external memory address latch 30M of external memory address switch 30, address switching circuit 40.
It is applied to the address input of external data memory 90 via address conversion circuit 60. On the other hand, the address information from 5CPU20 is sent to the address connected to 5CPU20.
A, 5 is applied to the address input of the external data memory 90 through the CPU external memory address latch 30S, address switching circuit 40, and address conversion circuit 60. The data transmission path from the external data memory 90 to the MCPUIO is the data output of the external data memory 90, the data conversion circuit 70. The MCPU of external memory data latch 80 is composed of external memory data latch 80M and data bus MD coupled to MCPUlo. On the other hand, the data transmission fee from the external data memory 90 to the 5 CPU 20 is the data output of the external data memory 90, the data conversion circuit 70.
5CPU external memory data latch 80S, 5CPU20
It is constituted by a data bus SD coupled to the data bus SD.

The memory device contention avoidance circuit 50 includes MCPUIO and 5 CPUs.
This system controls access to the external memory 90 by both CPUs 20 and avoids conflicts. The memory device conflict avoidance circuit 50 controls the address switching circuit 40 in response to the signal roma requesting external memory access from MCPUIO and the signal roma requesting external memory access from the 5 CPUs.
0 selects either the address from MCPUIO or the address from 5CPU 20 as the address to external memory 90. For this purpose, the memory device contention avoidance circuit 50
Address switching circuit 4 by selection signal MSEL from
0 performs a selection operation. When the address to the external memory 90 is determined, the memory device conflict avoidance circuit 50 selects the external memory 90.
chip selection signal CE and output enable signal OE for
Activate. This causes data to be output from external memory 90 and appear on the input bus of external memory latch 80 through data conversion circuit 70 . Here, the memory device contention avoidance circuit 50 operates either the MCPU external memory data latch 80M or the 5CPU external memory data latch 80S to latch the data in order to send the data to the CPU that has requested data access. For this purpose, the MCPU external memory data latch 80M operates in response to the latch signal MDL from the memory device contention avoidance circuit 50, and the 5CPU external memory data latch 80S
is the latch signal SDL from the memory device contention avoidance circuit 50.
It is designed to latch.

The address conversion circuit 60 and the data conversion circuit 70 convert the data of the external data memory 90 to the CPU101.
This is a conversion device for importing into 20. The address conversion circuit 60 is the address switching circuit 40.
The address passed through, that is, the CPU (MCPUIO or 5
Address (logical address) output from CPU 20)
The data conversion circuit 70 selectively changes the data output from the external data memory 90 to form an address that is actually input to the external data memory 90. 5CPU20)
This forms the data that is actually input into the system. Control signals are used to specify the manner of conversion in each conversion circuit 60,70. In each CPU10120, data access to the external data memory 90 is performed by executing a transfer command. C based on transfer instruction
The control signals generated by the PU are MRl, MR2, MR3 (
For MCPUI O), SR1, SR2, SR3 (S
(in case of CPU 20). These signals are sent to the external memory address switch 30 and the address switching circuit 40.
After passing through, the signals are called R1, R2, R3 (MRi
+LMRi→Ri or SRi+LSRi+Ri),
Control signals R1 and R2 are input to address conversion circuit 60 to specify the mode of conversion. Furthermore, in order to specify the S type of conversion in the data conversion circuit 70, the control signal R1
, R2, R3, address bit 12 signal AI2 from address conversion circuit 60, and address bit 15 signal A1.
5 is added to the data conversion circuit 70. Details of the address conversion circuit 60 and data conversion circuit 70 will be described later.

In order to define the interface between MCPUIO and 5 CPUs 20, a plurality of signals are transmitted between both CPUs. Signal A is 5C sent from MCPU 10 to 5CPU 20
A signal indicating the start of processing of PU20, signal B is 5CPU2
0 to the MCPUIO indicating the completion of processing of the 5CPU 20, Ma is the internal memory of the 5CPU 20 sent from the MCPUIO to the 5CPU 20 (206 in FIG. 3)
address information, signal C is MCPU 10 to 5 CPU
The read/write control signal of the internal memory of the 5 CPU 20 is sent to the MCPUIO, Din is the read data from the internal memory of the 5 CPU 20, which is sent from the 5 CPU 20 to the MCPUIO, D
oUT is sent from MCPUIO to 5CPU205
Represents data written to the internal memory of the CPU 20,
Details of the inter-CPU interface will be described later.

As mentioned above, MCPUIO and 5 CPU
20, a digital musical tone signal is generated. The generated result is M
From CPUIO, right DAC100R and left DAC100L
The signal is sent to a digital-to-analog converter (DAC) Zoo consisting of , and is converted into an analog musical tone signal and output to the outside.

<Configuration of MCPU and 5CPU (Figs. 2 and 3)> Fig. 2 shows the internal structure of MCPUIO, and Fig. 3 shows the structure of 5CPU2.
The internal structure of 0 is shown.

In FIG. 2, the control ROM 102 stores a main program for processing various control inputs of the musical instrument and an interrupt processing program for generating musical tones. Program words (commands) in
In the specific embodiment, the program word length is 28 bits, and part of the program word is located at the lower address of the address storing the program word to be read next. ROM address control unit 11 as part (intra-page address)
The next address method is entered in 4, but
A program counter method may be used instead, RA
When the operand of the instruction from the control ROM 102 specifies a register, the M address control unit 114 controls the RA
Specifies the address of the corresponding register in M106.

The RAM 106 is a group of registers constituting a calculation memory, and is used for general-purpose calculations, flag calculations, musical tone calculations, and the like. The ALU section (addition/subtractor and logic operation section) 108 and multiplier 110 are used when the instruction from the control ROMIO 2 is an operation instruction.

In particular, the multiplier 110 is used to calculate musical waveforms, and as an optimization for this purpose, it multiplies the first and second data inputs (for example, 16-bit data) to obtain data of the same length (16 bits) as the input. It is designed to be output. Above RA
M106, adder/subtractor 108, and multiplier 110 constitute an arithmetic circuit. The operation-on control circuit 112 decodes the operation code of the instruction from the control ROM 102 and sends a control signal (indicated by CNTR) to each part of the circuit in order to execute the instructed operation. In addition, when executing a conditional branch instruction, the operation control circuit 112
detects the establishment of a branch condition based on the status signal S (for example, an overflow signal, a zero flag signal, etc.) from the ALU unit 108 and jumps the address to the branch destination address via the ROM address control unit 114.

In order to execute the musical tone generation program in the control ROM 102 at predetermined intervals, this embodiment employs a timer interrupt. That is, the interrupt generation section 116 having a timer (hardware counter) sends a control signal IN to the ROM address control section 114 at regular intervals.
T, (interrupt request signal) is sent, and this signal causes the ROM to
The address control unit 114 sets the address of the next main program instruction iI! (retained) and instead sets the start address of the interrupt processing program (subroutine) in which musical tones are generated. This starts the interrupt processing program. Since the aS of the interrupt processing program has a return instruction, when this return instruction is decoded by the operation control circuit 112, the ROM address control unit 114 sets the saved address again and returns to the main program. . Furthermore, the control signal I from the interrupt generator 116
NT uses DACloo to determine the digital/analog conversion sampling rate of musical tone signals in DACloo.
is supplied to Note that although the interrupt generation unit 116 is depicted as an internal element of MCPUIO in the diagram,
It requests the CPUIO to stop the work it is currently doing and perform special processing, and logically the MCPUIO
It is an external element (peripheral M) of

The clock generation circuit 136 receives two-phase master claw signals CKI and CK2 from a master clock generation circuit (not shown), and generates various timing signals (T1 ．．
T2, T3, TlCK1, T2CK2, T3CK3, etc.)
occurs.

The remaining elements of FIG. 2 relate to interfacing MCPU 20 with external devices. 122 represents a gate as a bus interface for connecting the MCPU internal path to the external memory access address bus MA (FIG. 1), and 124 represents a gate for connecting the MCPU internal path to the external memory data bus MD. , 126 is DA
Represents a gate for connecting the MCPU internal path to the C data transfer path, and also includes an input capo (118) and an output capo (118).
120 is an interface for coupling the MCPU internal path to an external input device. 128 is 5 CPU internal R
132 is a gate for connecting the MCPU internal bus to the AM addressing path; 130 is a gate for connecting the MCPU internal path to the 5CPU internal RAM write data bus;
represents a gate for connecting the 5CPU internal RAM read data bus to the MCPU internal path.

The 5CPU reset control unit 134 is a device for managing the operating period of the 5CPU 20. According to this embodiment, the 5 CPU reset control section 134
In response to the interrupt signal INT from 16, 5CP
A signal A indicating the start of processing of U20 is generated. This signal A
is sent to the ROM address control unit 214 (FIG. 3) of the 5 CPU 20, thereby starting the address updating operation of the ROM address control unit 214, and starting the operation of the 5 CPU 20 (including sound source processing). When the operation of the 5 CPU 20 is completed, a signal B indicating the end of processing is generated from the operation control circuit 212 of the 5 CPU 20, and this signal B is sent to the 5 CPU 20.
It is sent to the reset control section 134. On the other hand, 5CP
The U reset control unit 134 inverts the signal A in order to stop the operation of the 5 CPU 20, thereby causing the R of the 5 CPU 20 to stop.
The 5 CPU stops the operation of the OM address control unit 214 and indicates that the 5 CPU 20 is stopped.
A status flag signal is sent to operation control circuit 112. The operation control circuit 112 is a control ROM 102
When executing the 5CPU status inspection command from
By reading the U status flag signal, the status of the 5 CPUs 20 can be detected.

In the block diagram of the 5 CPU 20 in FIG.
2.202a, 204.205 206.208.21
2.214.222.224.236 are the second
Element 102 in the MCPUIO blow diagram of the figure.
102a, 104.105.106.108.110.
This is an element corresponding to 112.114.122.124.136. However, the control ROM 202 of 5 CPU 20
Basically, only programs for sound source processing are stored in the 5 CPU 20, and the 5 CPU 20 functions as a processing device exclusively for sound source processing.

240 is RAM2 as a memory for calculation of 5CPU20
The data input to 06 is the data from MCPUIO (M
Gate 130. from CPUIO. Data bus D0LII
This is a RAM data-in switching unit that selects between data (data passed through the CPU 20) and data generated (operation RAM data-in switching section 24
0 has its selection mode controlled by signal A;
When indicates "5CPU20 in operation", 5C
Select the data calculated by PU20, and signal A is “5CP”.
When "U20 is stopped" is displayed, data from MCPUIO is selected.

The mode of the RAM address control unit 205 is also controlled by the signal A, and when the signal A indicates "5 CPU 20 in operation", the RAM address control unit 205 inputs the information on the path SA from the instruction output latch 202a of the control ROM.
Selected as the address of AM206, and the signal A is “5CP”.
When "U20 is stopped" is displayed, information from the MCPUIO on the path Ma is transferred from the MCPUIO to the RAM 20 via the pass gate 128 (opened by signal A).
Select it as address 6. Similarly, the mode of the write signal switching section 242 is controlled by the signal A,
When the signal A indicates "5CPU20 in operation", the RAM read/write signal from the operation control circuit 212 of the 5CPU20 is selected and coupled to the read/write input R/W of the RAM 206, and the signal A indicates "5CPU20 in operation".
When “stopped” is displayed, S is sent from the operation control circuit 112 of the MCFUIO instead of the 5CPU 20.
Select CPDRAM read/write signal and write to RAM206
It is coupled to the read/write input R/W of.

Below, various features of this embodiment will be explained in more detail.

Multiple CPU sound source functions (Figures 1 to 7, Figures 9 to 11) Figure 4 is a flowchart showing the operation of MCPUIO by the MCPUIO main program (background program), and Figure 5 is a timer interrupt signal. a flowchart showing the operation of MCPUlo by the interrupt processing routine of MCPUlo started by INT;
FIG. 6 is a flowchart showing the operation of the 5CPU 20 by the program of the 5CPU 20 activated by the timer interrupt signal INT, and FIG. 7 shows the MCPUIO and 5C
It is a flowchart of the sound source processing which each PU20 performs.

As mentioned in relation to @1-351J, the electronic musical instrument processing system of this embodiment is equipped with a plurality of CPUs consisting of an MCPUIO and 5 CPUs 20, and both CPUs cooperate to execute processing for the electronic musical instrument. . In particular, the MCPUIO processes the sound source using an interrupt processing routine as shown in Figure 5, the 5CPU 20 processes the sound source using a program as shown in Figure 6, and the MCPUIO processes the entire system using the main program shown in Figure 4. Perform various tasks for control.

In the main program flow shown in Figure 4, 4-1 is the process to initialize the system when the power is turned on, and 1MCP
Ul0 clears RAM106 and RAM206, sets initial values such as rhythm tempo, etc. 4-2 is MCPU
IO outputs a signal for key scanning from the output port 120, and receives the status of input devices such as the keyboard and function switches from the input port 118, so that the function keys, I! The state of the keyboard keys is stored in the key buffer area of the RAM 106. In 4-3, the function key whose state has changed is identified from the new state of the function key obtained in 4-2 and the previous state,
Execute the instructed functions (for example, set musical tone numbers, set envelope numbers, set rhythm numbers, etc.).In 4-4, based on the latest and previous states of the keyboard obtained in 4-2, In 4-5, which identifies the changed key (key press, key release), perform key assignment processing for pronunciation processing 4-9 from the processing result in 4-4. In 4-6, demonstrate using function keys. When a performance key is pressed, demo performance data (sequencer data) is sequentially read out from the external memory 90 and processed, thereby performing key assignment processing for the sound generation processing 4-9.

In step 4-7, when the rhythm start key is pressed, rhythm data is sequentially read out from the external memory 90, and sound generation processing 4 is performed.
In flow-period timer processing 4-8, which performs key 7 sign processing for -9, flow-open time (this is executed during one cycle of the flow) in order to know the timing of events required in the main flow. The calculation I
4 in 0 sound processing 4-9 to obtain the reference value for the envelope timer (envelope calculation cycle) and rhythm.
- From the data set in 5.4-6.4-7, perform various calculations to actually produce musical tones, and send the results to RA.
M106. Sound source processing register (11th
(Figure). 4-10 is a preparation process for the next main flow pass, in which the NEW ON state indicating a change to the key pressed state obtained in the current pass is set to ON, or the NEW indicating a change to the key released state is set to ON. Processing such as changing the OFF state to OFF is performed.

Interrupt signal INT from interrupt generation section 116
occurs, the MCPUIO interrupts the main program being executed, and the 5th v! The interrupt processing routine shown in J is executed, and the 5 CPU 20 executes the program shown in FIG. Here, the MCPUIO generates a musical tone signal in the flow shown in FIG. 5, and the 5CPU 20 generates a musical tone signal in the flow shown in FIG.

Specifically, the MCPUIO generates, accumulates, and stores musical waveform data for each channel at 5-1. Conventionally, this process was performed by the sound source circuit hardware, but in the 0th order interrupt processing timer process 5-2, the MCPUIO takes advantage of the fact that interrupts take a certain period of time,
Flow - timer register for cycle timing (in RAM 106)
Each time e passes, add l. In 5-3, the MCPUIO checks whether the sound source processing 6-1 of the 5CPU20 has been completed, and if it has been completed, the process proceeds to 5-4 and the MCPUIO
The musical sound waveform data on the RAM 206 generated in
Read into AM106.

Then, in step 5-5, the MCPUIO outputs the musical tone waveform data generated by the MCPUIO and the musical tone waveform data generated by the CPU 20 to the DACloo.

Details of the sound source processing 5-1.6-1 are shown in FIG. 7. In this example, each CPU (MCPUIO1scpU20) can generate musical waveform data for 8 channels,
As a whole, the system can generate musical waveform data for 16 channels. Clear the waveform addition RAM area (RAMI06, RAM206) in 7-1, and
In steps 2 to 7-9, sound source processing for each channel from the first channel to the W48 channel is sequentially executed. At the end of each channel sound source processing, the tone #-shaped value of the channel is added to the data in the waveform addition RAM area.

Next, an example of channel sound source processing will be described with reference to FIGS. 9 to 11. In this example, the PC to read out the waveform
M) method of musical sound synthesis is adopted (other musical sound synthesis methods, such as FM synthesis, are also possible, and this invention is not limited to a specific musical sound synthesis method). Channel sound source processing can be broadly divided into envelope and Processing (9-1 to 9-7)
and waveform processing including envelope addition (9-8 to 9-2
1). Each CPU (MCPUIO, 5CPU
20) is a group of sound source processing registers for the channel when executing channel sound source processing, that is, as shown in FIG.
y, current envelope, address addition value, loop address, end address, start address and current address, and update the desired register. The envelope should be added to the basic waveform for amplitude modulation, and consists of several segments (steps) as a whole. The timer for the envelope Δχ, the target envelope, the envelope ΔX, and the envelope with addition/subtraction flag Δy are envelope parameters that define the envelope segment currently in progress, and these envelope parameters are:
MCPUIO main program (Figure 4) pronunciation %F
In i4-9, this is information that is updated each time the envelope value reaches the target value of the segment, and in the interrupt processing routine (Figures 5 and 6), these envelope parameters are used except for the timer for envelope Δχ. It is simply referenced. The envelope ΔX represents the calculation cycle of the envelope, the target envelope represents the target value of the envelope in the current segment, the envelope Δy with addition/subtraction flag represents the change in the envelope for each calculation cycle, and the current envelope represents the current envelope value. Address addition value, loop address,
The end address and start address/current address are address information for the basic waveform stored in the external memory 90, the start address is the start address of the basic waveform memory (in the external memory 90), and the loop address is the return address when repeatedly reading the basic waveform. Destination address (3
In Figure 10, the end address represents the end address of the basic waveform, the current address is the address that represents the current phase of the basic waveform, and the integer part is the memory that actually exists in the basic waveform memory. The address add value is the value to be added to the current address at each time interval of the timer interrupt handling routine, and is directly proportional to the pitch of the tone being generated.

To explain in detail, in 9-1, the envelope calculation period ΔX
Increment the timer register for comparison with
The addition/subtraction flag (sign bit) of the envelope displacement data Δy is tested to determine whether the envelope is rising or falling.

9-4. In 9-5, the current envelope is subtracted or added, respectively. In 9-6, it is checked whether the current envelope has reached the target envelope value, and if it has, the target level is set in the current envelope. . This causes the next envelope step data to be set in the main program's sound generation process 4-9. Furthermore, when the current envelope of zero is read in the sound generation process 4-9, it is processed as the end of sound generation.

Next, waveform processing 9-8 to 9-21 will be described. In waveform processing, the integer part of the current address is used to read the waveform data of two adjacent addresses from the basic waveform memory.
The waveform value to be added to the current address indicated by (integer part ten decimal part) is obtained by interpolation. The reason why interpolation is necessary is 1. This is because the waveform sampling period due to the timer interrupt is constant, and the added value of the address (pitch data) covers a certain range in application to musical instruments. It is preferable to play back the original sound at a faster cycle than the recording sampling cycle of the original sound, since the deterioration of tone and distortion due to interpolation are more pronounced in the high range (although there is no need for supplementation, it would result in an unacceptable increase in storage capacity). , in this example, the original sound (4
, -4) The playback period is doubled (FIG. 10). Therefore, when the address addition value is L5, an A4 sound is obtained. In this case, the address addition value is (1,529) for A#4, and 1 for A3.These address addition values are stored as pitch data in the control data/waveform external memory 90, When a key is pressed, the pitch data corresponding to the key, the waveform start address, waveform end address, and waveform loop address of the selected tone are stored in the RAM 10 in the sound generation process 4-9.
6 or the corresponding register of RAM 206, i.e.
Set in the address addition value register, start address/current address register, end address register, and loop address register.

-For reference, in Figure 1 θ which shows interpolated waveform data with respect to time, white circles indicate waveform data values stored in the storage location of the basic waveform memory, and x marks indicate output samples including interpolated values.

There are various interpolation methods, but here we use linear interpolation. In detail, first, in step 9-8, the address addition value is added to the current address to obtain a new current address. Compare the current address and end address at 9-9-, and if current address > end address, 9-10.9
-11, if the current address is the end address, calculate the next physical (address) or logical (operational) address using 9-12, and use the integer part to store the basic waveform memory in 9-14. Access to get the next waveform data. The loop address is operationally the next address after the end address. That is, in the case of FIG. 10, the illustrated waveform is repeatedly read out. Therefore, when the current address = end address, the waveform data of the loop address is read as the next address (9-13), 9-15.9
-16 accesses the basic waveform with the integer part of the current address and reads the current waveform data.9-17
Subtract the current waveform value from the next waveform value with 9-18, multiply the difference by the decimal part of the current address, and use the result with 9-1
In step 9, the linearly interpolated value of the waveform is obtained by adding it to the current waveform value. This linearly interpolated data is multiplied by the current envelope value to obtain the musical tone data value of the channel (9-2
0), and adds it to the contents of the waveform addition register to accumulate musical tone data (9-21).The digital musical tone data accumulated in this register is added to the contents of the waveform addition register (9-21). 5 and sent to the DAC 100. In this regard, in FIG. 1, DACloo consists of a right DAC 100R and a left DAC 100L to obtain a stereo output.

In this case, it is preferable to decide which of the left and right DACs to assign each of the sound source channels processed by the MCPUIO and 5 CPUs 20. Specifically, the sound source data for each channel is stored on the internal RAM 10B, 206, and the selected DAC It also has two waveform addition areas, namely a waveform addition area for the left DAC and a waveform addition area for the left DAC.
Provide an area for waveform addition. In addition, in the step corresponding to 7-1, each waveform addition area for the left and right DACs is cleared, and after the processing in 9-20, the DAC assigned to the processing channel is determined from the selected DAC instruction data, and the corresponding Add the musical waveform data of the processing channel to the waveform addition area. Then, in the step corresponding to step 5-4 of the interrupt processing routine of the MCPUIO (FIG. 5), the musical waveform data for the left DAC and the musical waveform data for the right DAC generated by the 5CPU 20 are converted into the musical waveform data for the left DAC generated by the MCPUIO. Add the musical waveform data for the DAC and the musical waveform data for the right DAC, and add the addition results to the left DAC and right DA.
C musical tone waveform data in steps corresponding to 5-5,
The signals are sent to the left DAC 100L and right DAC 100R, respectively.

In this way, the electronic musical instrument processing device of this embodiment is an MCPU.
It has multiple CPUs, IO and 5CPU20, and each CPU
In U, sound source processing can be executed according to a built-in program. In the example, one 5 CPU
However, a plurality of 5 CPUs may be provided to perform sound source processing.

<5CPU operation start/end function (Figures 12 to 15, Figures 2 to 6, and Figure 8)> According to this embodiment, the MCPUIO has a function to manage and understand the operation period of the 5CPUs 20. .

For this purpose, (a) MCPUIO is the timer interrupt generator 11.
When an interrupt signal is generated from 6, 5 uses this as a signal to start the operation of 5CPU 20, and sets the 5CPU status flag referred to by the operation control circuit 112 of MCPUIO to "5CPU in operation".

(b) When the SCPU 20 completes the operation (sound source processing), it responds to the stop state, sends an operation completion signal to the MCPUIO, and sets the 5CPU status flag referenced by the operation control circuit 112 of the MCPUlo to "5CP".
Set to "U Stopping".

Referring to FIGS. 2 to 6, the MCPUIO interrupts the interrupt generation section 1 during execution of the main program (FIG. 4).
When an interrupt signal is received from 16 (Fig. 2), RO
The main program is interrupted via the M address control unit 114, and a timer interrupt processing routine shown in FIG. 5 is executed to generate musical tones. Furthermore, in response to the interrupt signal, the MCPUIO sends a 5CPU operation start signal A to the 5CPU 20 via the 5CPU reset control unit 134,
In response to this, the 5CPU 20 controls the ROM address control unit 21.
4 to execute the program for musical tone generation shown in FIG.
The M address control section 204, the RAM data-in switching section 240, and the write signal switching section 242 also have 5 CPUs 20.
(set for its own behavior). Upon completion of this program, the 5CPU 20 operates the operation control circuit 2.
12 generates an operation completion signal B. This signal B is 5C
It is sent to the PU reset control unit 134, and in response, the 5C
The PU reset control unit 134 inverts the signals A and B to stop the operation of the 5 CPU 20. Upon receiving the inverted signal A, the address updating operation of the ROM address control unit 214 of the 5 CPU 20 is stopped, and the 5 CPU 20 is stopped. In addition, signal B is used as a signal indicating "5 CPU is stopped" by the MCP.
The signal is applied to the operation control circuit 112 of the UIO.

When executing the 5cpuB state check command shown in 5-3 of the MCPUlo interrupt processing routine (Figure 5), the MCPUlo
The PUIO operating controller control circuit 112 reads the 5CPU status flag B, and the flag B indicates "5CPU is stopped", so the sound source processing by the 5CPU 20 is performed (Fig. 6).
is completed, MCPUIO advances to 5-4 and 5
MC reads the musical waveform data generated by the CPU 20
PUIO gives a command signal for returning to the main program from the operation control circuit 112 to the ROM address control section 114 at the end of the increment processing routine shown in FIG. 5, thereby returning control to the interrupted main program.

FIG. 8 shows the flow of the operation of this embodiment along the flow of time, and A to F are fragments of the main program. 5A~5
F represents the MCPU interrupt processing routine in FIG. 5, and 6A to 6F represent the 5CPU interrupt processing routine in FIG. 6. As shown in FIG.
When T occurs, MCPUIO interrupts the program being executed, interrupt processing is started in each CPU10120, and parallel processing of sound sources is executed.

FIG. 12 shows in detail the configuration that realizes the operation start and end functions of the 5 CPUs mentioned above, and FIGS. 13 to 15 show time charts of the operations. In the time chart of FIG. 13, CKI and CK2 are MCPUlo and 5CPU2
This is a two-phase master clock that is input to the RI o +7 ri generation circuits 136 and 236 at 0, and this master clock CK1 and CK2 may also be input to the clock generation circuit 136.
A three-phase clock T1. provides basic timing for CPUIO operations. Generate T2 and T3. The repetition period of this three-phase clock determines the machine cycle (shortest instruction execution time). Clocks TlCK1, T2CK2, T3
CK3 is TI and CK1. T2, CK2, T3
and CK3. The operation latch signal is a signal for causing the instruction output latch 102a of the control ROM 102 of MCPUlo to latch an instruction from the ROM 102.

Although not shown in FIG. 13, the clock circuit 236 of the 5 CPU 20 also generates a similar clock signal (see FIGS. 3 and 25). Note that a common clock generation circuit may be used for the MCPUIO and the 5 CPU 20. .

In FIG. 12, the right side of the dotted line 16 is the 5 CPU 20, and the left side is the MCPUIO. Among the elements on the left, latch L1. Latch L2, gates 1142-1154 are MC
PUIO (second (iU) R0M address control unit 114
It is a circuit element included in. MCPUI for latch Ll
ROM1027 address information A of the next instruction to be executed by O
N (information contained in the current instruction from ROM 102) is latched with clock TICKI. Main program (
During the execution of Figure 4), the output of latch Ll is the next address BN.
The address is input to the ROM address decoder 104 of the MCPUIO. That is, the output of latch Ll is output from inverter 11.
The address input BN to the ROM address decoder 104 is passed through the 44.3-state inverter gate 1146 (enabled). Here, interrupt generation part 1
When an interrupt signal INT is generated from 16, an OR gate 1154 receiving this signal INT also applies a signal to turn off (high impedance) the 3-state inverter (3-state inverter) 1146 on the output side of latch Ll via inverter 1148. Instead, by the OR game) 1154 signal, the interrupter / return destination address selection game) 11
A three-state inverter (gate) 1152 on the output side of gate 1150 converts the output of gate 1150 to ROM address decoder 104.
The 0 interrupt λ low/return address selection gate 1150 that passes through the address input BN of the interrupt signal INT and the latch L
It consists of a group of NOR gates that receive output signals from 2,
“H” interrupt signal ■When NT occurs, interrupt processing routine (Figure 5) is input p (second entry point)
This signal is inverted by a 3-state inverter (1152) and outputs an all "θ" signal representing
'' is input to the ROM address decoder 104 of the MCPU as the signal BN.Then, the next operation 1 latch signal causes the instruction,
The first instruction of the interrupt processing routine is fetched into the output latch 102a.
Control then moves to the interact processing routine.

Further, the interrupt signal INT from the interrupt generating section 116 passes through the AND gate (1142) at the timing of the clock 72CK2, and operates the latch L2 as a latch signal. As a result, latch L2 saves the address of the next instruction of the main program on path AN.
to interrupt the main program.

Furthermore, the interrupt signal INT from the interrupt generating section 1]6 is supplied to the 5 CPU reset control section 134.

The 5 CPU reset control section 134 includes a D-free 7-flop 1342 and a NAND gate 13 connected as shown in the figure.
44, R-S flip-flop 1346. During execution of the main program, the R-S flip-flop 134
6 is in a reset state (Q="L"), and an R-S flip-flop 7'1346 (not shown) is initialized to a reset state when the system is powered on.

The interrupt signal INT is taken into the D flip-flop 1342 at the timing of the clock 72CK1, and the NAND gate is input at the timing of the next clock TICKI.
It is inverted and output from 1344 and sets an R-S flip-flop 1346. As a result, the Q output of the R-5:y flip-flop 1346, that is, the signal A, changes from "H" to "L", and the Q output, that is, the 5 CPU status flag changes from "L" (indicating that the SCPU is stopped). “H” (SC
(indicates that the PU is in operation). Signal A is 5CPU2
This signal is input to latch L3 for latching the address SAN of the next instruction at 0 as a reset release signal (latch L3 enable signal). As a result, the latch L3 inputs the address of the first instruction of the 5 CPU program (FIG. 6) on the path SAN to the ROM address decoder 204 of the 5 CPU 20 as SBN at the timing of the next clock TlCK1. In this way, the operation of the 5 CPU 20 is started in response to the interrupt signal INT from the interrupt generating section 116, and the sound source processing shown in FIG. 6 is executed.

5 When the CPU 20 executes the instructions after 1& of sound source processing,
An operation end signal (return command signal) SRT is generated inside the operation control circuit l12 of the 5CPU 20.

This signal SRT is taken into the D flip-flop 2122 at the timing of clock T2CK1, and then the next TI
The NAND gate 2124, which operates at the CKI timing (latch timing of the next dummy instruction), inverts the
The R-S flip-flop 1346 of the 5 CPU reset control unit 134 is reset as the operation end signal B of the 〇-pulse. As a result, the Q output of the R-S flip-flop 1346, that is, the signal A switches from "L" to "H".
The Q output, that is, the 5CPU status flag switches from "H" indicating that the 5CPU is operating to "L" indicating that the 5cPU 20 is stopped. By “H” level signal A (reset signal),
The operation of latch L3 is prohibited, and the output of latch L3, that is, the input of address decoder 204 is
r instruction) address. At this time, latch L3
Address information (included in the NoP instruction word) of the first instruction of the 5-CPU sound source processing program (FIG. 6) is placed on the input path SAN.

The MCPUIO executes the 5CPU status check instruction 5-3 of the interrupt processing routine (FIG. 5), and in particular checks the level of the 5CPU status flag via the operation control circuit 112 to determine whether the 5CPU is stopped, that is, the sound source processing of the 5CPU 20 is completed. After checking, the musical sound waveform data that is the processing result of the 5 CPU 20 is read from the RAM 206 to the RAM 106 (5-4), so that the MCPUIO
20 correct processing results can be efficiently obtained.

MCPUIO generates a pulse of the return command signal RT from the operation control circuit 112 when executing the last instruction of the interrupt processing routine. This signal pulse R
T passes through OR gate 1654 and input/hater 1148, and temporarily turns off address information (1146) on the output side of latch Ll, and instead connects to latch L2 (interrupt/return destination address selection gate). Address gate 1152 on the output side of 1150 is temporarily opened. At this point, interrupt/return destination address selection gate 1150 is used to store the instruction of the interrupted main program saved in latch L2. The inverted output of this gate 1150 is inverted again by a signal pulse RT in a three-state gate 1152 which serves as an inverter. As a result, the address of the instruction of the interrupted main program is input to the ROM address decoder 104 of the MCPUIO, and the instruction is taken out from the control ROM 102 via the instruction output latch 102a in response to the next operation latch signal. In this way, control of MCPUIO returns to the main program.

As described above, the electronic musical instrument processing device of this embodiment has the MCP
Management of the operating period of 5 CPUs 20 by UlO is performed by 5 CPUs.
By providing a simple management interface configuration such as the reset control unit 134, this can be done efficiently and reliably.

Multiple data transfer> In certain applications that use the CPU,
updates multiple data during execution of the main program (first program), and updates the interrupt processing routine (
When the second program) is executed, these multiple pieces of data are referenced for the purpose of processing. This is the problem of passing data from the main program to the interrupt handling routine. Such multiple data must be updated in the main program before the main program is interrupted by the interrupt processing routine, or interrupted when the main program has updated only part of the multiple data. If the CPU control is transferred to the interrupt processing routine, the processing result of the interrupt processing routine will be incorrect.

In the case of the electronic musical instrument processing device of this embodiment as well, a plurality of messages are passed from the MCPUIO main program (Fig. 4) to the MCPUIO timer interrupt processing routine (Fig. 5) (and the 5 CPU 20 timer interrupt processing routine shown in Fig. 6). There is data on. Envelope ΔX (envelope calculation cycle), envelope Δy with addition/subtraction flux (
An example is an envelope parameter consisting of a target envelope (envelope change amount). The external data memory 90, which is a data source, stores envelope parameters for each envelope segment (eg, attack segment, decay segment, sustain segment, etc.). The main program of MCPUlo is sound processing 4
-9, when the envelope reaches the target value (9-6, 9-
7), the envelope parameters (new target envelope, envelope Δx, envelope with adjustment Δy) for a predetermined segment are retrieved from the external data memory 90 and stored in the MCPU internal RAM 106.
It is necessary to update the envelope parameters consisting of a plurality of data by setting them in the corresponding channel sound source processing registers (or 5 CPU internal RAM 206). Such a plurality of data must be updated in the main program before the main program is interrupted by the interrupt signal INT from the interrupt generating section 116.

In order to solve the problem of multiple data transfers (updates), this embodiment discloses two solutions. 1st
The solution to this problem is an interrupt masking method that masks interrupts during data updating so that the execution of the main program's data update instructions is not interrupted.
The solution to this problem is a one-instruction one-instruction method that utilizes the function of executing multiple data transfers with one instruction.

Interrupt mask formula (16th, 17th, 2nd to 7th
(Figure) According to this method, the interrupt from the interrupt generation unit 116 is masked while data is set in the channel sound source register group of the internal RAM by the data update command group in the main program, especially in the sound generation process 4-9, and the interrupt from the MCPUIO (7) #jI control the main program (
4) to the interrupt processing routine (FIG. 5) is prohibited.

Figure 17 shows envelope processing including multiple data transfers (
Fig. 16 shows the hardware related to the interrupt mask.

In Figure 17, MCPUIO is specified by 17-1 flt
Check whether the channel's current envelope has reached the target envelope. If it reaches MCPUIO
goes to step 17-2 and retrieves the envelope parameters for the next envelope segment from the external data memory 90 (FIG. 1): new target envelope, envelope Δy with addition/subtraction flag, envelope Δ)
, and set it in the transfer buffer in the internal RAM 106.

Here, the transfer buffer is an intermediate storage unit between the data number and the data destination, and is used in the interrupt processing routine (9th
Since this is a RAM area that is not referenced by (Figure), an interrupt mask is not required at this point. The reason for providing the transfer buffer is that the data source memory 90 is the MCPU.
This is because the external memory is shared by the IO and the five CPUs 20, and its data access time is longer than the data transfer time between internal RAMs. Block 17=2
This function is processed by sequentially executing a plurality of data transfer commands from the external data memory 90 to the internal RAM 100.

Data transfer from the transfer buffer to the channel sound source register group (referenced in the interrupt processing routine) is executed in block 17-4. To prevent MCPUIO control from shifting to the timer interrupt processing routine (Figure 5) during this data transfer (or
In order to prevent the control of the CPU 20 from shifting to the program shown in FIG.
Prior to this, an instruction to mask the interrupt is executed in block 17-3. During execution of this interrupt mask command, a low active mask signal MASK is generated from the operation control circuit 112 of the MCPUIO.

This mask signal MASK' is transmitted to the interrupt generating section 116.
It functions to mask the insect interrupt signal INT and prohibit transfer of control to the interrupt processing routine (FIGS. 5 and 6). For this purpose, in FIG. 16, a mask release special section 150 coupled to the interrupt generating section 116 is provided. Mask release special equipment part 15
0 is an R-S flip-flop 15 coupled as shown.
02, an AND gate 1504, and a D flip-flop 1506.

When the mask signal MASK is at the "H" level indicating mask release, the R-S flip-flop 1502 is set by the interrupt signal INT from the interrupt generating section 116, and its output is the AND signal enabled by the "H" MASK. Through the gate, the D flip-flop 1506 receives TICKI (at timing 75), and the output of this D flip-flop 1506 is input to the MCPUIO R as the actual interrupt signal A-I NT.
It is input to the OM address control section 114. As a result, 5
As mentioned in the CPU operation start/end function, R
OM address control part 114 game) 1152 to RO
The address of the entry point of the interrupt processing routine (FIG. 5) is input to the M address decoder 104, and the address of the next main program instruction is saved from path AN to latch L2, and the control of MCPUIO starts interrupt processing. A transition is made to the routine, and the main program is interrupted. Also 5, signal A-I NT is 5CP
is input to the U reset control unit 134, and as a result, 5CP
As mentioned in the U operation start/end function, S(1:
, the program (FIG. 7) operation of the PU 20 starts. D
The H level output from the flip-flop 1506 is R-
S flip-flop 1502 is reset, resulting in
At the timing of the next TICKI, D flip-flop 7p15
The output of 06 (output of the mask release special unit 150) is switched to the L level.

In response to peeling, when a low active mask signal MASK is input from the operation control circuit 112 to the mask release standby 11A150 by executing the interrupt mask command as shown in 17-3 in FIG. The interrupt signal from 116 is masked by AND gate 1504. As a result, the mask release special unit 1504 sets its output A-INT to the "L" interrupt disable level while the mask signal MASK is low active, continues the normal operation of the ROM address control circuit 114, and maintains the main Allow program control to continue.

Therefore, the execution of the transfer command group (and the clear command for the envelope Δχ timer) shown in block 17-4 is as follows:
Even if the interrupt signal INT is generated from the interrupt generation unit 116 during execution, the interrupt processing routine (IIF! 5, 6) can refer to the correctly updated envelope parameters, and the correct Computation results (music waveform data) can be obtained.

Thereafter, MCPUIO executes the interrupt mask release instruction shown in block 17-5. As a result, the signal MASK supplied from the operation control circuit 112 to the mask release special unit 150 switches to the "H" level indicating mask release. Block 17-4 containing multiple data transfers
If an interrupt signal is generated from the interrupt generation section 116 during the execution of
By the output of the RS flip-flop 1502 of 50, the interrupt request is accepted after execution of this mask release instruction, the main program is interrupted as described above, and control is transferred to the interrupt processing routine.

(Figures 18 to 21) This method is called a long instruction in order to save multiple pieces of data in the main program (Figure 4) to the internal RAM area referred to by the interrupt processing routine. A single instruction for bulk transfer of multiple data is used, and control of the MCPUIO is not transferred to the interrupt processing routine until the execution of the long instruction is completed.

A CPU capable of transferring a plurality of data with a single instruction (long instruction) is disclosed, for example, in Japanese Patent Publication No. 47612/1983, and this technique can be applied to this embodiment. Special Public Service 1986-
According to No. 47612, the long instruction can be applied to transfer between multiple registers at consecutive addresses (for example, registers AO to A3 to registers Be to B3) (here, register means one memory location in RAM). and A and B are R
Represents the upper address of AM, that is, the row address, and is 0.3
represents the lower address of RAM, that is, the column address),
The long instruction word from the control ROM (corresponding to element 102 in this embodiment) includes the row address of the first register (A in the above example) and the row address (B) of the destination register.

Column address (O) of the register related to the first data transfer,
Contains information on the column address (3) of the register related to the last data transfer. The RAM address control unit (corresponding to element 105 in this embodiment) is configured to be suitable for executing long instructions, and changes the column address by 1 for each data transfer from the column address of the first transfer to the column address of the last transfer. To detect that all data transfers have been completed, the counter output is compared with the column address value of the last data transfer, and if they match. and a matching circuit that sometimes generates a long instruction execution completion signal.

In the following description, it is assumed that the main program of the control ROM 102 of this embodiment includes the above-mentioned long instructions, and the RAM address control unit 105.205
It is assumed that the configuration is such that the execution of long instructions can be applied as described above.

Figure 18 shows that during the execution of a long instruction, the interrupt signal IN
A block diagram of the hardware including a circuit that prohibits interruption of the main program by T is shown. Figure 19m shows the memory map of the RAM when the long instruction is applied to envelope parameter transfer. Figure 20 shows the long instruction. order(
FIG. 21 shows a flowchart related to envelope parameter transfer using a long instruction.

In FIG. 18, a transfer termination special unit 152 is coupled to the interrupt generating unit 116. This circuit 152 prohibits interruption of the main program by an interrupt signal during execution of a long instruction. The transfer end special unit 152 includes R-S flip-flops 1522 and A connected as shown in the figure.
It consists of an ND gate 1524 and a D flip-flop 1526, and the output of the D flip-flop 1526 (output of the transfer end special unit 152) is used as the interrupt signal A-INT that actually acts on the ROM address control unit 214 and the 5CP.
It is coupled to the U reset control section 134. AND game)
While the signal ~LONG input to 1524 is “L”, the interrupt signal IN is output from the interrupt generation unit 116.
Even if T occurs, the output of the D flip-flop 1526 remains "L", and the ROM address control units 214 and 5
The CPU reset control unit 134 receives an interrupt signal INT.
Here, the signal ~LONG is a signal that becomes "L" during execution of the long instruction.

Upon completion of execution of the long instruction, RAM address control unit 1
It returns to "H" in response to the long instruction execution completion signal generated from the coincidence circuit 04. When the level of the signal ~LONG is H'', the interrupt signal INT from the interrupt generation unit 116 passes through the transfer end wait m152 and is sent to the ROM address control unit 214 and the 5CPU reset@@i
ll I 34 and controls the MCPUIO from the main program (Figure 4) to the interrupt processing routine (
(Fig. 5) and the 5CPU20 program (6th
Figure) Start the operation.

When applying the Ikkei lj formula to update the envelope parameters, the channel sound source processing subroutine (Fig. 9) of the interrupt processing routine (Figs. 5 and 6) refers to it, and the envelope processing subroutine (Fig. 9) of the main program The envelope parameters set (updated) in FIG. 21) are the timer for the envelope Δχ, the new target envelope 11i The data source is the external memory 90 (
1), when updating the envelope data (21-1), the data is transferred from the external data memory 90 to the internal RAM
Since direct transfer to the channel sound source data area of 06.206 is not desirable, the envelope parameters from the external data memory 90 are temporarily transferred to the transfer buffer area in the internal RAM 106 (2l-2), and then transferred to the transfer bar. , move from the F area to the channel sound source data area (
21-3).

The above-mentioned long command is used in the data transfer process 21-3 from the transfer buffer area to the channel sound source data area. In order to apply the long command, the transfer buffer area needs to be a continuous area on the RAM, and similarly the channel sound source data area of the envelope parameter needs to be a continuous area. An example of this is shown in FIG. 19. Here, the buffer area for envelope parameter transfer is a continuous area of registers x4 to x7, and the 1-channel sound source data area for envelope parameters is a continuous area of registers A4 to A7. It has been mapped. Therefore, when it is necessary to update the envelope parameters in one channel, registers x4 to x7 are transferred to register A in 21-3.
4 to A7. While this instruction is being executed, even if the interrupt signal INT is generated from the interrupt generation section 116 as described above, the long instruction of the transfer end special section 152 is executed. Due to the instruction completion standby function, the effect of the interrupt signal does not affect the ROM address control unit 114.5 CPU reset control unit 134 until the long instruction is completed (see FIG. 20(B)). Since the interact processing routine starts after all the envelope parameters have been changed to correct update values, the calculation results (music waveform data) show correct values, and error-free operation is guaranteed. , On the other hand, if the transfer processing function shown in 21-3 is attempted to be achieved by executing multiple transfer instructions (one envelope parameter is transferred for each - instruction),
During the transfer, for example, if an interrupt signal INT occurs during the execution of transfer instruction 1 as shown in FIG. 20(A), the first instruction of the interrupt processing routine will be executed instead of transfer instruction 2 in the next machine cycle. Therefore, the envelope transfer process is interrupted midway, and as a result, the processing result (music waveform data) of the interrupt processing routine becomes an incorrect value.

- 1 for multiple data transfer (update) processing using command method
There is also the advantage that there is no need to execute an interrupt mask command or an interrupt release command as shown in 7-3.17-5, and transfer processing can be performed in the shortest possible time without an overhead.

As a modified example, a transfer termination special unit 1 as shown in FIG.
52, the control ROM 10 is used during execution of a long instruction.
2. Means may be used to inhibit the operation of the instruction output latch 102a that fetches one instruction from the control ROM 102.
By the mode signal (indicating that the instruction is long) included in the long instruction word given via a,
A circuit is provided in the operation control circuit 112 to inhibit generation of an operation latch signal applied to the instruction output latches 102a and 202a, and to generate an operation latch signal in the next machine cycle in response to a long instruction execution completion signal. If so, interrupt signal IN
Even if T occurs during the execution of a long instruction, the control ROM 10
2. Since the first instruction word of the interrupt processing routine from 202 is not fetched into the instruction output latches 102a, 202a (and therefore not executed) until the execution of the long instruction is completed, the same effect as in the embodiment can be obtained.

<5CPU access function from MCPU> The device of this embodiment has access from MCPUIO to SC, internal RA of PU 20.
It has a function to access (read or write) data to M206 at high speed.

This problem is generally understood as a data access problem between multiple CPUs. In the prior art, there is a problem in that this type of inter-CPU data access takes time. In the prior art, a request signal is given from a CPU requesting access to a CPU requesting access. In response to this request signal, the CPU to which access is requested cannot immediately generate an acknowledge signal that allows data access from the requesting CPU, and delays generation of the acknowledge signal until the ongoing operation is completed. let Therefore 1. The conventional inter-CPU data access method has become one of the obstacles in applications requiring high-speed processing.

In this embodiment, two solutions are disclosed for high-speed inter-CPU data access, namely, a 5-CPU stop mode utilization method and an instantaneous forced access method.

5CPU stop mode utilization method (Figures 22, 2, and 3) This method utilizes the above-mentioned 5CPU operation start/end function. With this function, the program operation of 5CPU20 (Fig. 6) starts at the same time as the start of the interrupt processing routine (Fig. 5) in MCPUIO.
It ends before the interrupt processing routine of PUl0 ends. Therefore, while the main program (FIG. 4) is operating in the MCPUIO, the 5 CPU 20 is in the stop mode (reset state 1).As shown in FIG.
becomes “H” level indicating “5 CPU is stopped”. This signal A stops the operation of the ROM address control section 214 in the 5 CPU 20 (FIG. 3), and the RAM address control section 204 controls the ROM address control section 202 of the 5 CPU 20 (FIG. 3).
The operation mode is set so that the designated address of the 5CPU internal RAM 206 is received from the MCPUIO by connecting it to the RAM address bus Ma from MCPUlo via the passgate 128 instead of the AM address bus SA, and the RAM
The data switching unit 240 is set to an operation mode in which the data input of the RAM 206 is coupled to the data bus DoUI that carries data from the MCPUIO instead of the data bus DB that carries the operation results of the CPU 20 (the output of the ALU unit 208 or the output of the multiplier 210). , the write signal switching unit 242 is a 5-CPU operation control circuit 21.
2, but not the read/write control signal C from the operation control circuit 112.
The operating mode is set to be coupled to the read/write control of AM206. When in a stopped state like this, 5CP
U20 is placed in a state where it can access data by MCPUlO.

Therefore, according to this embodiment, the MCPUIO can freely access the internal RAM 206 of the 5 CPUs 20 in the main program. This situation is shown in FIG. 22. Confirmation of the stopped state (sound source processing completion) of the 5CPtJ20, that is, inspection of the 5CPU status flag from the 5CPU reset control unit 134 in the MCPU operation control circuit 112, is performed by the interrupt processing routine of the MCPUIO (see FIG. ) (see 5-3). Once the stop state is confirmed, there is no need to confirm again until the next interrupt signal INT is generated. , MCPUIO can access the internal RAM 206 of the 5 CPU 20. Therefore, the time required for data access to the 5 CPUs 20 is significantly reduced compared to the prior art.

Instant forced access method (Figures 23 to 825) This method allows 5 CPUs to access data from MCPUIO without going through the conventional procedure of requesting and approving access between MCPUIO and 5 CPUs 20 for data access. Sometimes, the operation of 5CPU20 is forcibly stopped,
Meanwhile, MCPUIO is 5 CPU 20 internal RAM 20
6. According to this method, MC
PUIO can access 5CPTJ20 at high speed (by executing a -instruction) without having to check the status of 5CPU20 at any time.

A block diagram of the MCPU 10 and a block diagram of the 5CPU 20 with such features are shown in Figures 23 and 2, respectively.
The MCPU and 5CPU shown in Figure 4 are elements related to the above-mentioned 5CPU operation start and end function (5C in Figure 2).
PU reset control circuit 134 and others), but their illustration is omitted in FIGS. 23 and 24 for the sake of brevity. In this case, it is sufficient to supply the 5CPU operation start/stop signal A from the reset control circuit 134 only to the ROM address control unit 214 of the 5CPU 20 (FIG. 24). Second
FIG. 25 shows a time chart of operations related to instantaneous forced access of MCPUIO and 5 CPU 20 in FIGS. 3 and 24.

When using the instantaneous forced access method, MCPUIO and 5CPU20 are separate clock generation circuits 136.236
Requires M. 5 Clock generation circuit 23 of CPU 20
6M stops its operation in response to a high active 5CPU access signal output from the operation control circuit 112M of MCPUIO when a data access instruction to 5CPU 20 is executed. In this regard, MCPUI
The clock generation circuit 136 of the CPU 20 and the clock generation circuit 236M of the 5 CPU 20 use a common two-phase master clock signal C.
K1. Although it receives CK2, the timing of the output clock is independent. In MCPUIO, clock generation circuit 1
The three-phase clock signal T1. A machine cycle (the shortest one instruction execution time) is defined by one period of T2 and T3, and in the 5 CPU 20, a three-phase clock signal ST1. ST2. One cycle of ST3 defines the machine cycle.

In FIG. 25, before the 5CPU access signal is generated, the timing of clock TI regarding MCPUIO matches the timing of clock ST2 rather than clock STI regarding 5CPU20.
Other possible timing relationships between them are T1 matching STI and TI matching Sr1.

The 5 CPU access signal output from the operation control circuit 112 during execution of the 5 CPU access instruction in MCPUIO is generated by the clock generation circuit 23 of the 5 CPU 20.
In order to stop the 6M and stop the operation being executed by the 5 CPU 2o, and to allow the MCPUIO to access the internal RAM 206 of the 5 CPU 20 during the stop, the bus gate 128.
It has a function of switching the operation mode of the address control unit 204, data-in switching unit 240, and write signal switching unit 242 from the 5CPU side to the MCPUII.For this purpose, the 5CPU access signal , 240. A D flip-flop 250 and an AN
It is coupled via a delay circuit consisting of a D gate 252. Under such an accessible state, the MCPUIO
The 5cPU internal RAM 206 is tressed via the bus gate 128 and the RAM address control unit 204, and in the case of read access, the data output from the 5CPU internal RAM 206 is sent to the MCPU via the pass gate 132.
The data is read into the internal RAM 106, and in the case of a write access, the write data is transferred to the data bus DOUT via the bus game 130, and a write signal C is given to the 5 CPU internal RAM 206 to write the data.

5 by the 5 CPU access signal from MCPUIO
When interrupting the operation of the CPU 20, it is necessary to ensure that the intermediate result of the operation is not lost, and after the 5CPU access signal is released, the 5CPU 20 can execute the remaining part of the operation using the intermediate result held in advance. It is necessary to do so. For this,
Latches 206a and 206b are provided to temporarily store data output from the 5CPU internal RAM 206. latch 2
06a is the operation number from RAM206 (first operand)
is latched at the timing of 5TICKI, and the latch 206
b latches the operand (second operand) from the RAM 206 at the timing of 5T2CK1.

An operation example will be described with reference to FIG. 25. In this example, M
The CPUIO executes write access to the internal RAM 206 of the 5 CPU 20 while the 5 CPU access signal is at a high active level. In MCPUlo, the first time slot TI of this data write operation is
During this period, transfer data (R
At the 8th time slot T2 to retrieve data (to be written to AM206), MCPUIO writes data to the 5CPU internal RAM.
Add and sing 206. At the last time slot T3, MCPUIO gives write signal C to 5 CPU internal RAM 20B and writes data to RAM 206, 5
For CFU20, the 5CPU access signal from MCPUIO changes to active when operation 2 of 5CPU 20 moves to time slow 7 ST2. This operation 2 is 5 CPU 20 RAM 20
This may be an instruction operation in which the operands and operands in No. 6 are operated on by the ALU unit 208 or the multiplier 210. At the first time slot STI of operations 1 and 2, which is the time slot immediately before the 5 CPU access time from MCPUlo, the 5 CPU 20 retrieves the data of the operation number from the RAM 106 and uses the data as the clock TI.
0 latched in the arithmetic latch 106a by CKI
If the 5CPU access signal from MCPUl0 is not generated, the 5CPU20 will access R in the next time slot ST2.
The operand is taken out from AM106 and latched to the operand lar 7ch 10b, and the AL
The U unit 108 or the multiplier llO executes the operation and stores it in the RAM.
106 operand register (actually the first timeslot of operation 2 as shown) STI
Following this, a 5 CPU access signal from MCPUIO is generated. In this case, one countermeasure is to keep the processing to be executed in the remaining two time slots ST2 and ST3 of operation 2 until the 5 CPU access signals are removed.
That is, the 5 CPU access operations of MCPUIO are suspended until they are completed. Even with this method, MCP
UIO can execute operations that access 5 CPUs 20 within the shortest time (same time as accessing MCPUIO's internal RAM 106), but this is not optimal for 5 CPUs 20, and each time a 5 CPU access operation from MCPUIO occurs, the operation of 5 CPUs 20 increases in time. This will result in a delay of three slots. Conveniently, the process performed in the first time slot TI of the MCPUIO(7) SCPU access operation is a process that does not affect the 5 CPUs 20. By utilizing this feature, in the example, 5 CPUs are
Even if an access signal is given, the 5 CPU 20 is allowed to continue its own operation during the time slot TI of the MCPUIO, thereby minimizing the delay in the operation of the 5 CPU 20. In the example of Figure 25, 5
During the first time slot TI of a 5 CPU data write operation of MCPU 10, CPU 20 writes RAM
The data of the operand is taken out from the latch 206.
A clock 5T2CK1 is applied to b to latch the operand. Thereafter, the operation of the 5CPU clock generation circuit 236 is stopped until the 5CPU access signal is removed, and the 5CPU 20 is placed in a waiting state. During this wait state, elements 128,264,240 of 5 CPU20
．． 242 is switched to the "MCPU side" by the 5CPU access signal, and the processing related to time slots T2 and T3 in the 5CPU data write operation of MCPUlo is executed, and the MC is stored in the 5CPU internal RAM 206.
Data from PUIO is written.

When the 5CPU access signal from MCPUIO is removed, the 5CPU crawl generation circuit 236 resumes operation and changes the clock ST3 to "H".
By removing the PU access signal, the elements 128.204.240.242 of the 5 CPU 20 are returned to the "5 CPU side", and the 5 CPU 20 itself becomes operable. Therefore, the 5CPU 20 stores the calculation output of the ALU section 208 or the multiplier 210 in the RAM in this time slot ST3.
20B and perform the remainder of operation 2.

As shown in the time chart of Fig. 25, 5 CPU20
The operation is interrupted for only two time slots for each 5 CPU access operation from MCPUIO.

In addition, MCPUIO is 5CPU20 internal RAM206
For a read access operation to read data from
tT addresses the internal RAM 206, addresses the MCPU internal RAM 106 at time slot T3, and takes data from the 5CPU internal RAM 206 into the MCPU internal RAM 106 via the bus 132.

As described above, according to the instantaneous forced access method, the MCPU
IO can access the internal RAM 206 of the 5 CPU 20 within the shortest possible time in the same way as access to the MCPU's own RAM 106, and there is no need to execute a waiting time instruction. Furthermore, according to the instantaneous forced access method, 5CP
The U20 operation was interrupted midway and the MCPUIO
After 5 CPU access operations, the operation can be resumed from where it was interrupted. Therefore, M
The CPUIO does not need to check the state of the 5 CPU 20 before accessing the 5 CPU 20, and can freely access the 5 CPU 20 at any time, for example, during the interrupt processing routine (FIG. 5).

Shared memory access conflict resolution function (Figs. 26, 27, and 1)> In Fig. 1, the external memory 90 is connected to multiple CPUs,
This is a data memory shared by CPUIO and 5 CPUs 20. Therefore, a means is needed to support multiple accesses to external data memory 90, ie, external data memory 90 accesses from MCPUIO and external data memory 90 accesses by five CPUs 20. Furthermore,
When sharing the external data memory 90, the MCP
It is desirable to allow the UIO and five CPUs 20 to attempt to access external data memory 90 at the same time. M.C.
External data memory 90 between PUIO and 5 CPU 20
By providing a function to exchange usage rights (tokens) for MCPUIO and 5CPU 20, it is possible to prevent the MCPUIO and 5CPU 20 from accessing the external data memory 90 at the same time, but the token procedure reduces the preparation time for accessing the external data memory. occupies the external data memory, the total time required to access the external data memory increases, making it inefficient.
On the other hand, when allowing simultaneous access to the external data memory 90 by the MCPUIO and the 5 CPUs 20, since the memory 90 itself cannot be physically accessed at the same time, a means is required to resolve access conflicts caused by simultaneous access.

In order to realize these means, as shown in Figure 1, MC
External memory address information from PUIO is coupled to the address input of external memory 90 via address bus MA, MCPU external memory address latch 30M, address switching circuit 40, and address conversion circuit 60, and data output from external memory 90. is the data conversion circuit 70. M
CPU external memory data latch 80M, data bus MD
is coupled to MCPUIO via. On the other hand, 5CP
External memory address information from U20 is sent to address bus S.
A, 5 CPU external memory address switch 30S, address switching circuit 40, and address conversion circuit 60 are connected to the address input of external memory 90. Data output from external memory 90 is connected to data conversion circuit 70, SC
The PU external memory data latch 80S is coupled to the 5 CPU 20 via the data bus SD. And M.C.P.
Signals MCPU-roma and SCPU-ro representing external data memory access requests from UIO and 5CPU 20
The memory device δ contention avoidance circuit 50 receiving the MCPU external memory address latch 30M
External memory address switch 305, address switching circuit 40, MCPU external memory data latch 80M, SC
The PU external memory data latch 80S is controlled. This memory device conflict avoidance circuit 50 includes a function to avoid the above-mentioned access conflict.

FIG. 26 shows a block diagram of the memory device conflict avoidance circuit 50, and FIG. 27 shows a time chart of operations regarding access conflicts.

In FIG. 26, the memory device contention avoidance circuit 50 receives an access request signal MCPU from MCPUIO as an input.
-roma, access request signal SC from 5 CPU 20
PU-roma, furthermore, MCPU reset signal MRES
and 5CPU reset signal 5RES (not shown in FIG. 1) are coupled. M'CPU reset signal MRE
S is set-reset circuit (R-S flip-flop) 5
02 and a reset circuit 506 coupled to its output.
The signal MCPU-roma sets the set-reset circuit 502. Set reset circuit 50
2 temporarily stores the access request from MCPUIO, and the output side set reset circuit 506 is in the set state.
Indicates that the access request from MCPUIO has been accepted and the access operation is being executed via the external memory data access control signal generation circuit 510;
Similarly, the 5CPU reset signal 5RES resets the reset circuit 504 and the set reset circuit 508 coupled to its output, and the signal 5CPU-roma sets the set reset circuit 504. The reset circuit 504 temporarily stores the access request from the 5 CPU 20, and the output side set reset circuit 508 indicates in the set state that the access request from the 5 CPU 20 has been accepted and the access operation is being executed.

In detail, the output "H" of the set state of the MCPU access request set reset circuit 502 indicates that the 5 CPU access is being executed, provided that the triset circuit 508 is not in the set state, that is, the access operation of the SCPU 20 is not being executed. sets the MCPU access execution set reset circuit 506 to the MCPU access execution state (via an AND gate 524 where a low input is coupled to an inverted input from 508 to an inverting input via input 522); By the signal that sets the set reset circuit 506, the OR game) 51
2 (low input is coupled to reset signal MRES) to reset the MCPU access request set reset circuit 502. Similarly, the set state output “H” of the 5CPU access request set reset circuit 504 is
Access Execution Set Reset, provided that the access circuit 506 is not in the set state, i.e., that no access operation of the MCPUIO is in progress (one of the low inputs is connected to the inverting input from the input circuit 506 via the input circuit 520). 5CPU through AND gate 526)
The access execution set reset circuit 508 is set to the 5 CPU access execution state, and by the signal that sets the 5 CPU access execution set reset circuit 508, the OR
516 (low input is coupled to reset signal 5RES) by a configuration of 0 or more that resets the 5CPU access request set reset circuit 504 through the
Even if there is an access request from a PU (for example, 5 CPU 20), if an access operation related to the other CPU (MCPU 1 O) is being executed, the access requesting CPU (SCPU 20) will wait until the execution is completed.
No access operations are performed, which essentially avoids access conflicts.

Furthermore, MCPUIO,! -3 CPUs 20 may request completely simultaneous access. In response to this access conflict, in the embodiment, priority is given to the access request from MCPUIO, and after the access operation of MCPUIO is executed, the access operation of 5 CPUs 20 is executed. For this purpose, the MCPU access request
/) When the reset signal 502 is in the set state, the output signal "H" inhibits the AND gate () 526 via the inverter 525, and the set reset circuit 502
When is being set, 5CPU access request set reset
The 5-CPU access execution set reset circuit 508 is prevented from being set even if the 2-to-1 circuit 504 is set.

The external memory data access control signal generation circuit 510 includes:
is coupled to the outputs from set-reset circuits 506 and 508 such that the output of either set-reset circuit is in the set state "
When it changes to "H", the CPU access operation indicated by the set state is executed in a series of sequences.The signals CE and OE output from the external memory data access control signal generation circuit 510 are used to output data from the external memory 7. The signal MDL is a control signal for latching data from the external memory 90 into the MCPU external memory data latch 80M, and the signal SDL is a control signal for latching data from the external memory 90 into the 5 CPU external memory data latch 805.
This is a control signal for latching data starting from 0. The external memory data access control signal generation circuit 510 generates an END signal when the execution of the access operation is completed. This END signal causes the access execution set reset circuit that was in the set state to be reset. That is, the END signal is connected to an AND gate 528 whose low input is coupled to the output of the set-reset circuit 506 and whose low input is coupled to the output of the MCPU.
It is coupled to the reset input of the set-reset circuit 506 via an OR gate 514 that is coupled to the reset signal MRES, and an AND gate 530 whose low input is coupled to the output of the set-reset circuit 50B and whose low input is coupled to the 5CPU reset signal 5RES. It is coupled to the reset input of set-reset circuit 508 via OR gate 518 .

5 The output of the CPU access execution set reset and reset circuit 508 is sent to the address switching circuit 4 via the inverter 532.
An address selection signal MSEL for 0 is generated. Therefore, the address switching circuit 40 receives the 5CP from the 5CPU external memory access address latch 305 while the 5CPU 20 access operation is being executed.
The U address is selected, and in other cases, the MCPU address from the MCPU external memory access address latch 30M is selected.

In the case of Figure 27, MCPUIO and 5CPU20 are "MC
PU operation
The PU operation requests access to the external memory 90 at the same time as shown in "roma".
In the operation of the oma instruction, the MCPUIO
sends address information to the address bus MA and outputs the signal M
Addresser for MCPU external memory access by outputting CPU roma.

The address information is latched on the chip 30M, and the 5CPU
20 sends the address information to the address bus SA, outputs the signal SCPU-roma, and causes the 5 cPU external memory access address switch 305 to latch the address information 6.
Memory device contention avoidance circuit 50 by U-roma@ issue
MCPU access request set reset circuits 502 and 5
The CPU access request set reset circuit 504 is set at the same time. On the other hand, according to the MCPU access priority logic described above, the MCPU access execution set reset circuit 50B immediately changes to the set state, thereby causing the external memory data access control signal generation circuit 510 to perform the MCPUIO access operation to the external memory 90. Execute. At this point, address switching circuit 4
0 selects address information from MCPUIO.

Set the period of MCPUIO access operation to 142
(Note that the circuit 510 operates with two-phase master claws, CKI, and CK2, but the second
(not shown in FIG. 6), the external memory data access control signal generation circuit 510 makes the chip enable signal CE low active during period n, and makes the output enable signal OE low active during period m in the latter half of period n. Therefore, during this period m, the MC is stored from the external memory 90.
The data requested by PUIO is output, and the signal MDL generated from the external memory data access request signal generation circuit 510 within this period m causes this output data to be sent to the MCPU.
It is latched into external memory data latch 80M. As a result, external memory data access request signal generation circuit 51
Since the access operation for MCPUIO 0 is complete, circuit 510 outputs an end signal END. As a result, the MCPU access execution set reset circuit 506 is reset, and the 5 CPU access execution set reset circuit 508 is set instead. As a result, the signal MSEL changes to "L" level indicating selection of the 5 CPU address, and the address switching circuit 40 selects the address from the 5 CPU 20 to address the external memory 90. Further, in response to the 7-21 signal from the 5 CPU access execution set reset circuit 508, the external memory data access control signal generation circuit 510 executes an access operation for the 5 CPU 20. This period is shown in the period view on the right side of FIG. 27. During this operation, the external memory data access control signal generation circuit 510
makes the signal CE゛ low active, and during the latter half of the period p
The signal OE is activated low to cause the data requested by the 5CPU 20 to be output from the external memory 90, and during the output, the signal SDL is generated to cause the SCPU external memory data latch 805 to latch the data requested by the 5CPU 20. As a result, the access operation for the 5 CPUs 20 of the external memory data access control signal generation circuit 510 is completed, so the circuit 510 outputs the end signal END.
Outputs 5CPU access execution set reset circuit 5
08 to the reset state.

After this, MCPUIO and 5CPU 20 can obtain the requested data by reading the output data of external memory data latches 80M and 805 on data buses MD and SD, respectively.

In this way, each CPU10.20 executes the roma instruction (
After executing an external memory access request instruction).

The requested data can be obtained by waiting a predetermined period during which the memory device contention avoidance circuit 50 executes access operations for both CPUs.

The problem of access contention is resolved. Furthermore, since the waiting time is constant (2 statements), each CPU 10120 can use this period to execute other instructions, optimizing the execution efficiency of program instructions.

In addition, MCPU-roma@ and SCPU-roma@
Cases in which the timing relationship of the number is another timing relationship are omitted from illustration, but in any case, after each CPU10120 executes the roma instruction, if it waits for two sentences for a predetermined period, each CPU's timing relationship has already been established. Since the requested data is latched in the external data latch, the data can be obtained.

address/data conversion hardware (28th to 32nd
In general, in a microcomputer system including a CPU, converting the original data (desired information extracted from the original data) from the original data in the data memory to the calculation memory is a process. often desired. Particularly for this type of data, conversion is necessary to compensate for efficient use of the storage capacity of the data memory. For this purpose, conventionally, a transfer instruction from the data memory to the calculation memory is executed to move the original data in the data memory to the calculation memory, and then one or more conversion instructions are executed to transfer the original data from the data memory to the calculation memory. Converts the data in the ALU via the ALU. Therefore, in the conventional case, the data conversion procedure to obtain the desired data on the calculation memory takes time;
This is one of the obstacles in applications that require high-speed processing.

In this embodiment, the CPU 10120 is connected from the external memory 90, which is a data memory, to the internal RAM 106, which is a calculation memory.
Alternatively, simply by executing an instruction (roma instruction) to transfer data to the internal RAM 106 or 206, the desired converted data is read into the internal RAM 106 or 206, thereby speeding up the data conversion process. To achieve this purpose, an address conversion circuit 60 is provided on the address path between the CPU 10120 and the external memory 90, and a data conversion circuit 70 is provided on the data path between the external memory 90 and the CPU 10120. Each conversion circuit 60.
70 executes a desired conversion in response to a control signal given from CPU 10120 when executing the roma instruction.

FIG. 28 shows a list of external memory access instructions roma. The first instruction romao is a transfer instruction without conversion, whereas the address translation circuit 60
The input address given from the external data memory 90 is directly passed to the external data memory 90 as an output address, and the data conversion circuit 70 also passes the data (16-bit data) from the external data memory 90 to the CPU 10120 without conversion.

In this non-conversion transfer instruction romaO, the conversion control signal R given from the CPU10120 to the conversion circuit 60.70
1, R2, and R3 are all at L'' level.

The second instruction romal is an instruction suitable for reading a special waveform. In response to this instruction, the address conversion circuit 60
The 13th input address sent from PUl0120
(Pitsu) When A12 is "0", the lower 12 bits are passed through without conversion, but when the 13th bit A12 is 1'', the lower 12 bits are passed through without conversion.
Invert the bits. Note that the 13th bit of the output address of the address conversion circuit 60 is fixed to "0" regardless of the value of the 13th bit A12 of the input address.

In addition, in response to this instruction, the data conversion circuit 70
The 13th bit A12 of the input address sent from 0120 is set as the 13th bit D12 of the data sent to CPU10120, and when A12 is "L", the lower 12
The data from the external memory 90 is converted in a format that inverts the bit data. Therefore, the special waveform data (ooo) having 12 valid data beats (2 beats) as shown in FIG.

~0FFF), when the CPU10120 repeatedly executes this instruction for the specified address range 0000-IFFF, the external memory address output from the address conversion circuit 60 will once change from 0000 to 0.
The process proceeds to FF-F, during which time the data conversion circuit 70 passes the data from the external memory 90 as it is, and then, due to the inversion operation of the address conversion circuit 60, the address to the external memory 9o is reversed from 0FFF to oooo, during this time, The data conversion circuit 70 inverts the lower 12 bits of the data output from the external memory 9o,
12 is changed to "!" and the converted data is output. In the end, CPU10120 changed the address from 0000 to LF F
Move to F and command r.

When mal is repeatedly executed, the waveform actually received by the CPU 10120 is the waveform shown on the right side of the column romal in FIG. This converted waveform is a repetitive waveform (a waveform that is symmetrical about the address, 0FFF, and data 0FFF points) that is obtained by extending the original waveform in the external memory 90 shown on the left in a predetermined manner. In other words, compared to a method in which the converted waveform data itself is stored in advance in the external data memory 90, there is an advantage that the waveform data storage capacity is halved. This command r omal
In this case, only R1 among the control signals R1, R2, and R3 is “
It becomes H'' level.

The third instruction ROMA2 is an instruction to read a part (half word) of external memory data. For this command,
Only R2 becomes "H" level.

The storage capacity of one address (one word) of external data memory 90 is 16 bits. For this command roma2,
When the 16th bit A15 of the address from the CPU 10120 is 0, the data conversion circuit 70 leaves the lower 8 bits of the 16-bit data from the external data memory 90 and sets the upper 8 bits to 0. When A15 is l'', the upper 8 bits of the 16-bit data from the external data memory 90 are converted to the lower 8 bits.
Shift to bits (remaining upper 8 bits are masked) conversion is executed. In addition, since the data conversion circuit 70 uses the 16th bit (A15) of the input address as a control signal, the address conversion circuit 60 masks the 16th bit of the output address to a predetermined value 〒0'' regardless of the value of A15. In this case, the relationship between the upper 8 bits and lower bits of the 16-bit information in the external data memory 90 or 6 is that the upper data part (for example, integer S) and the lower data part in one data (for example, phase data) part(
For example, it may be a relationship such as a decimal part), or it may be an independent relationship such as two different types of 8-bit data (for example, rate data and level data).

The fourth instruction ROMA3 is an instruction to shift external memory data and read a part of it. In the case of this instruction, only R3 becomes "H" level. In response to this command, the data conversion circuit 70 converts the 16-bit data from the external memory 90 into
Leave bit 15 as is and use bit 1 of the upper 12 bits.
5 to bit 4 are shifted to bit 14 to bit 3, and the lower 3 bits bit 2 to bit O are masked to 0. Here, the upper 12 bits of the 16 bit data in the external memory 90 are, for example, b f t 15. is the waveform data with the sign bit as the sign bit, and the lower 4 bits represent other data. In this case, ζ
120 can read waveform data in a format suitable for use on the internal RAM 106 and 206 at high speed.

FIG. 29 shows a block diagram of the address translation circuit 60.
Of the 16-bit address input from the CPU 20 via the 7 address latches 30M and 30S and the address switching circuit 40, the lower 12 bits (bit O to bi
tll) is input to an inverting circuit 610 whose details are shown in FIG. This inverting circuit 610 inputs the signal R1 as the command roma.
A12 of Aγless is "l" which represents -1",!,
'', it is operated by a negative signal from the AND gate 612 to invert the lower 12 bits of the input address.

Further, the signal R1 which becomes "L" when the instruction ROM'AL is executed is passed through the AND gate 60 through the inverter 602.
4 is prohibited, and the corresponding bit (bit-12) of the output address is set to '0' regardless of the value of A12 of the input address. -AI-3 and A14 of the input address are output as is. '10-less corresponding bit (b, lit13.
bit14). Input address A15
(MSB) is the corresponding bit of the output address via the AND gate 608 (bit 15), when the signal R2 of "1" indicating that the instruction roma2 is being executed is generated.
This signal R2 inhibits the AND gate 608 via the inverter 606 and outputs bit 15 (MSB) of the address.
is masked to “0”.

Therefore, the address conversion circuit 60 uses the S conversion instruction r o
For m a O and shift read command roma3, R1="0", R2; 0", so the input address is passed as is as an output address, and the special waveform read command ro
Since R1="1" for mal, the output address b
It12 is masked to "0", and the lower 12 bits of the input address) (bi
t.

~bitll) is inverted and used as the output address.

Furthermore, for the partial read instruction roma2, R2-“
l'', so bit 15 of the output address is masked to θ'''. In this way, the function of the address conversion circuit described with reference to FIG. 28 is realized.

FIG. 31 shows a block diagram of the data conversion circuit 70, and FIG. 32 shows its details. In these figures, data input is data supplied from the external memory 90 of FIG. In FIG. 32, a 3-state gate circuit 702 coupled to the upper 8 bits of the input data and a 3-state gate circuit 702 coupled to the lower 8 bits of the input data
The 3-state gate circuit 704 coupled to the bit outputs the L-order 8 bits of the input data as the lower 8 bits of the output data.
This is to determine whether to select the lower 8 bits of input data. R2=″1″(roma
2 instructions), when A15=1, the AND gate 706 “
1" output signal and its inverted signal, the output signal "0" of the inverter 708, makes the gate circuit 702 conductive, turns off the gate circuit 704, and selects the upper 8 bits of the input data as the lower 8 bits of the output data. In other cases, the gate circuit 702 is turned off and the gate circuit 704 is conductive, so that the lower 8 bits of the input data are output as they are as the lower 8 bits of the output data.Furthermore, R2="
1" (roma2 instruction), the AND gate circuit 710 that connects to the upper 8 bits of input data is inhibited and the upper 8 bits of output data are masked to "0".

That is, when R2="1", inverter 712 and NOR
The inhibit signal is passed through the gate 714 to the AND gate circuit 71
In addition to this, the upper 8 bits of the input data in the AND gate circuit 710 are prevented from passing through. Furthermore, the AND gate element connected to the upper 3 bits of the input data in the AND gate circuit 710 is inhibited via the NOR gate 714 when R1="1" (romal instruction), and the upper 3 bits of the output data are to mask.

EX-OR gate circuit 716 is a circuit for selectively inverting the lower 12 bits of input data. EX-OR
When R1=“l” (romal instruction) and A12=1, the gate circuit 716 inverts the lower 12 bits of data according to the inversion signal “1” from the AND gate 718, and otherwise leaves the lower 12 bits of data unchanged. Pass 0 circuit 7
bits of input data through AND gate elements within 10
State gate 722 coupled to R1=“1”(ro
mal instruction), is turned off by signal "0" provided through inverter 720 coupled to signal R1, and instead tri-state gate 724 coupled to A12 switches off signal R1.
It becomes conductive and generates bit 12 of the output data.

The shift mask circuit 726 selectively converts bits 15 to 4 of the input data to bits 14 to b of the output data.
This is a circuit for shifting to it3 and masking bit2 to bi10 of the output data to "0", and R3="1"
This conversion is performed by a signal "1" from inverter 728 coupled to signal R3 when (roma3 instruction).

Therefore, the data conversion circuit 70 converts the non-conversion instruction ROM
When ao (R1=R2=R3="0"), the input 16-bit data is passed through as is, and when the special waveform read command is romal (R1="1"), the -L-order 4 bits of the input address are passed through. (bit15-bft12) is o
ooo” (when A1220) or “0001” (AI
When 2 = 1), the lower 12 bits of the output data are used as they are, depending on which lower 12 bits of the input data.
When A12 = 0), or convert the lower 12 bits of the output data into data in which the lower 12 bits of the input data are inverted (AI2 = 1), and issue a partial read command roma2 (R2 -“1”), the upper 8 bits of the output data are all zeros, and the lower 8 bits of the output data are the lower 8 bits of the input data (A
15 = 0), or perform data conversion so that the upper 8 bits of the output data are all zeros and the lower 8 bits of the output data become the upper 8 bits of the input data (when A15 = 1), and shift Read command roma3 (R3
= 1) + 7), the lower 3 bits of the output data
O-bit2) is all zero, and bit3 of the output data
~bj t 14 is input data bit t4 ~ bjt1
In step 5, data conversion is performed so that bit 15 (MSB) of the output data becomes bit 15 (MSB) of the input data.In this way, the data conversion I described in FIG.
e! functionality has been achieved.

As described above, the address conversion circuit 60 and the data conversion circuit 7
The advantage of providing 0 is obvious. That is, C
For PU10.20, simply executing the access instruction rozna to the external memory 90, which is data memory, changes the circuits 60 and 70! i! 5. Data with the desired transformation can be obtained immediately by Ill& function.
Unlike conventional methods, there is no need to once import the data in the external memory 90 into the internal RAM 106.206, which is the calculation memory, and then execute conversion via an ALU such as the ALU unit 108.208, resulting in faster processing. There is an advantage that

Note that the list of access commands r o m a shown in FIG. 28 is merely an example, and can be easily expanded and changed.

<DAC Sampling (FIGS. 33 and 34)> In this embodiment, the DAC 100 converts the digital musical tone signal generated by the MCPUIO and the 5 CPU 20 into an analog musical tone signal. As shown in 5-5 in Figure 5, the MCPU
IO is performed by MC in the timer interrupt processing routine.
A sample of the digital musical tone signal generated by the PUIO and the 5CPU 20 is set in the DAC 100. This process 5-5
The average execution interval of timer interrupt generator 1 is
16, but the actual execution interval varies due to program operations. Therefore, if D/A conversion is performed using the execution interval of process 5-5 as the conversion period of D/A conversion, a large distortion will occur in the analog musical tone signal.

FIG. 33 shows an example of the configuration of the right DAC 100R or the left DAC 100L. In the configuration shown in FIG. 33(A), when processing 5-5 is executed, the internal The waveform addition register in the RAM 106 is added, and the latest digital musical tone data stored therein is taken out and placed on the data bus.

Then, at the timing when the digital musical tone data is on the data bus, a strobe program control signal is input to the clock input of the latch 1004 to the operation control circuit 1.
12 and the data on the data bus is set,
New digital musical tone data from latch 1004 is D/A
It is input to converter 1002. Therefore, the 34th S (
As shown in A), the digital musical tone data input to the D/A converter 1002 is switched at an unstable cycle due to program control. Unless the conversion period (sampling period) of the D/A converter 1002 is very stable, large distortions will occur in the conversion.

This problem can be solved by adopting a configuration as shown in FIG. 33(B). That is, between the soft control latch 1004 controlled by the program control signal from the operation control circuit 112 and the D/A converter 1002 that converts the digital musical tone signal into an analog musical tone signal,
An interrupt control latch 1006 is provided which is controlled by an interrupt signal INT, which is a precise timing signal from the interrupt generating section 116. The generation period of the interrupt signal follows the stability of the clock oscillator, so it is extremely stable. The output of the driver and driver 1006 is switched in synchronization with the timing of the interrupt signal. That is, the generation cycle of the interrupt signal becomes the conversion (sampling) cycle of the D/A converter 1002. The timing chart for the configuration of FIG. 33(B) is shown in FIG. 34(B), and as shown in FIG. Although it varies depending on time (the length of the shaded part), since there is a latch 1006 that operates with the interrupt signal, the timing at which the input data of the D/A converter 1002 switches is synchronized with the interrupt signal. This solves the distortion problem in the configuration of FIG. 33(A).

Although the embodiments have been described above, various modifications and changes can be made without departing from the scope of the present invention.

[Effects of the Invention] As explained in detail above, in the digital microcomputer of the present invention, the interrupt signal is masked during the writing process of multiple data to be passed from the main program executed in the main program mode to the interrupt processing routine. This ensures that the interrupt routine always receives the correct data and executes the correct processing.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of an electronic musical instrument processing device to which the present invention is applied.
Figure 4 is a flowchart of the main program executed by the MCPU. Figure 5 is a flowchart of the interrupt processing routine executed by the MCPU. Figure 6 is a flowchart of the program executed by the 5CPU. Figure 7 is the sound source. Processing flowchart, FIG. 8 is approach 1 of the operation of the embodiment over time;
- Figure 9 is a flowchart of channel sound source processing, Figure 10 is a diagram showing waveform data, Figure 11 is a diagram showing a RAM table for sound source processing, and Figure 12 is a diagram of the circuit related to the 5CPtJ operation start and end function. Block diagram: Figures 13, 14, and 15 are time charts of the operation of the circuit in Figure 12. Figure 16 is a block diagram of a circuit with an interrupt mask function. Figure 17 is envelope setting using the interrupt mask method. Processing flowchart Figure 18 is a block diagram of a circuit that has the function of prohibiting interruption of the main program due to an interrupt signal while multiple data are transferred using a single instruction. FIG. 20 is a diagram showing an example of a memory map of a RAM suitable for the following. FIG. 20 is a diagram showing a comparison between operations using multiple transfer instructions and operations using a single transfer instruction. FIG. 21 is a flowchart of envelope setting processing using the single transfer instruction method. Figure 22 is a flowchart used to explain the 5CPU access function from the MCPU using the 5CPU stop mode, Figure 23 is a flowchart of the MCPU with the instantaneous forced access function to the 5CPU, and Figure 24 is a flowchart for the 5CPU. A block diagram of the 5 CPUs that is compatible with the instantaneous forced access function. Figure 25 is a time chart of the operation when data is written from the MCPU to the internal RAM of the 5 CPUs. Figure 26 is a block diagram of the memory device contention avoidance circuit shown in Figure 1.
27 is a time chart of the operation of the circuit in FIG. 26, FIG. 28 is a diagram showing a list of external memory access instructions including instructions to convert and import data from external memory, and FIG. 1, FIG. 30 is a circuit diagram of the inversion circuit shown in FIG. 29, FIG. 31 is a block diagram of the data conversion circuit shown in FIG. 1, FIG. 32 is a circuit diagram of the data conversion circuit, Figure 33 is a diagram comparing the configuration in Figure 1 in which the DAC sampling cycle is unstable and the configuration in which the sampling cycle is stabilized. Figure 34 is a time chart when the DAC sampling cycle is unstable. It is a figure which compares and shows the time chart in a stable case. 10...MCPU (CPU)116...
... Interrupt generation section (interrupt generation means) 114 ... ROM address control section (CPU mode control means) 102 ... Control ROM 112 ... Operation control circuit 150.・
...Mask release special unit 102.112.150... (Interrupt mask means)

Claims (1)

[Scope of Claims] A CPU having a main program mode for executing a main program and an interrupt mode for executing an interrupt processing routine; interrupt generating means for generating an interrupt signal; and execution by the CPU in response to the interrupt signal. CPU mode control means for interrupting a main program in the CPU and controlling the mode of the CPU to be switched to the interrupt mode, the digital microcomputer having: a plurality of data stored in the interrupt processing memory in the main program mode of the CPU; means for writing and referring to the plurality of data stored in the interrupt processing memory in the interrupt mode; and writing processing of the plurality of data to the interrupt processing memory is executed by the means in the main program mode. interrupt masking means for inhibiting the operation of the CPU mode control means by masking the interrupt signal during the writing process, and for inhibiting interruption of the write processing.