JPH0460746A - Digital microcomputer - Google Patents

Abstract

PURPOSE:To obtain the digital microcomputer of plural CPU, in which the functions of respective CPU can sufficiently be used, by providing a CPU mode control means which responds to a parallel processing start signal, switch- controls the modes of respective CPU to the execution mode of a prescribed processing and realizes the parallel processing of plural CPU. CONSTITUTION:A memory device contention avoiding circuit 50 controls the access of an external memory 90 by MCPU 10 and SCPU 20 and avoids the contention. An address conversion circuit 60 and a data conversion circuit 70 set CPU 10 and 20 to fetch data obtained by converting data of the external data memory 90. MCPU 10 and SCPU 20 generate a digital musical signal. It is transmitted to a digital-analog converter DAC 100 composed of right DAC 10R and left DAC 100L from MCPU 10, is converted into an analog musical signal and is outputted to an external part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital microcomputer, and particularly to a digital microcomputer having a plurality of CPUs.

BACKGROUND OF THE INVENTION Digital computers with one CPU are known. When there is a large amount of data to be processed or in applications that require high-speed processing, there is a limit to the amount of data that can be processed within a unit time by one CPU, so application systems are often implemented using multiple CPUs. It will be done.

Having multiple CPUs basically aims to improve processing performance. Unfortunately, increasing the number of CPUs to N does not increase the processing power by N times that of a single CPU; in some dual-CPU computers, when one CPU is running, the other has stopped. Although this is an extreme example, the current situation is that in microcomputers with multiple CPUs, sufficient parallel processing cannot be realized due to access problems between the CPUs.

[Object of the Invention] Accordingly, an object of the present invention is to provide a digital microcomputer with multiple CPUs that can fully utilize the functions of each CPU.

[Structure and operation of the invention] According to the present invention, a plurality of CPUs, a parallel processing start signal generating means for generating a parallel processing start signal, and a mode of each CPU is set to each CPU in response to the parallel processing start signal. There is provided a digital microcomputer characterized in that it has a CPU mode control means for realizing parallel processing by the plurality of CPUs by controlling switching to an execution mode of a predetermined process shared by the plurality of CPUs.

According to this configuration, me(7) is signaled by the parallel processing start signal.
) Since each CPU starts its assigned processing at the same time, near-ideal parallelism is achieved, and the performance of the digital microcomputer is greatly improved.

Certain applications require a microcomputer to periodically perform a fixed-time process, such as reading input from an input device, processing data, or providing a desired processing signal or control output to an output device. For example, a microcomputer used in an electronic musical instrument application must generate samples of a musical tone signal at a predetermined period and output the samples to a digital-to-analog converter, which is an output device. In this type of application, the parallel processing start signal is a signal generated at predetermined time intervals from means such as a timer.

One preferred configuration example includes a main CPU that includes a main program and an interrupt processing routine, at least one sub-CPU that includes a program for executing processing assigned by the main program of the main CPU, and a predetermined period of time. interrupt generating means for generating an interrupt signal every time a period of time elapses; and in response to the interrupt signal, the mode of the main CPU is set to a mode in which the main program being executed in the main CPU is interrupted and the interrupt processing routine is executed. main CPU mode control means for controlling switching and returning the mode of the main CPU to a mode in which the main program is executed again in response to completion of execution of the interrupt processing routine; Sub-CPU mode control means controls switching of the mode of the CPU from a stopped state to a mode in which the program is executed, and controls the mode of the sub-CPU to return to the stopped state in response to completion of execution of the program. A digital microcomputer is provided.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

Summary> This embodiment applies this invention to an electronic musical instrument.
This embodiment (W41 to FIG. 34) includes various features. The first feature is that multiple microcomputer processing units I (CPUs) that operate according to a program are used as sound sources that generate musical tone signals, and there is no need for a conventional /\-ware sound source with a dedicated structure. . 1 CPU
serves as the main CPU or master CPU (10), and handles not only sound source processing but also input devices (function keys, etc.) according to the application (in this case, musical instruments) and output devices (DAC, etc.) (Figs. 4 and 5). ), other C
The PU functions as a sub-CPU or slave CPU (20) for the master CPU and executes sound source processing (FIG. 6).Therefore, the burden of sound source processing is shared between each CPU.

The second feature is related to the mechanism by which the sub-CPU starts and ends its operation, and according to this embodiment, the sub-CPU
The operation starts in response to a timer interrupt that requests sound source processing to the master CPU, and as a result, sound source processing is executed in parallel in the master CPU and sub CPU. When the operation (sound source processing) of the sub CPU is completed, the sub CPU is transferred to the reset state (stop state) by the end signal, and the end signal is sent to the master CPU.
This feature allows the master CPU to effectively manage and keep track of the operating period of the sub-CPUs. Furthermore, this feature allows efficient execution of sound source processing tasks (generating digital samples of musical tone signals) that require high-speed processing.

The third feature of this embodiment relates to the problem of updating (transferring) data passed from the main program to the timer interrupt processing routine. As a result of the execution of the interrupt processing routine, it becomes necessary to update a plurality of data to be referenced in the interrupt processing routine (for example, envelope parameters such as an envelope target value and an envelope plate). The execution instructions for updating this plurality of data are included in the main program. That is, this plurality of data is updated by the main program and referenced by the timer interrupt processing routine. Since such multiple pieces of data constitute meaningful information as a whole, control must not be transferred to the interrupt processing routine before all of the multiple pieces of data have been updated in the main program. As a method, a method has been disclosed that masks the interrupt and prohibits transition to the interrupt processing routine until the data update is completed ($1
6 and 17), and as a second method, a method is disclosed in which multiple data updates (transfers) are executed with a single instruction in the main program (FIGS. 118 to 21). As a result, The processing results (samples of musical tone signals) of the interrupt processing routine show correct values, and correct operation is guaranteed.

The feature of W44 of this embodiment relates to the problem of data access from the master CPU to the slave CPU. In conventional multi-CPU microcomputer systems, generally,
Data transfer between CPUs is performed through a series of sequences and takes a considerable amount of time.Typically, a CPU requesting data access sends an access request signal to the CPU to which access is requested. In response to this access request signal, the CPU to which access is requested sends an acknowledge signal to the CP after completing the operation being executed.
Pass it to U and enter the stopped state. After sending the access request signal,
The requesting CPU remains in a wait state until the acknowledgment signal is received. Upon receiving the approval signal, the requesting CPU performs actual data access to the internal memory of the requested CPU. As described above, the conventional inter-CPU data access method takes time and is not suitable for applications such as electronic musical instruments where high-speed processing is desired.In order to solve this problem, in this embodiment, li! As data access method 1, the master CPU reads/writes (accesses) data to the internal memory (206) of the sub CPU when the sub CPU is in a stopped state by using the above second feature.
A stop mode control method is disclosed (Fig. 22), and the second
Master C as a data access method without waiting state
An instantaneous data access method in which a PU accesses data from a sub-CPU (the sub-CPU is forcibly stopped only during data access) is disclosed (Figs. 23 to 25).
figure).

The fifth feature of this embodiment is that the CPU external memory as a data source is shared by multiple CPUs.
According to this embodiment, by providing a memory device conflict avoidance circuit (50) to be described later, conflicts in access to the shared memory are resolved, and after a certain waiting time, the shared memory is Allows data to be retrieved from memory.

The sixth feature of this embodiment relates to speeding up data conversion processing (shifting, inversion, partial extraction, etc.).

Conventionally, in order to obtain data converted from data in a data memory such as the above-mentioned CPU external memory onto the CPU internal memory (m-arithmetic memory), a transfer (read access) command is used to access the data memory. The data is transferred to the calculation memory, and then the data in the calculation memory is converted via the ALU by a conversion instruction. It is also often necessary to execute multiple conversion instructions to effect the desired data conversion. As described above, there has been a problem in the past that data conversion processing takes time, which is a particularly serious problem in applications that require high-speed processing, such as sound source processing. To solve this, according to this embodiment, data address translation hardware (60
, 70) and executes a special transfer instruction (transfer with conversion instruction), the data that has been subjected to the desired data conversion via the data/address conversion hardware that responds to the instruction is transferred to the calculation memory ( 106, 206). Therefore, in order to obtain desired conversion data, it is sufficient to execute a single instruction instead of a plurality of instructions, and the processing speed can be increased.

Overall Configuration (Figure 1) Figure 1 is a block diagram showing the overall configuration of this embodiment configured as a processing device for an electronic musical instrument.
(denoted as U20).

Each CPUl0120 has a built-in program, and the MCPUl0, which operates according to the respective program, controls the entire system in addition to sound source processing (Fig. 5).For example, input devices (such as keyboards, processing input information from function keys, etc.);
DAC that converts digital musical tone signals to analog musical tone signals
100 control etc. (Figure 4), whereas 5CP
U20 is dedicated to sound source processing (FIG. 6).

A memory 90 serves as a data source for sound source control data, waveform data, and the like. The data memory 90 is an LSI
It consists of a ROM externally attached to a chip (which carries the remaining devices in Figure 1). If the degree of integration is high, data memory 90 can be formed as an internal memory on a single LSI chip. External memory 90 is MCPUI
It is shared by O and 5 CPU20. Address information from MCPUIO is transferred to address bus MA that couples to MCPUIO.
, the MCPU external memory address latch 30M of the external memory address switch 3o, the address switching circuit 40, and the address conversion circuit 60, and are added to the address input of the external data memory 90. On the other hand, the address information from the 5 CPU 20 is transferred to the address bus SA connected to the 5 CPU 20.
, 5CPU external memory address switch 303, address switching circuit 40. It is applied to the address input of external data memory 90 through address conversion circuit 60. The data transmission path from the external data memory 90 to the MCPU 10 is constituted by the data output of the external data memory 90, the data conversion circuit 70, the MCPU external memory data latch 80M of the external memory data latch 80, and the data bus MD coupled to the MCPUIO. . On the other hand, the data transmission path from the external data memory 90 to the 5 CPU 20 includes data output from the external data memory 90, data change! lI circuit 7
0.5 CPU external memory data latch 8°S, 5 CPU
20 and a data bus SD coupled to the data bus SD.

The memory device contention avoidance circuit 50 includes MCPUIO and 5 CPUs.
This system controls access to the external memory 90 by both CPUs 20 and avoids conflicts. The memory device conflict avoidance circuit 50 controls the address switching circuit 40 in response to the signal roma requesting external memory access from MCPUIO and the signal roma requesting external memory access from the 5 CPUs.
selects either the address from MCPUIO or the address from 5CPU 20 as the address to external memory 90. For this purpose, the address switching circuit 40 receives the selection signal MSEL from the memory device conflict avoidance circuit 50.
performs a selection operation. When the address to the external memory 90 is determined, the memory device conflict avoidance circuit 50 activates the chip selection signal GE and the W key enable signal OE for the external memory 90. This causes data to be output from external memory 90 and appear on the input bus of external memory latch 80 through data conversion circuit 70 . Here, the memory device contention avoidance circuit 5° operates either the MCPU external memory data latch 2 80M or the 5 CPU external memory data latch 80S to latch the data in order to send the data to the CPU that has requested data access. . For this purpose, the MCPU external memory data latch 80M operates 2,000 times by the latch signal MDL from the memory device contention avoidance circuit 50, and the 5CPU external memory data latch 80M
S is a latch signal SD from the memory device contention avoidance circuit 50
L is used for latch operation.

The address conversion circuit 60 and the data conversion circuit 70 convert the data of the external data memory 90 and convert the data to the CPU101.
This is a conversion device for importing into 20. The address conversion circuit 60 is the address switching circuit 40.
It selectively changes the address passed through the CPU (MCPUI O or 5 CPU 20) (logical address) to form the address that is actually input to the external data memory 90, and performs data conversion. The circuit 70 selectively changes the data output from the external data memory 90 and outputs it to the CPU (MCPUIO or 5CPU20).
) forms the data that is actually input. Each conversion port i! Control signals are used to specify aspects of the conversion in g60.70. In each CPU10120, data access to the external data memory 90 is performed by executing a transfer command. The control signals generated by the CPU based on the transfer command are transmitted to MHI, MR2, and M
R3 (for MCPUI O), SR1, SR2, SR
3 (in case of SCPU 20). After these signals pass through the external memory address switch 30 and the address switching circuit 40, they are called signals R1, R2, and R3 (
MRi −” LMRi→Ri or SRi→LSRi
+Ri), to specify the conversion mode, control No. 18 R1
, R2 are input to the address conversion circuit 60. Furthermore, in order to specify the conversion mode in the data conversion circuit 70,
Control signals R1, R2, R3, address bit 12 signal A12 from address conversion circuit 60, and address bit 1
5 signal A15 is applied to the data conversion circuit 70. Details of the address conversion circuit 60 and data conversion circuit 70 will be described later.

In order to define the interface between MCPUIO and 5 CPUs 20, a plurality of signals are transmitted between both CPUs. @
No. A is 5CP sent from MCPUIO to 5CPU20
A signal indicating the start of processing of U20, signal B is 5CPU20
A signal indicating the end of processing of 5 CPU 20 is sent from MCPUIO to MCPUIO, Ma is address information of the internal memory of 5 CPU 20 (206 in FIG. 3) sent from MCPUIO to 5 CPU 20, and signal C is sent from MCPUIO to 5 CPU 20.
The read/write control signal of the internal memory of the 5 CPU 20 sent to
υ is 5CP sent from MCPUIO to 5CPU20
CP, which represents the data written to the internal memory of U20.
Details of the U-U interface will be described later.

As mentioned above, MCPUIO and 5 CPU
20, a digital musical tone signal is generated. The generated result is M
From CPUIO, right DACl 00R and left DAC100
Digital-to-analog converter (DAC) Zoo consisting of
The signal is then converted to an analog musical tone signal and output externally.

<MCPU,! :5CPU configuration (Figures 2 and 3)> Figure 2 shows the internal structure of the MCPU 10, and Figure 3 shows the 5C
The internal structure of PU20 is shown.

In FIG. 2, the control ROM 102 stores a main program for processing various control inputs of the musical instrument and an interrupt processing program for generating musical tones. Program words (commands) in
In the specific embodiment, the program word length is 28 bits, and part of the program word should be read out next. ROM address control unit 11 as the lower part (in-page address)
The next address method is entered in 4, but
A program counter method may be used instead, RA
When the operand of the instruction from the control ROM 102 specifies a register, the M address control unit 114 controls the RA
Specifies the address of the corresponding register in M106.

The RAM 106 is a group of registers constituting a calculation memory, and is used for general-purpose calculations, flag calculations, musical tone calculations, and the like. The ALU section (addition/subtractor and logic operation section) 108 and multiplier 110 are used when the instruction from the control ROMIO 2 is an operation instruction.

In particular, the multiplier 110 is used to calculate musical waveforms, and as an optimization for this purpose, it multiplies the first and second data inputs (for example, 16-bit data) to obtain data of the same length (16 bits) as the input. It is designed to be output. Above RA
M106, adder/subtractor 108, and multiplier 110 constitute an arithmetic circuit. The operator control circuit 112 decodes the operation code of the command from the control ROM 102 and sends control signals (indicated by CNTR) to each part of the circuit in order to execute the instructed operation. In addition, when executing a conditional branch instruction, the operation control circuit 112
detects the establishment of a branch condition based on the status signal S (for example, an overflow signal, a zero flag signal, etc.) from the ALU unit 10g, and jumps the address to the branch destination address via the ROM address control unit 114.

In order to execute the musical tone generation program in the control ROM 102 at predetermined intervals, this embodiment employs a timer interrupt. That is, the interrupt generation section 116 having a timer (hardware counter) sends a control signal IN to the ROM address control section 114 at regular intervals.
T (interrupt request signal) is sent, and in response to this signal, the ROM address control unit 114 saves (holds) the address of the next main program instruction, and returns the address to the beginning of the interrupt processing program (subroutine) in which musical tones are generated. Set the address instead. This starts the interrupt processing program. Since there is a return instruction at the end of the interrupt processing program, when this return instruction is decoded by the operation control circuit 112, the ROM address control section 114 sets the saved address again and returns to the main program. . Furthermore, the control signal INT from the interrupt generating section 116 is D.
It is supplied to the DAC 100 in order to determine the digital/analog conversion sampling rate of the musical tone signal in the AC 100. Note that the interrupt generation unit 116 is M in the diagram.
Although it is depicted as an internal element of CPUIO, MCPUl
It is a request to o to stop the work it is currently doing and to perform special processing, and is logically an external element (peripheral W) of the MCPU 10.

The clock generation circuit 136 is a master clock generation circuit (
2-phase master clocks CKI and CK from (not shown)
2, various timing signals (TI T2
, T3. TICK1, T2CK2, T3CK3, etc.).

The remaining elements in FIG. 2 relate to the MCPU 20's interface with external devices. 122 represents a gate as a bus interface for connecting the MCPU internal bus to the external memory access address bus MA (FIG. 1), and 124 represents a gate for connecting the MCPU internal path to the external memory data bus MD. , 126 is a DAC
Represents a gate for connecting the MCPU internal bus to the data transfer bus, and also input port 118 and output port) 1
20 is an interface for coupling the MCPU internal bus to an external input device. 128 is 5 CPU internal RA
A gate for connecting the MCPU internal bus to the M address specification bus, 130 a gate for connecting the MCPU internal bus to the 5 CPU internal RAM write data bus, and 132 a gate for connecting the 5 CPU internal RAM read data bus to the MCPU internal path. Represents a gate for.

The 5CPU reset control unit 134 is a device for managing the operating period of the 5CPU 20. According to this embodiment, the 5CPU reset control unit 134 responds to the interrupt signal INT from the interrupt generation unit 116, and
A signal A indicating the start of processing by the PU 20 is generated. This signal A is the ROM address control unit 214 (third
ROM address control unit 214.
The address update operation starts, and the operation of the 5 CPU 20 (including sound source processing) starts. When the operation of the 5CPU 20 is completed, a signal B indicating the end of processing is generated from the operation control circuit 212 of the 5CPU 20, and this signal B is transmitted to the 5CP
It is sent to the U reset control unit 134. On the other hand, 5C
The PU reset control unit 134 inverts the signal A to stop the operation of the 5 CPU 20.
5C, which stops the operation of the ROM address control unit 214 and indicates that the 5CPU 20 is stopped.
A PU status flag signal is sent to the operation control circuit 112. The operation control circuit 112 is a control ROM1
When executing the 5 CPU status inspection command from 02, this 5
By reading the CPU status flag signal, 5CPU20
can detect the state of

In the block diagram of the 5 CPU 20 in FIG.
．． 202a, 204.205.206.208.212
．． 214.222.224.236 are respectively elements 102.1 in the block diagram of MCPU 10 in FIG.
02a, 104105.106, tOS, 110.11
This is an element corresponding to 2.114.122.124.136. However, the control ROM 202 of the 5 CPU 20 basically stores only a program for sound source processing, and allows the 5 CPU 20 to function as a processing device exclusively for sound source processing.

240 is RAM2 as a memory for calculation of 5CPU20
The data input to 06 is the data from MCPUIO (M
From CPUIO to gate 130, data bus D OUT
This is a RAM data-in switching unit that selects from data generated (computed) by the 5CPU 20 (data on the data bus DB from the ALU unit 208 or the multiplier 210). RAM data-in inspection section 240
Its selection mode is controlled by signal A, and when signal A indicates "5CPU20 in operation", 5C is selected.
Select the data calculated by PU20, and signal A is “5CP”.
When "U20 is stopped" is displayed, data from MCPUIO is selected.

The RAM address control unit 205 also has its mode controlled by the signal A, and when the signal A indicates "5 CPU 20 in operation", the RAM address control unit 205 inputs the information on the bus SA from the instruction output latch 202a of the control ROM.
Selected as the address of AM206, and the signal A is “5CP”.
MCPU 10 when U20 is stopped and indicates 7
The information from MCPUIO on bus Ma is transferred to RAM2 via bus gate t28 (opened by @A).
06 address. Similarly, the mode of the write signal switching section 242 is controlled by the signal A,
When the signal A indicates "5CPU20 in operation", the RAM read/write signal from the operation control circuit 212 of the 5CPU20 is selected and coupled to the read/write input R/W of the RAM 206, and the signal A indicates "5CPU20 in operation".
When "stopped" is displayed, the SCPURAM read/write signal from the operation control circuit 112 of the MCPU 10 is selected instead of the 5CPU 20, and the RAM 20 is
It is connected to the read/write manual R/W of 6.

Below, various features of this embodiment will be explained in more detail.

Multiple CPU sound source function (Figures 1 to 7, Figures 9 to 11)> Figure 4 is a flowchart showing the operation of MCPUIO by the MCPUIO main program (background program), and Figure 5 is the timer interrupt signal INT. A flowchart showing the operation of MCPUlo by the interrupt processing routine of MCPUlo started by
FIG. 6 is a flowchart showing the operation of the 5CPU 20 by the program of the 5CPU 20 activated by the timer interrupt signal INT, and FIG. 7 shows the MCPUIO and 5C
It is a flowchart of the sound source processing which each PU20 performs.

As described with reference to FIGS. 1 to 3, the electronic musical instrument processing system of this embodiment is equipped with a plurality of CPUs consisting of an MCPUIO and 5 CPUs 20, and the 5 CPUs work together to execute processing for the electronic musical instrument. do. In particular, the MCPUIO processes the sound source using an interrupt processing routine as shown in Figure 5, the 5CPU 20 processes the sound source using a program as shown in Figure 6, and the MCPUIO processes the entire system using the main program shown in Figure 4. Perform various tasks for control.

In the flow of the main program shown in FIG.

4-1 is a process to initialize the system when the power is turned on, and the MCPUIO clears the RAM 106 and RAM 206, sets initial values such as rhythm tempo, etc. In 4-2, the MCPUIO performs key scanning from the output board 120. Outputs the signal for W@.

By taking in the status of an input device such as a function switch from the input port 118, the status of the function key and the main key of the Li board is stored in the key buffer area of the RAM 106. 4-3
Now, from the new state of the function key obtained in 4-2 and the previous state, identify the function key whose state has changed and execute the instructed function (for example, set musical tone number, set envelope number, Rhythm number set, etc.), 4-4 uses the latest keyboard state obtained in 4-2 and the previous state,
Identify the changed key (key press, key release) 4 in 0th order 4-5
Key assignment processing for 1 sound processing 4-9 is performed from the processing result of -4. In 4-6, when the demo performance key is pressed with the function key, the demo performance data (
By sequentially reading and processing the sequencer data), key assignment processing and the like for the sound generation processing 4-9 are performed.

In step 4-7, when the rhythm start key is pressed, rhythm data is sequentially read out from the external memory 90, and sound generation processing 4 is performed.
Flow-period timer processing 4-8 performs key assignment processing for Flow-period timer processing 4-8, which performs key assignment processing for Flow-period timer processing 4-8. This is obtained by counting the number of timer interrupts (this counting process is performed in interrupt timer processing 5-2, which will be described later). 0 sound processing to obtain the reference value In 4-9, 4-
5. From the data set in 4-6.4-7, perform various calculations to actually produce musical tones, and store the results in RAM.
106, set in the sound source processing register (811) in the RAM 206. 4-10 is a preparation process for the next main flow pass, in which the NEW ON state indicating a change to the key pressed state obtained in the current pass is set to ON, or the NEW indicating a change to the key released state is set to ON. Processing such as changing the OFF state to OFF is performed.

Interrupt signal INT from interrupt generation section 116
When this occurs, the MCPUIO interrupts the main program being executed and executes the interrupt processing routine shown in FIG. 5, and the 5CPU 20 executes the program shown in FIG. Here, the MCPUIO generates a musical tone signal in the flow shown in FIG. 5, and the 5CPU 20 generates a musical tone signal in the flow shown in FIG.

Specifically, the MCPUIO generates, accumulates, and stores musical waveform data for each channel at 5-1. Conventionally, this processing was performed in the sound source circuit/\-ware.
MCPUIO in the next interrupt processing timer processing 5-2
takes advantage of the fact that interrupts occur at regular intervals, and increments the flow cycle timer register (in RAM 106) by 1 each time it passes. MCPUIO at 5-3
checks whether the sound source processing 6-1 of the 5CPU 20 has been completed, and if it has been completed, proceeds to 5-4 and processes the 5CP
The musical tone waveform data on the RAM 206 generated in U20 is read into the RAM 106.

Then, at 5-5, the MCPUIO outputs the musical tone waveform data generated by the MCPUIO and the musical tone waveform data generated by the 5CPU 20 to the DACI OO.

Details of the sound source processing 5-1.6-1 are shown in FIG. 7. In this example, each CPU (MCPUIO 1 SCPU 20) can generate musical waveform data for 8 channels,
As a whole, the system can generate musical waveform data for 16 channels. Clear the waveform addition RAM area (RAMI06, RAM206) in 7-1, and
In steps 2 to 7-9, sound source processing for each channel from the first channel to the eighth channel is sequentially executed. At the end of each channel sound source processing, the tone waveform value of the channel is added to the data in the waveform addition RAM area.

Next, an example of channel sound source processing will be described with reference to FIGS. 9 to 11. In this example, the PC to read out the waveform
M) method of musical sound synthesis is adopted (other musical sound synthesis methods, such as FM synthesis, are also possible, and this invention is not limited to a specific musical sound synthesis method). Channel sound source processing can be broadly divided into envelope and Processing (9-1 to 9-7)
and waveform processing including envelope addition (9-8 to 9-2
1). Each CPU (MCPUIO1SCPU2
0) is a group of sound source processing registers for that channel when executing channel sound source processing, that is, as shown in FIG.
, refer to the current envelope, address addition value, loop address, end address, start address and current address, and update the desired register. The envelope should be added to the basic waveform for amplitude modulation, and consists of several segments (steps) as a whole.

The timer for the envelope ΔX, the target envelope, the envelope ΔX, and the envelope Δy with addition/subtraction flag are the envelope processing parameters 4J that define the envelope segment currently in progress.
In the sound generation process 4-9 of the MCPUIO main program (Figure 4), this information is updated each time the envelope value reaches the target value of the segment, and in the interrupt processing routine (Figures 5 and 6). These envelope parameters are only referenced, except for the timer for envelope Δχ. The envelope ΔX represents the calculation cycle of the envelope, the target envelope represents the target value of the envelope in the current segment, the envelope Δy with addition/subtraction flag represents the change in the envelope for each calculation cycle, and the current envelope represents the current envelope value. The address addition value, loop address, end address, and start address/current address are address information for the basic waveform placed in the external memory 90, the start address is the start address of the basic waveform memory (in the external memory 90), and the loop address is the basic Return destination address (first
The end address is the end address of the basic waveform, the current address is the address that represents the current phase of the basic waveform, and the integer part is the memory location that actually exists in the basic waveform memory. , the decimal part of which represents the deviation from this memory location,
The address addition value is the value to be added to the current address at each time interval of the timer interrupt processing routine,
Directly proportional to the pitch of the musical note being generated.

To explain in detail, in 9-1, the envelope calculation period ΔX
Increment the timer register for comparison with ΔX at each interrupt, and when it matches ΔX at 9-2,
Test the addition/subtraction flag (sign bit) of the envelope displacement data Δy to determine whether the envelope is rising or falling, and subtract or add the current envelope in steps 9-4 and 9-5, respectively.9- At step 6, check whether the current envelope has reached the target envelope value,
If it has been reached, set the target level in the current envelope. This causes the next envelope step data to be set in the main program's sound generation process 4-9. Furthermore, when the current envelope of zero is read in the sound generation process 4-9, it is processed as the end of sound generation.

Next, waveform processing 9-8 to 9-21 will be described. In waveform processing, the integer part of the current address is used to read the waveform data of two adjacent addresses from the basic waveform memory.
The expected waveform value for the current address indicated by (integer part to decimal part) is obtained by interpolation. The reason why interpolation is necessary is that the waveform sampling period due to the timer interrupt is constant, and the added value of the address (pitch data) spans a certain range in application to musical instruments. (If waveform data is prepared for the original sound, there is no need for interpolation, but this would result in an unacceptable increase in storage capacity.) Since timbre deterioration and distortion due to interpolation are more pronounced in the high frequency range, the original sound is recorded at a faster rate than the recording sampling rate of the original sound. In this embodiment, it is preferable to reproduce the original sound (4-
4) The playback cycle is doubled (Fig. 1O). Therefore, when the address addition value is 0.5, an A4 sound can be obtained. In this case, the address addition value is 0.529 for A#4, and 1 for A3. These address addition values are stored as pitch data in the control data/waveform external memory 90, and when a key is pressed, in the sound generation process 4-9, the pitch data corresponding to Il and the waveform start address of the selected tone, The waveform end address and the waveform loop address are set in the corresponding registers of RAM 106 or RAM 206, ie, address addition value register, start address/current address register, end address register, and loop address register.

For reference, in FIG. 10, which shows interpolated waveform data with respect to time, white circles indicate waveform data values stored at storage locations in the basic waveform memory, and X marks indicate output samples containing interpolated values.

There are various interpolation methods, but here we use linear interpolation. In detail, first, in step 9-8, an address addition value is added to the current address to obtain a new current address. At 9-9, compare the current address and end address,
If current address>end address, 9-1O19-
11, if the current address is the end address, it is 9.
-12, the next physical (address) or logical (operational) address is calculated, and the integer part accesses the basic waveform memory at 9-14 to obtain the next waveform data. The loop address is operationally the next address after the end address. That is, in the case of FIG. 10, the illustrated waveform is repeatedly read out. Therefore, when the current address = end address, the waveform data of the loop address is read as the next address (9-13), 9-15.91
Step 6 accesses the basic waveform using the integer part of the current address and reads the current waveform data.Next, step 9-17 subtracts the current waveform value from the next waveform value, and step 9-18 subtracts the current waveform value from the current address. A linearly interpolated value of the waveform is obtained by multiplying the decimal part and adding the result to the current waveform value at 9-19. Multiply this linearly interpolated data by the current envelope value to obtain the musical tone data value of the channel (9-20)
, adds it to the contents of the waveform addition register and accumulates musical tone data (9-21). The digital musical tone data accumulated in this register is sent to the timer interrupt processing routine (9-21).
It is sent to DACloo at 5-5 in FIG. In this regard, in FIG. 1, the DAC 100 consists of a right DAC 100R and a left DAC 100L to obtain a stereo output.

In this case, it is preferable to decide which of the left and right DACs to assign each of the sound source channels processed by the MCPUIO 1 SCPU 20. Specifically, one selected DAC instruction data is stored on the internal RAM 106, 206 as the sound source data for each channel. It also has two waveform addition areas, namely, a waveform addition area for the left DAC and a waveform addition area for the left DAC.
Provide an area for waveform addition. In addition, in the step corresponding to 7-1, each waveform addition area for the left and right DACs is cleared, and after the processing in 9-20, the DAC assigned to the processing channel is determined from the selected DAC instruction data, and the corresponding Add the musical waveform data of the processing channel to the waveform addition area. Then, in a step corresponding to step 5-4 of the interrupt processing routine of the MCPUIO (FIG. 5), the musical sound waveform data for the left DAC and the east sound waveform data for the right DAC generated by the 5 CPU 20 are transferred to the left DAC generated by the MCPUIO. add the music waveform data for the left DAC and the right DAC #11 music waveform data, and send the addition results, the music waveform data for the left DAC and right DAC, to the left DAC 100L and right DAC 100R, respectively, in steps corresponding to 5-5. .

In this way, the electronic musical instrument processing device of this embodiment uses the MCPU
It has multiple CPUs, IO and 5CPU20, and each CPU
In U, sound source processing can be executed according to a built-in program. In the example, one 5 CPU
However, a plurality of 5 CPUs may be provided to perform sound source processing.

<5CPU operation start/end function (I@12 to Figure 15,
(FIGS. 2 to 6, FIG. 8)> According to this embodiment, the MCPUIO has a function of managing and understanding the operating period of the 5 CPUs 20.

For this purpose, (a) MCPUIO is the timer interrupt generator 11.
When an interrupt signal is generated from 6, the 5CPU 20 starts operating using this as a signal, and the 5CPU status flag referred to by the operation control circuit 112 of MCPUlo is set to ``5CPU in operation''.

(b) When the SCPU 20 completes the operation (sound source processing), 5
In response to this, it transitions to the stop state, sends an operation completion signal to MCPUIO, and sets the 5CPU status flag referenced by the operation control circuit 112 of MCPUIO to “5CP
Set to "U Stopping".

Referring to FIGS. 2 to 6, the MCPUIO interrupts the interrupt generation section 1 during execution of the main program (FIG. 4).
When an interrupt signal is received from 16 (Fig. 2), RO
The main program is interrupted via the M address control unit 114, and a timer interrupt processing routine shown in FIG. 5 is executed to generate musical tones. Furthermore, in response to the interrupt signal, the MCPUIO sends 5CPU operation start No. 7 A to the 5CPU 20 via the 5CPU reset control unit 134.
In response to this, the 5CPU 20 controls the ROM address control unit 21.
4 to execute the program for musical tone generation shown in FIG.
The M address control section 204, the RAM data-in switching section 240, and the write signal switching section 242 also have 5 CPUs 20.
(set for its own operation), upon completion of this program, the 5CPU 20 starts the operation control circuit 2.
12 also generates an operation end signal B. This signal B is 5C
It is sent to the PU reset control unit 134, and in response, the 5C
The PU reset control unit 134 inverts the signals A and B to stop the operation of the 5 CPU 20. Upon receiving the inverted signal A, the address updating operation of the ROM address control unit 214 of the 5 CPU 20 is stopped, and the 5 CPU 20 is stopped. In addition, signal B is used as a signal indicating "5 CPU is stopped" by the MCP.
The signal is applied to the operation control circuit 112 of the UIO.

When executing the 5CPU status check command shown in 5-3 of the MCPUIO interrupt processing routine (Figure 5), the MCPUIO
The PUIO operation 1 control circuit 112 reads the 5CPU status flag B, and the flag B indicates "5CPU is stopped", so the sound source processing by the 5CPU 20 is performed (Fig. 6).
is completed, MCPUIO advances to 5-4 and 5
MC reads the musical waveform data generated by the CPU 20
At the end of the interrupt processing routine shown in FIG. 5, PUlo gives a command signal for returning to the main program from the operation overlap control circuit 112 to the ROM address control unit 114 to return control to the interrupted main program.

FIG. 8 shows the flow of the operation of this embodiment along the flow of time, and A to F are fragments of the main program. 5A~5
F represents the MCPU interrupt processing routine in FIG. 5, and 6A to 6F represent the 5th CPU interrupt processing routine in the 6th FgJ. Processing starts in each CPU10120, and parallel processing of sound sources is performed.

FIG. 12 shows in detail the configuration that realizes the operation start and end functions of the 5 CPUs mentioned above, and FIGS. 13 to 15 show time charts of the operations. In the time chart of FIG. 13, CKI and CK2 are MCPUIO and 5CPU2
This is a two-phase master clock that is input to the clock generation circuits 136 and 236 at MCP 0, and from these master clocks CK1 and CK2, the clock generation circuit 136
A three-phase clock T1. provides basic timing for UIO operation. Generate T2 and T3. The repetition period of this three-phase clock is a machine cycle (the shortest instruction execution time)
Establish. Clocks TlCK1, T2CK2, T3CK
3 are Tl and CK1.3, respectively. T2 and CK2. T3 and C
This is the AND signal of K3. The operation 2,000 signal is a signal for causing the instruction output latch 102a of the control ROM 102 of the MCPUlo to latch an instruction from the ROM 102.

Although not shown in FIG. 13, the clock circuit 236 of the 5 CPU 20 also generates a similar clock signal (see FIGS. 3 and 25). Note that a common clock generation circuit may be used for the MCPUIO and the 5 CPU 20. .

In FIG. 12, the right side of the dotted line 16 is the 5 CPU 20, and the left side is the MCPUIO. Among the elements on the left, latch L1. Latch L2. Gate l! 42-1154 are MC
This is a circuit element included in the ROM address control unit 114 of the PUIO (FIG. 2). The latch Ll contains ROM102 address information AN of the next instruction to be executed by MCPUIO.
(information contained in the current instruction from ROM 102) is latched with clock TICKI. Main program (4th
v! During execution of J), the output of latch L1 is the next address BN.
The address is input to the ROM address decoder 104 of the MCPUIO. That is, the output of latch L1 is output from inverter 11.
44.3-state inverter) 1146 (enabled) and becomes the address input BN to the ROM address decoder 104. Here, interrupt generation part 1
When an interrupt signal INT is generated from 16, a signal is applied from an OR gate 1154 receiving this signal INT to turn off (high impedance) the 3-state inverter 1146 on the output side of the latch L1 via an inverter 1148. Instead, a signal from the OR gate 1154 is used to select the interrupt address/return destination address (11).
A three-state inverter (gate) 1152 on the output side of gate 1150 converts the output of gate 1150 to ROM address decoder 104.
6 interrupt input BN/return destination address selection game) 1150 is the interrupt signal INT and latch L
It consists of a group of NOR gates that receive output signals from 2,
When the interrupt signal INT of 'H' is generated, the entrance (entry point) of the interrupt processing routine (Fig. 5)
This signal is inverted by a 3-state inverter (1152) and outputs an all-0 signal representing
” is input to the ROM address decoder 104 of the MCPU as a signal BN. Then, in response to the next operation latch signal, an instruction is output from the control ROM 102 and the first instruction of the interrupt processing routine is fetched from the control ROM 102 to the chip 102a. , MCPUI
Control of O is transferred to the interrupt processing routine.

Furthermore, the interrupt signal INT from the interrupt generating section 116 passes through the AND gate (1142) at the timing of the clock 72CK2, and operates the latch L2 as a latch signal. As a result, latch L2 latches (saves) the address of the next instruction of the main program on bus AN.
to interrupt the main program.

Furthermore, the interrupt signal INT from the interrupt generating section 116 is supplied to the 5 CPU reset control section 134.

The 5 CPU reset control unit 134 includes a D flip-flop 1342 and a NAND gate 134 coupled as shown in the figure.
4. It consists of an R-S flip-flop 1346. During main program execution, R-S flip-flop 1346
Although not shown, the R-S flip-flop 1346 is initialized to the reset state when the system is powered on.

The interrupt signal INT is taken into the D flip-flop 1342 at the timing of the clock T2CK1, and the NAND gate)1 is taken in at the timing of the next clock TICKI.
344 and is inverted and output, setting an R-S flip-flop 1346. As a result, the Q output of the R-S flip-flop 1346, that is, the signal A changes from "H" to "L".
”, and the Q output, that is, the 5 CPU status flag, becomes “L”.
” (indicating SCPU is stopped) to “H” (SCPU
(indicating that it is in operation). @ No. A is input as a reset release signal (enable signal of latch L3) to latch L3 for latching the address SAN of the next instruction in 5 CPU 20. As a result, the latch L3 inputs the address of the first instruction of the 5 CPU program (FIG. 6) on the bus SAN to the ROM address decoder 204 of the 5 CPU 20 as SBN at the timing of the next clock TlCK1. In this way, in response to the interrupt signal INT from the interrupt generating section 116,
The operation of the CPU 20 starts.

The sound source processing shown in FIG. 6 is executed.

5 CPU 20 executes the last instruction of sound source processing 68.5
An operation end signal (return command signal) SRT is generated inside the operation control circuit l12 of the CPU 20. This signal SRT is taken in by the D-flip 70 block 2122 at the timing of a-tuck T2CK1, and then the next TI
It is inverted by the NAND gate (NAND game operating at the CKI timing (latch timing of the next dummy instruction)) 2124 and resets the R-S flip-flop 1346 of the 5 CPU reset control unit 134 as a low-pulse operation end signal B. As a result, the Q of the R-S flip-flop 1346 is
The output, that is, the signal A switches from "L" to "H'',
The Q output, that is, the 5 CPU status flag switches from "H" indicating that the 5 CPU 11 is in operation to "L" indicating that the 5 CPU 20 is stopped. The operation of the latch L3 is prohibited by the 'H' level signal A (reset signal), and the output of the latch L3, that is, the input of the address decoder 204 is
o? (instruction) address. At this time, latch L
3 input bus SAN contains address information (NOP
(included in the command word) is on board.

The MCPUIO checks the level of the 5CPU status flag via the operation control circuit 112 when executing the 5CPU status check instruction 5-3 of the included processing routine (FIG. 5), and checks the level of the 5CPU status flag while the 5CPU is stopped, that is, the sound source processing of the 5CPU 20 is completed. After confirming that, the musical sound waveform data that is the processing result of the 5 CPU 20 is read from the RAM 206 to the RAM 106 (5-4). As a result, the MCPUIO
20 correct processing results can be efficiently obtained.

The MCPUIO generates a pulse of the return command signal RT from the operation control circuit l12 when the last instruction of the interlab 143 routine is executed. This signal pulse RT passes through an OR gate 1654, an inverter 1148, and an address gate (11464-) on the output side of the latch Ll.
At this point, the address gate 1152 on the output side of the interrupt row/return address selection gate 1150, coupled to latch L2, is temporarily turned off and the interrupt row/return address selection gate 1152 coupled to latch L2 is temporarily opened. Return destination address selection game) 1150 functions as an inverter that inverts and passes the address of the interrupted main program instruction saved in latch L2, and the inverted output of this gate 1150 functions as an inverter by signal pulse RT. 3 state game) is inverted again at 1152. As a result, the address of the interrupted main program instruction is input to the ROM address decoder 104 of the MCPUIO, and the primary operation latch signal causes the instruction to be transferred from the control ROM 102 via the instruction output latch 102a. taken out. In this way, control of MCPUIO returns to the main program.

As described above, the electronic musical instrument processing device of this embodiment has the MCP
5 CPUs manage the operation period of 5 CPUs 20 by UIO.
By providing a suitable management interface configuration such as the reset control unit 134, this can be done efficiently and reliably.

Multiple data transfers> In some types of application software using the CPU, the CPU
updates multiple data during execution of the main program (first program), and updates the interrupt processing routine (
When the second program) is executed, these multiple pieces of data are referenced for the purpose of processing. This is the problem of passing data from the main program to the interrupt processing routine. Such multiple data must be updated in the main program before the main program is interrupted by the interrupt handling routine, or the main program is interrupted when only a part of the multiple data has been updated. If the CPU control is transferred to the interrupt processing routine, the processing result of the interrupt processing routine will be incorrect.

In the case of the electronic musical instrument processing device of this embodiment as well, a plurality of messages are passed from the MCPUIO main program (Fig. 4) to the MCPUIO timer interrupt processing routine (Fig. 5) (and the 5 CPU 20 timer interrupt processing routine shown in Fig. 6). data is Al, envelope ΔX (envelope o
An example is the two-fold rope parameter consisting of the target envelope and the envelope Δy (envelope change). The external data memory 90, which is a data source, stores envelope parameters for each envelope segment (eg, attack segment, decay segment, sustain segment, etc.). The main program of MCPUlo is the sound processing 4-
9, the envelope detected in the key press (note-on) or in the channel sound source processing (9th FIIJ) of the interrupt processing routine reaches the target value (9-6,
9-7), the envelope parameters (new target envelope, envelope Δx, envelope with adjustment Δy) for a predetermined segment are retrieved from the external data memory 90 and stored in the MCPU internal RAM 1.
It is necessary to update the envelope parameter consisting of a plurality of data by setting it in the corresponding channel sound source processing register of 06 (or 5 CPU internal RAM 206). Such a plurality of data must be updated in the main program before the main program is interrupted by the interrupt signal INT from the interrupt generating section 116.

In order to solve this problem of multiple data transfers (updates), this embodiment discloses two solutions. 1st
The solution to this problem is an interrupt masking method that masks interrupts during data updating so that the execution of the main program's data update instructions is not interrupted.
The solution to this problem is a one-instruction method that utilizes the ability to execute multiple data transfers with one instruction.

Interrupt mask method (16th, 17th. 2nd to 7th
(Figure) According to this method, an interrupt from the interrupt generation unit 116 is generated by an internal 1? While data is being set in the AM channel sound source register group, it is masked and the control of the MCPUIO is prohibited from being transferred from the main program (FIG. 4) to the interrupt processing routine (FIG. 5).

Figure 17 shows envelope processing including multiple data transfers (
Fig. 16 shows the hardware related to the interrupt mask.

In FIG. 17, the MCPUIO checks in step 17-1 whether the current envelope of the designated sound source channel has reached the target envelope. If this is reached, the MCPUIO proceeds to step 17-2, retrieves the envelope parameters for the next envelope segment from the external data memory 90 (FIG. 1), that is, the new target envelope, the envelope Δy with addition/subtraction flag, and the envelope ΔX, and stores them in the internal RAM 106. transfer buffer.

Here, the transfer buffer is an intermediate storage unit between the data source and the data destination, and the interrupt processing routine (JF
! 9rI! Since this is a RAM area that is not referenced by J), an interrupt mask is not required at this point. The reason for providing the transfer buffer is that the data source memory 90 is an external memory shared by the MCPUIO and 5 CPUs 20, and the data access time is limited to the internal RA.
This is due to the fact that the data transfer time is longer than the data transfer time between the M units. The function of block 17-2 is processed by sequentially executing a plurality of data transfer instructions from external data memory 90 to internal RAM 100.

Data transfer from the transfer buffer to the channel sound source register group (referenced in the interrupt processing routine) is executed in block 17-4. To prevent MCPUIO control from shifting to the timer interrupt processing routine (Figure 5) during this data transfer (or
In order to prevent control of the CPU 20 from transferring to the program of FIG. 6), MCPUlo executes an interrupt masking instruction in block 17-3 prior to block 17-4. While this interrupt mask 64 is being executed, a low active mask signal MASK is generated from the MCPUIO operation control circuit 112. This mask signal MASK acts to mask the interrupt signal INT from the interrupt generating section 116 and prohibits control from shifting to the interrupt processing routine (FIGS. 5 and 6). For this purpose, in Figure 16,
A mask release special unit 150 coupled to the interrupt generating unit 116 is provided. The mask release special unit 150 includes an R-S flip-flop 1502 and an AN
D game) 1504 and a D flip-flop 1506.

When the mask signal MASK is at the "H" level indicating mask release, the R-S flip-flop 1502 is set by the interrupt signal INT from the interrupt generating section 116, and its output connects the AND gate enabled by the "H" MASK. Through, D flip-flop 1
506 at the timing of TICKI, this D
The output of the flip-flop 1506 is input to the ROM address control section 114 of the MCPU 10 as an actual interrupt signal A-I NT. As a result, 5 CPU operation MMI-H completed*#! , (1) As mentioned earlier,
ROM address control unit 114 game) 1152 to RO
The address of the entry point of the interrupt processing routine (FIG. 5) is input to the M address decoder 104, and the address of the next main program instruction is saved from bus AN to latch L2, and control of MCPUIO is transferred to the interrupt processing routine. The main program will be interrupted. Further, the signal A-INT is input to the 5CPU reset control section 134, and as a result, the program (FIG. 7) operation of the 5CPU 20 is started as described in the 5CPU operation start/end function. The H level output from D flip-flop 1506 resets R-S flip-flop 1502, so that the next TICK
At the timing of I, the output of the D flip-flop 1506 (
The output of the mask release special unit 150) is switched to L level.

On the other hand, as shown in FIG. 17-3, when the low active mask signal MASK is input from the operation M control U path 112 to the mask release special unit 150 by executing the interrupt mask command, , the interrupt signal from interrupt generation 41116 is masked by AND gate 1504. As a result, while the mask signal MASK is low active, the mask release special unit 1504 sets its output A-INT to the "L" interrupt disable level, continues the normal operation of the ROM address control circuit 114, and executes the main program for the MCPUIO. control continues.

Therefore, the execution of the transfer command group (and the clear command for the envelope Δχ timer) shown in block 17-4 is as follows:
Even if the interrupt signal INT is generated from interrupt occurrence 1!1116 during execution, it will not be interrupted.
As a result, the interrupt processing routine (Figures 5 and 6)
(Figure) can refer to correctly updated letter envelope parameters and obtain correct calculation results (music waveform data).

Thereafter, MCPUIO executes the interrupt mask release instruction shown in block 17-5. As a result, the signal MASK supplied from the operation control circuit 112 to the mask release special unit 150 switches to the "H" level indicating mask release. Block 17- containing multiple data transfers
4, if an interrupt signal is generated from the interrupt generation unit 116, the output of the R-S flip-flop 1502 of the mask cancellation special unit 150 causes an interrupt request to be issued after the execution of this mask cancellation command. Acceptance is accepted, the main program is interrupted as described above, and control is transferred to the interrupt processing routine.

One instruction method (Figures 18 to 21) This method stores multiple data in the main program (Figure 4) from the internal RA referenced by the interrupt processing routine.
To set it in the M area, a single instruction called a long instruction for bulk transfer of multiple data is used, and the MC is sent to the interrupt processing routine until the execution of the long instruction is completed.
This is to prevent PUIO control from shifting.

A CPU capable of transferring a plurality of data with a single instruction (long instruction) is disclosed, for example, in Japanese Patent Publication No. 47612/1983, and this technique can be applied to this embodiment. Special Public Service 1986-
According to No. 47612, long instructions can be applied to transfer between multiple registers at consecutive addresses (for example, registers AO to A3 to registers BO to B3) (here, a register means one memory location in RAM). and A and B are R
Represents the upper address of AM, that is, the row address, and is 0.3
represents the lower address of RAM, that is, the column address),
The long instruction word from the control 1'lOM (corresponding to element 102 in this embodiment) contains the source register row address (A in the above example), the destination register row address (B), and the first Information about the column address (0) of the register related to the data transfer and the column address (3) of the register related to the last data transfer is included. The RAM address control section (corresponding to element 105 in this embodiment) is configured to be suitable for long instruction execution, and changes the column address from the column address of the first transfer to the column address of the last transfer, l, for each data transfer. A counter that updates continuously (its output is R
(sequentially added to the column address input of AM) and the column address value of the last data transfer to detect that all data transfers have been completed. When they match, the long instruction execution completion signal is output. and a matching circuit that generates a match.

In the following description, it is assumed that the main program of the control ROM 102 of this embodiment includes the above-mentioned long instructions, and the RAM address control unit 105.205
It is assumed that the configuration is such that the execution of long instructions can be applied as described above.

Figure 18 shows that during the execution of a long instruction, the interrupt signal IN
A block diagram of the hardware including a circuit that prohibits interruption of the main program by T is shown in Figure 19.
A memory map of AM is shown, and FIG. 20 shows a comparison of operations between a long instruction (single transfer instruction) and multiple transfer instructions.
FIG. 21 shows a flowchart related to envelope parameter transfer using a long instruction.

In FIG. 18, a transfer termination special unit 152 is coupled to the interrupt generating unit 116. This circuit 152 prohibits interruption of the main program by an interrupt signal during execution of a long instruction. At the end of transfer aI! The portion 152 is connected to the R-S flip 7+ff-/pu1 as shown.
522, AND gate 1524, D flip-flop 1
526, and the output of the D flip-flop 1526 (
The output of the transfer end special unit 152) is sent to the ROM address control unit 2 as the interrupt signal A-INT that actually acts.
14 and 5 are coupled to the CPU reset control unit 134.

AND game) Signal input to 1524 ~ LONG is L
”, even if the interrupt signal ZNT is generated from the interrupt generation unit l16, the D flip-flop 1526
The output of the ROM address control unit 21 remains at L”.
4 and 5 The CPU reset control unit 134 is not affected by the interrupt signal INT. Here, the signal ~LONG is a signal that becomes "L" during execution of a long instruction, and RAM address control is performed upon completion of execution of the long instruction. It returns to "H" in response to the long instruction execution completion signal generated from the coincidence circuit of section 104. When the level of the signal ~LONG is "H", the interrupt signal INT from the interrupt generation section 116 passes through the transfer end special section 152 to the ROM address system '111g214to5CPU! J Sey to f1
111 part 1341. :Acts to transfer the control of MCPUIO from the main program (Fig. 4) to the interrupt processing routine (Fig. 5), and transfers the control of MCPUIO from the main program (Fig. 4) to the interrupt processing routine (Fig.
Figure 6) Start the operation.

When applying the one-instruction method to update envelope parameters, the channel sound source processing subroutine (Fig. 9) of the interrupt processing routine (Figs. 5 and 6) refers to the envelope processing subroutine (Fig. 21) of the main program. ) is set (updated) by envelope parameters such as envelope Δχ timer, new target envelope c
r-fu.

j envelope Δx, 1llo11 flagged envelope Δy, 0. In this embodiment, the data source for these envelope parameters is the external memory 90 (FIG. 1).
When updating the envelope parameters in (21-
1), from external data memory 90 to internal RAM 106.2
Since direct transfer to the channel sound source data area of channel 06 is not desirable, the envelope parameters of the external data memory 90 are temporarily transferred to the transfer buffer γ area in the internal RAM 10B (2l-2), and then transferred to the transfer buffer area. Move from to channel sound source data area (21-3)
.

The above-mentioned long command is used in the data transfer process 21-3 from the transfer buffer area to the channel sound source data area. In order to apply the long command, the transfer buffer γ area needs to be a continuous area on the RAM, and similarly the channel sound source data area of the envelope parameter needs to be a continuous area. An example of this is shown in FIG. 19. Here, the envelope parameter transfer buffer area is mapped to a continuous area of registers X4 to x7, and the one-channel sound source data area for envelope parameters is mapped to a continuous area of registers A4 to A7. mapped to the area. Therefore, when it is necessary to update the envelope parameters in one channel, registers x4 to x7 are transferred to register A in 21-3.
4 to A7. While this instruction is being executed, even if the interrupt signal INT is generated from the interrupt generation section 11B as described above, the long instruction of the transfer end special section 152 is executed. Due to the instruction completion wait function, the effect of the interrupt signal does not affect the I'lOM address control unit 114.5 CPU reset control unit 134 until the long instruction is completed (see FIG. 20(B)).
As a result, the interrupt processing routine starts after all the envelope parameters in the channel sound source data area have been changed to the correct update values, so the calculation result (music waveform data) shows the correct value and error-free operation is guaranteed. Ru.

On the other hand, if you try to perform the transfer processing function shown in 21-3 by executing multiple transfer instructions (one envelope parameter is transferred for each - instruction),
For example, if an interrupt signal INT occurs during the execution of transfer instruction 1 as shown in No. 209 (A) during transfer, the first instruction of the interrupt processing routine is executed instead of transfer instruction 2 in the next machine cycle. As a result, the envelope transfer process is interrupted midway.As a result, the processing result of the interlab) ILJI routine (music waveform data)
will be an incorrect value.

- 1 for multiple data transfer (update) processing using command method
There is also the advantage that there is no need to execute an interrupt mask instruction or an interrupt release instruction as shown in 7-3.17-5, and transfer processing can be executed in the shortest possible time without overhead.

As a modified example, a transfer termination special unit 1 as shown in FIG.
52, the control ROM 10 is used during execution of a long instruction.
2. An instruction that fetches instructions from 202,
A means for inhibiting the operation of the latch 102a from the control ROM 102 may be used.
By the mode signal (indicating that the instruction is long) included in the long instruction word given via a,
Prohibits the generation of the operation latch signal applied to the instruction output latches 102a and 202a, and operates the circuit that generates the operation latch signal in the next machine cycle in response to the long instruction execution completion signal.
If provided in the interrupt signal IN control circuit 112, the interrupt signal IN
Even if T occurs during the execution of a long instruction, the control ROM 10
2. Since the first instruction word of the interrupt processing routine from 202 is not fetched into the instruction output latches 102a, 202a (and therefore not executed) until the execution of the long instruction is completed, the same effect as in the embodiment can be obtained.

<Function for accessing 5 CPUs from MCPU> The device of this embodiment accesses the internal RAM 206 of 5 CPUs 20 from MCPUIO.
It has the ability to access (read or write) data at high speed.

This problem is generally overlooked as a data access problem between multiple CPUs. In the prior art, there is a problem in that this type of inter-CPU data access takes time. In the prior art, a request signal is given from a CPU requesting access to a CPU requesting access. In response to this request signal, the CPU to which access is requested cannot immediately generate an acknowledgment signal that allows data access from the requesting CPU, and cannot accept the request signal until the ongoing operation is completed. ! Delay the generation of the signal. Therefore, the conventional inter-CPU data access method has become one of the obstacles in applications requiring high-speed processing.

In this embodiment, two solutions are disclosed for high-speed inter-CPU data access, namely, a 5-CPU stop mode utilization method and an instantaneous forced access method.

5CPU stop mode utilization method (FIGS. 22, 2, and 3) This method utilizes the above-mentioned 5CPU operation start/end function. With this function, the program operation of the 5CPU 20 (Fig. 6) starts simultaneously with the start of the interrupt processing routine (Fig. 5) in the MCPUIO, and
It ends before the PUIO interrupt processing routine ends. Therefore, while the main program (FIG. 4) is operating in the MCPUIO, the 5CPU 20 is in the stop mode (reset state t!i). In the stop mode as shown in FIG. Signal A becomes "H" level indicating "5 CPU is stopped".

This signal A causes the 5 CPU 20 (Fig. 3) to read the ROM
The operation of the 7-address control unit 214 is stopped, and the RAM address control unit 204 connects to the RAM address bus Ma from MCPUIO via the bus gate 128 instead of the RAM address bus SA from the control ROM 202 of the 5CPU 20. 5 The operating mode is set to receive the designated address of the CPU internal RAM 206, and the R
The AM data switching unit 240 receives the operation result of the 5 CPU 20 (ALU unit 208 output or multiplier 210
RAM 206 on the data bus D OUT which carries data from MCPUIO instead of the data bus DB which carries data (output).
The write signal switching unit 242 uses the read/write control signal C from the operation control circuit 112 instead of the read/write control signal from the 5 CPU operation control circuit 212 to read the data from the RAM 206. / set to the operating mode coupled to the light control input. When stopped like this,
The 5 CPU 20 is placed in a state where it can access data by MCPUlo.

Therefore, according to this embodiment, the MCPUIO can freely access the internal RAM 206 of the 5 CPUs 20 in the main program. This situation is shown in FIG. 22, which shows the stoppage L! of the 5 CPU 20. i (sound source processing complete)
Confirmation of MCPU operation control W circuit! The check of the 5CPU status flag from the 5CPU reset control unit 134 in step 12 only needs to be performed once in the MCPUIO interrupt processing routine (Fig. 5) (see 5-3); once the stopped state is confirmed, Until the next interrupt signal INT occurs, without the need for confirmation again, - upon execution of the instruction, the MCPUIO
The internal RAM 20B can be accessed. Therefore, the time required for data access to the 5 CPUs 20 is significantly reduced compared to the prior art.

Instant forced access formula Figures 23 to N425) This method uses MCPUIO and 5CPU20 for data access.
When MCPUIO accesses 5CPU data, the operation of 5CPU20 is forcibly suspended, without going through the conventional procedure of requesting and approving access between the MCPUIO and
06. According to this method, M
The CPU 10 can access the 5 CPUs 20 at high speed (by executing -instructions) without having to check the status of the 5 CPUs 20 at any time.

Block diagram of MCPUIO with such features and 5
The block diagrams of the CPU 20 are shown in FIGS. 23 and 24, respectively. This MCPU and 5CPU are the 5C
Elements related to the PU operation start/end function (5 CPUs in Figure 2)
The reset control circuit 134 and others) are not shown in FIGS. 23 and 24 for the sake of simplicity. In this case, it is sufficient to supply the 5CPU operation start/stop signal A from the reset control circuit 134 only to the ROM address control unit 214 of the 5CPU 20 (FIG. 24). FIG. 25 shows a time chart of operations related to instantaneous forced access of the MCPUIO and 5 CPU 20 shown in FIGS. 23 and 24.

When using the instantaneous forced access method, MCPUIO and 5CPU20 are separate clock generation circuits 136.236
Requires M. 5 Clock generation circuit 23 of CPU 20
6M stops its operation in response to a high active 5CPU access signal output from the operation control circuit 112M of MCPUIO when a data access instruction to 5CPU 20 is executed. In this regard, MCPUI
The clock generation circuit 136 of the CPU 20 and the clock generation circuit 236M of the 5 CPU 20 use a common two-phase master clock signal C.
K1. Although it receives CK2, the timing of the output clock is independent. In MCPUIO, clock generation circuit 1
A machine cycle (the shortest one instruction execution time) is defined by one period of the three-phase clock signals T1, T2, and T3 from 36.

On the other hand, in the 5 CPU 20, a machine cycle is defined by one period of the three-phase clock signals STI, Sr1, and Sr1 from the clock generation circuit 236M.

In FIG. 25, before the 5CPU access signal is generated, the timing of clock T1 regarding MCPUlo matches the timing of clock ST2 rather than clock STI regarding 5CPU20.
Other possible timing relationships for 1i# are a relationship where TI matches STI and a relationship where Tl matches Sr1.

The 5 CPU access signal output from the operation control circuit 112 during execution of the 5 CPU access instruction in MCPUIO is generated by the clock generation circuit 23 of the 5 CPU 20.
In order to stop the operation being executed by the 5 CPU 20 by stopping the 6M, and to allow the MCPUIO to access the internal RAM 206 of the 5 CPU 20 during the stop, the bus gate 128.
address control unit 204, data-in switching unit 240. It also has a function of switching each operation mode of the write signal switching unit 242 from "5CPU side" to "MCPUIII". To this end, the 5 CPU access signal is coupled via a delay circuit consisting of a D flip-flop 250 and an AND gate 252 to a control input that selects the operating mode of these elements 128, 204, 240, 242. Under such an accessible state, the MCPU
10 is a bus gate 128 and a RAM address control section 20
Addresses the 5 CPU internal RAM 206 via the 5 CPU internal RAM 206 via the
The data output from 6 is passed through bus gate 132 to M
The data is read into the CPU internal RAM 106, and in the case of write access, the write data is transferred to the data bus D0LIT via the bus game) 130, and the data is transferred to the CPU internal RAM 2.
A write signal C is given to 06 to write data.

5 CPU access signal from MCPUIO
When interrupting the operation of the CPU 20, it is necessary to prevent the intermediate results of the operation from being lost. I need to be able to do the rest. For this,
5CPU internal RAM 206 data output is temporarily stored, and chips 206a and 206b are provided. latch 2
06a latches the operation number (w41 operand) from RAM206 at the timing of 5TICKI, and
6b is the operand from RAM 206 (second operand)
is latched at the timing of 5T2CK1.

An operation example will be described with reference to FIG. 25. In this example, M
The CPUIO executes write access to the internal RAM 206 of the 5 CPU 20 while the 5 CPU access signal is at a high active level. In MCPUlo, the first time slot TI of this data write operation
During this period, transfer data (R
0th time slot T2f to take out data to be written to AM206 MCPU10 is 5 CPU internal RAM
Dress 206 7 times. Last Times)
T3? M CPU 10 is 5 CPU internal RA
The write signal C is given to the M20B to write data to the RAM 206.The 5CPU access signal Dt*s from the 10 MCPUs for the 5CPU 20 is active when the operation mode 2 of the cPU 20 moves to the time slot ST2. This operation 2 is 5
The operands and operands in the RAM 206 of CP020 are
It may be an operation code of an instruction to be operated on in the LU unit 208 or the multiplier 210. 5C from MCPUlo
5 CPUs in the first timeslot STI of operation 2, which is the timeslot immediately before the PU access time.
20 takes out the data of the arithmetic number from the RAM 106, and loads the data into the arithmetic number latch 10 by opening TICKI.
If the 5CPU access signal from the 0MCPUl0 latched in ST2 is not generated, the 5CPU20 takes out the operand from the RAM 10B in the next time slot ST2 and latches it in the operand latch 10b, and then in the last time slot ST2) The ALU unit 108 or the multiplier 110 executes the operation and writes it to the operand register of the RAM 106.Actually, as shown in the figure, the operation is performed.
A PU access signal is generated. In this case, one solution is to change the remaining two time slots S
The process to be executed by T2 and Sr1 is suspended until the 5CPU access signal D is removed, that is, until the 5CPU access operation of MCPUIO is completed. Even with this method, MCPUIO performs operations that access 5 CPUs 20 for the shortest time (MCPUIO's internal R
Execute within the same time as accessing AM106)
However, it is not optimal for 5CPU20 and MCPUI
5C for each 5CPU access operation from O
The operation of PU 20 will be delayed by three time slots. Conveniently, the processing performed in the first time slot T1 of the 5 CPU access operations of MCPUIO is processing that does not affect SCPυ20. By utilizing this feature, in the embodiment, the MCPU
Even if 5 CPU access signals are given from IO, MC
During time slot TI of PU 10, 5 CPU 20
Allow your own operations to continue and earn 5 CP.
The operation delay of U20 is made as short as possible. 25th
In the example in the figure, 5CPU20 is 5CP of MCPUIO
First timeslot T of U data write operation
During I, the data of the operand is taken out from the RAM 206, and the clock 5T2CK1 is applied to the latch 206b to latch the operand. Thereafter, the operation of the 5CPU clock generation circuit 236 is stopped until the 5CPU access signal is removed, and the 5CPU 20 is placed in a waiting state. During this wait state, the element 128 of 5 CPU 20
．． 264.240.242 is switched to "MCPU11" by the 5CPU access signal, and 6 steps 1M regarding time slots T2 and T3 in the 5CPU data write operation of MCPUIO are executed and the data from MCPUIO is stored in mRAM 20B in 5cPU. is written.

When the 5CPU access signal from MCPUIO is removed, the 5CPU clock generation circuit 236 resumes operation and changes the clock ST3 to "H'".
By removing the PU access signal, the element 128.204.240.242 of the 5 CPU 20 is returned to "5 CPU II-", and the 5 CPU 20 itself becomes operable.

Therefore, in this time slot ST3, the 5CPU 20 converts the calculation output of the ALU section 208 or the multiplier 210 into R.
Write to AM 206 and execute the remaining part of Operation Code 2.

As shown in the time chart of Fig. 25, 5 CPU20
The amount of time the operation is interrupted for each 5 CPU access operation from MCPUIO is only two timeslots.

In addition, the MCPU 10 uses the internal RAM 20 of the 5 CPU 20.
In the case of a read access operation that reads data from 6, MCPU 10 reads data from 5 in that time slot T2.
The CPU internal RAM 206 is dressed 7 times, and the MCPU internal RAM 106 is dressed 7 times at time slot T3, and the data from the 5 CPU internal RAM 206 is taken into the MCPU internal RAM 106 via the bus gate 132.

As described above, according to the instantaneous forced access method, the MCPU
IO can access the internal RAM 206 of the 5 CPU 20 in the same way as access to the MCPU's own RAM 106 within the shortest possible time, and there is no need to execute latency instructions.

According to the instantaneous forced access method, the operation of the 5 CPUs 20 can be interrupted midway, and the operation can be resumed from the point where it was interrupted after the 5 CPU access operation of the MCPUIO. Therefore, MCPUIO is 5
There is no need to check the state of the 5CPU 20 prior to accessing the CPU 20, and the 5CP can be freely accessed at any time, for example, during the interrupt processing routine (FIG. 5).
U20 can be accessed.

Shared memory access conflict resolution function (Figs. 26, 27, and 1)> In Fig. 1, the external memory 90 is connected to multiple CPUs,
This is a data memory shared by CPUIO and 5 CPUs 20. Therefore, multiple accesses to external data memory 90, ie, external data memory 90 accesses from MCPUIO.

A means for supporting external data memory 90 access from 5 CPUs 20 is required. Furthermore, when sharing the external data memory 90, MCPUIO and 5CPU
20 and attempt to access external data memory 90 at the same time. MCPUlo and 5CP
U20 and the right to use the external data memory 90 (
By providing a function to exchange tokens), MCP
UIO and 5 CPU 20 simultaneously use external data memory 90
Although it is possible to avoid accessing the MCPUl, the token procedure occupies the preparation time for external data memory access, which increases the total time required for external data memory access, which is not efficient.
When allowing simultaneous access to the external data memory 90 by the CPUs 20 and 5, since the memory 90 itself cannot be physically accessed at the same time, a means is required to resolve access conflicts caused by simultaneous access.

In order to realize these means, as shown in Figure 1, MC
The external memory address information from the PUIO is coupled to the address input of the external memory 90 via the address bus MA, the MCPU external memory addresser, the chip 30M, the address switching circuit 40, and the address conversion circuit 60. Data output is a data conversion circuit 70,
MCPU external memory data register 80M is coupled to MCPUIO via data bus MD. On the other hand, 5
External memory address information from the CPU 20 is transmitted through the address bus SA, the 5CPU external memory address switch 305, the address switching circuit 40, and the address change II! The data output from the external memory 90 is coupled to the address input of the external memory 90 via the circuit 60, and the data output from the external memory 90 is connected to the data conversion circuit 7.
0. The SCPU external memory data latch 80S is coupled to the 5CPU 20 via the data bus SD. Then, signals MCPU-roma and SCP representing an external data memory access request from MCPUIO and 5CPU20 are transmitted.
The memory device conflict avoidance circuit 50 receiving U-roma causes the MCPU external memory address latch 30M to:
SCPU external memory address switch 30S, address switching circuit 40, MCPU external memory data latch 80
M, SCPU external memory data latch 80S is controlled. This memory device conflict avoidance circuit 5° includes a function to avoid the above-mentioned access conflict.

FIG. 26 shows a block diagram of the memory device conflict avoidance circuit 50, and FIG. 27 shows a time chart of operations regarding access conflicts.

In FIG. 26, the memory device contention avoidance circuit 50 receives an access request signal MCPU from MCPUIO as an input.
-roma, access request signal SC from 5 CPU 20
PU-roma, plus 1 MCPU reset signal MRES
and 5CPU reset signal 5RESC (not shown in FIG. 1) are combined with 0MCPU reset signal MRES
is set-reset circuit (R-S flip-flop) 50
2 and its output, and the signal MCPU-roma sets the set-reset circuit 502. The set reset circuit 502 temporarily stores the access request from MCPUlo, and the output side set reset circuit 506 stores the access request from MCPUlo in the set state.
Similarly, the 5CPU reset signal 5RES is sent to the set reset circuit 504 and its output, indicating that the access request from PUlo has been accepted and the access operation is being executed via the external memory data access control signal generation circuit 510. Coupling set-reset circuit 508
The signal 5CPU-roma sets the set-reset circuit 504. Set reset circuit 50
4 temporarily stores the access request from the 5 CPU 20, and the output side set reset circuit 508 stores the access request from the 5 CPU 20 in the set state.
This indicates that the access request from the CPU 20 has been accepted and the access operation is being executed.

In detail, the output “H” of the set state of the MCPU access request set reset circuit 502 is provided on the condition that the 5 CPU access execution set reset circuit 508 is not in the set state, that is, the access operation command of the 5 CPU 20 is not being executed. (value input is 5)
A signal that sets the MCPU access execution cycle 506 to the MCPU access execution state (via the ANa gate) 524 which is coupled to the inverting input via the inverter 522 from 08; By OR game) 512
MCPU access request set reset circuit 502 (value input is coupled to reset signal MRES). Similarly, the output “H” in the set state of the 5 CPU access request set reset circuit 504 is set on the condition that the MCPU access execution set reset circuit 506 is not in the set state, that is, on the condition that no MCPUIO access operation is being executed (value Sets the 5 CPU access execution set reset circuit 508 to the 5 CPU access execution state through an AND gate 526 ), one of whose inputs is coupled to an inverting input from 506 via an inverter 520; OE game
) 516 (value input is coupled to reset signal 5RES) 5 CPU access request set reset circuit 5
By configuring 0 or more to reset 04, one CPU
Even if there is an access request from (for example, 5 CPU 20),
When an access operation regarding the other CPU (MCPUlo) is being executed, the access operation regarding the CPU (SCPU20) that requested access will not be executed until the execution is completed.
Access conflicts are basically avoided.

Furthermore, MCPUIO and 5 CPUs 20 may request access completely simultaneously. In response to this access conflict, in the embodiment, priority is given to the access request from MCPUIO, and after the access operation of MCPUlo is executed, the access operation command of 5 CPUs 20 is executed. For this reason, when the 1MCPU7 access request set reset circuit 502 is in the set state, its output signal "
H'' to IN - AND gate 52 via E 525
6 is prohibited, and the set reset circuit 502 is setting the CPU access request set reset circuit 5.
Even if 04 is set, the 5cPU access execution set reset circuit 508 is prevented from being set.

The external memory data access control signal generation circuit 51O is
is coupled to the outputs from set-reset circuits 506 and 508 such that the output of either set-reset circuit is in the set state "
When it changes to "H", the CPU access operation indicated by the set state is executed in a series of sequences.Signals CE and OE output from the external memory/memory data access control signal generation circuit 510 output data from the external memory 7. The signal MDL is a control signal for MCPU
This is a control signal for latching data from the external memory 90 into the external memory data latch 80M, and the signal SDL
is a control signal for latching data from the external memory 90 into the 5CPU external memory data latch 80S.

When the external memory data access control signal generation circuit 510 finishes executing the access operation, it generates EH11. This EH11 resets the access execution set reset circuit that was in the set state. That is, EH11 has an AND gate 528 whose value input is coupled to the output of the set/reset circuit 506 and a value input which is coupled to the MCPU.
A value input is coupled to the reset input of the set-reset circuit 506 via an OR gate 514 that is coupled to the reset signal MRES, and an AND gate 530 whose value input is coupled to the output of the set-reset circuit 508 and a value input is coupled to the 5CPU reset signal 5RES. It is coupled to the reset input of the set/reset circuit 508 via an OR gate 518 .

The output of the 5CPU access execution set reset circuit 508 is sent to the address switching circuit 40 via the inverter 532.
An address selection signal MSEL is generated for the address selection signal MSEL. Therefore, the address switching circuit 40 performs access operations for the five CPUs 20.

When the program is running, select the 5CPU address from the 5CPU external memory access address check 305,
In other cases, the MCPU address from the MCPU external memory access address latch 30M is selected.

@27W (7) 11 go, MCPUI O and 5CPU20
is "MCPU operation roma"5C
As shown in roma'' in the PU operation instruction, access to the external memory 90 is requested at the same time.In the operation of this roma instruction, the MCPUI
O sends address information to the address bus MA, and the signal M
CPU-roma is output to cause the address latch 30M for MCPU external memory access to latch the address information, and similarly, the 5CPU 20 sends address information to the address bus SA, outputs the signal SCPU-roma, and latches the address information to the MCPU external memory access address latch 30M.
The address information is latched by the address switch 303 for U external memory access. MCPU-ro occurring at the same time
The MCPU access request set reset circuit 502 and the 5CPU access request set reset circuit 504 of the memory device conflict avoidance circuit 50 are simultaneously set by the ma signal and the SCPU-roma@ signal. In response, according to the MCPU access priority logic described above, the MCPU access execution set reset circuit 506 immediately changes to the set state, and thereby the external memory data access control signal generation circuit 510 executes the MCPUIO access operation to the external memory 9o. . At this point, the address switching circuit 4o has selected the address information from MCPUIO. MCPUlo access operation 1
The period of 27th v! Indicated by the period sentence to the left of J (in addition,
The circuit 510 uses a two-phase master clock CK1. It works on CK2, but the 26th rI! (Illustrations are omitted in J)
, the external memory data access control signal generation circuit 510 makes the chip enable signal CE active low during period n, and makes the output enable signal OE active low during period m, which is the latter half of period n. Therefore, during this period m, the data requested by the MCPUIO is output from the external memory 90, and this output data is transferred to the MCPU external memory data latch 80M by the signal MDL generated from the external memory data access request signal generation circuit 510 within this period m. Latched. As a result, the access operation for MCPUIO of the external memory data access request signal generation circuit 510 is completed, and the circuit 51O outputs the end signal END. As a result, the 1MCPU7 access execution set reset circuit 506 is reset and the 5cPU access execution set reset circuit 508 is set instead. As a result, the signal MSEL changes to L'' level indicating selection of the 5 CPU address, and the address switching circuit 40 selects the address from the 5 CPU 20 and dresses the external memory 90. External memory data access 8111M number generation circuit 5 in response to the set signal of
10 performs access operations for 5 CPUs 20. This period is shown in the period view on the right side of 27th g.
In this operation, the external memory data access control signal generation circuit 510 makes the signal CE low active, and in the latter half period p, makes the signal OE low active to output the data requested by the 5 CPU 20 from the external memory 90, and during the output. Generates signal SDL and sends it to SCPU
The external memory data latch 803 is made to latch the data requested by the 5 CPU 20. As a result, the access operation for the 5 CPUs 20 of the external memory data access control signal generation circuit 510 is completed.
0 outputs the end signal END and returns the 5CPU7 access execution set reset circuit 508 to the reset state.

After this, MCPUIO and 5CPU 20 can obtain the requested data by reading the output data of external memory data latches 80M and 805 on data buses MD and SD, respectively.

In this way, each CPU10.20 executes the roma instruction (
After executing an external memory access request instruction).

If the memory device contention avoidance circuit 50 waits for a predetermined period of time for executing access operations for both CPUs, the requested data can be obtained, and the problem of access contention is resolved. Furthermore, the waiting time is constant (2!l) S1
7) Te, each CPUIO 5z0 can use this period to execute other instructions, and the execution efficiency of program instructions is optimized.

In addition, the MCPU-roma signal and the SCPU-roma@
Cases where the timing relationship of the number is other timing relationships are omitted from illustration, but in any case, after each CPU10.20 executes the Roma instruction, if it waits for two sentences for a predetermined period, each CPU has already executed the Roma instruction. Since the requested data is latched in the external data latch, the data can be obtained.

address/data conversion hardware (28th to 32nd
FI! J, trl! J)> Generally, in a microcomputer system including a CPU, it is often desired to create data (desired information extracted from W data) by converting the original data onto the calculation memory from the original data in the data memory. . Particularly for this type of data, conversion is necessary to compensate for efficient use of the storage capacity of the data memory. For this purpose, conventionally, a transfer instruction from the data memory to the calculation memory is executed to move the original data in the data memory to the calculation memory, and then one or more conversion instructions are executed to transfer the original data from the data memory to the calculation memory. Converts the data in the ALU via the ALU. Therefore, in the conventional case, the data conversion procedure to obtain the desired data on the calculation memory takes time;
This is one of the obstacles in applications that require high-speed processing.

In this embodiment, the CPUs 10 and 20 are connected from an external memory 90 which is a data memory to an internal RAM 106 which is a calculation memory.
Alternatively, simply by executing an instruction (roma instruction) to transfer data to the RAM 206, data that has been subjected to desired conversion is read into the internal RAM 106.206, thereby speeding up data conversion processing. To achieve this purpose, an address conversion circuit 60 is provided on the address path between CPU10.20 and the external memory 90, and a data conversion circuit 70 is provided on the data path between the external memory 90 and CPU10120. and each conversion circuit 60.
70 is CPU10120 when executing r o m a instruction.
performs the desired conversion in response to control signals provided by the converter.

FIG. 28 shows a list of external memory access instructions roma. The first instruction romao is a transfer instruction without conversion, whereas the address translation circuit 60
．． The input address given from the external data memory 90 is directly passed to the external data memory 90 as an output address, and the data conversion circuit 70 also passes the data from the external data memory 90 (16bee/2 data) without conversion and passes it to the CPU 10120.

In this non-conversion transfer instruction romao, the conversion control signal R given from the CPU 10°20 to the conversion circuit 60.70
1, R2, and R3 are all at the "L" level.

The second instruction romal is an instruction suitable for reading a special waveform. In response to this instruction, the address conversion circuit 60
The 13th input address sent from PUl0120
When bit A12 is "0", the lower 12 bits are passed through without conversion, but when the 13th bit A12 is 1", the lower 12 bits are inverted. Note that the 13th bit of the output address of the address conversion circuit 60 is It is fixed at "θ" regardless of the value of the 13th bit AI2 of the input address.

In addition, in response to this instruction, the data conversion circuit 70
The 13th bit A12 of the input address sent from 0120 is set as the 13th bit D12 of the data sent to CPU 10120, and when A12 is "1", the lower 12
The data from the external memory 90 is converted in a format that inverts the bit data. Therefore, special waveform data (o o o) having 12 effective data bits as shown in FIG. 28 is stored in the address area oooo to 0FFF of the external memory 90.

~0FFF), when the CPU10120 repeatedly executes this instruction for the specified address range 0000-IFFF, the external memory address output from the address conversion circuit 60 will once change from 0000 to 0.
During this time, the data conversion circuit 70 passes the data from the external memory 90 as is, and then, due to the inversion operation of the address conversion circuit 60, the address to the external memory 90 advances from 0FFF to oooo, and during this time, the data conversion circuit 70 passes the data from the external memory 90 as is. The circuit 7o inverts the lower 12 bits of the data output from the external memory 9o, and outputs the 13th data bit) D12.
is set to "l" and the converted data is output. In the end, C
PUl0120 moves the address from oooo to IFFF and executes the instruction r.

When m a 1 is repeatedly executed, CPUl012
The waveform that 0 actually takes is the waveform shown on the right side of the ROMAL column in FIG. This converted waveform is a repetitive waveform (a waveform that is symmetrical about the address 0FFF and data 0FFF points) obtained by extending the original waveform in the external memory 90 shown on the left in a predetermined manner.As a result, in terms of storage capacity, This method has the advantage that the waveform data storage capacity is halved compared to a method in which the converted waveform data itself is stored in advance in the external data memory 90. In the case of this command romal, only R1 of the control signals R1, R2, and R3 is “H”
level.

The third instruction ROMA2 is a part of external memory data (half M
) is an instruction to read. For this command,
Only R2 becomes "H" level.

The storage capacity of one address (one word) of external data memory 90 is 16 bits. For this command roma2,
When the 16th bit A15 of the address from the CPU 10120 is "O", the data conversion circuit 70 leaves the lower 8 bits of the 16 bits from the external data memory 90 and sets the upper 8 bits to "0". When A15 is “l”, the external data memory 9 is
Shift the upper 8 bits of 0 to 16 bit data to the lower 8 bits (remaining upper 8 bits are masked)
Perform the conversion. Furthermore, since the data conversion circuit 70 uses the 16th bit A15 of the input address as a control signal, the 1-address conversion circuit 60 sets the 16th beat 7 of the output address to a predetermined value '0' regardless of the value of A15.
In this case, the relationship between the upper 8 bits and the lower bits of the 16-bit information from the external data memory 90 is that the upper data part (for example, the integer part) and the lower It may be a relationship such as a data part (for example, a decimal part), or an independent relationship such as a relationship between 8-bit data of different zli classes (for example, rate data and level data).

The fourth instruction ROMA3 is an instruction to shift external memory data and read a part of it. In the case of this instruction, only R3 becomes "H" level. In response to this command, the data conversion circuit 70 converts the 16-bit data from the external memory 90 into
Leave bft15 as is and use bit1 of the upper 12 bits.
Shift bits 5 to 4 to bits 14 to 3, and perform conversion to mask the lower 3 bits bits 2 to 0 to 0. Here, of the 16 bits of data in the external memory 90, the upper 12 bits, for example, set bit 15 as the sign bit. waveform data, and the lower 4 bits represent other data. In this case, the above conversion allows CPU 10.20 to quickly read waveform data in a format suitable for use on internal RAM 106.206. .

FIG. 29 shows a block diagram of the address conversion circuit 60.
This address conversion circuit 60 includes MCPUlo or 5C.
Of the 16-bit address input from the PU 20 via the address bit 2,30M, 3O3, and the address switching circuit 4o, the lower 12 bits are
ll) is input to an inverting circuit 610 whose details are shown in FIG. This inverting circuit 610 receives the signal R1 as the command romal.
When A12 of the address is “l”, AN
It is operated by a signal from the D-game) 612 and inverts the lower 12 bits of the input address. Also, the instruction ro
The signal R1 that becomes “l” when mal is executed is the inverter 6.
02 of the input address, which inhibits the AND gate 604 and makes the corresponding beat 2 (bft12) of the output address "0" regardless of the value of A12 of the input address.
l1 and A14 are the corresponding output addresses, )(
bit13, bft14). A15 (MSB) of the input address is passed through the AND gate 608 and becomes the corresponding bit (bit15) of the output address.When a signal R2 of "L" indicating that the instruction roma2 is being executed is generated, this signal R2 is output to the inverter. 606 to disable AND gate 608 and bit 1 of the output address
Mask 5 (MSB) to “0”.

Therefore, the address conversion circuit 60 converts the non-conversion instruction ROM
R1= for aO and shift read instruction roma3
"0", R2="0", so the input address is passed as an output address and the special waveform read command romal is executed.
For R1=“l”, bit 1 of the output address
2 to "θ", A12 = "l" scale rotation circuit 6
10 indicates the lower 12 bits of the input address.

~bitll) is inverted and used as the output address.

Furthermore, for the partial read instruction 1 o m a 2, since R2="1", the output address bft15 is set to "0".
to mask. In this way, the function of the address conversion circuit described in FIG. 28-d is realized.

FIG. 31 shows a block diagram of the data conversion circuit 70, and FIG. 32 shows its details. In these figures, data input is data supplied from the external memory 90 of FIG. In FIG. 32, a 3-state gate circuit 702 coupled to the upper 8 bits of input data and a 3-state gate circuit 704 coupled to the lower 8 bits of the input data output the lower 8 bits of the input data. The upper 8 bits are selected, but this is for determining whether to select the lower 8 bits of input data. R2=“l”(r o m a
2 instructions) - When t'A15=1, AND gate 70
6's "l" output signal and its inverted signal, inverter 7.
In response to the output signal "0" of 08, the gate circuit 702 becomes conductive, the gate circuit 704 turns off, and the upper 8 bits of the input data are selected as the lower 8 bits of the output data. In other cases, the gate circuit 702 is turned off and the gate circuit 704 is turned on, so that the lower 8 bits of the input data are directly output as the lower 8 bits of the output data. Furthermore, when R2 = "1" (r o m a 2 instruction), the AND gate circuit 710 that connects to the upper 8 bits of the input data is inhibited, and the upper 8 bits of the output data are
In other words, when R2="1", the inhibit signal is masked to A through the inverter 712 and the NOR gate 714.
AND gate circuit 71 in addition to ND gate circuit 71O
Passage of the upper 8 bits of input data at 0 is blocked. Furthermore, the AND gate element connected to the upper 3 bits of the input data in the AND gate circuit 710 has R1="l".
” (romal instruction), it is inhibited via the NOR gate 714, and the upper three bits of the output data are masked to “O”.

The EX-OR gate circuit 716 is a circuit for selectively inverting the lower 12 bits of input data.
R gate circuit 716 has R1="1" (romal instruction)
When A12=1, the lower 12-bit data is inverted by the inversion signal "l" from the AND gate) 718, and in other cases, it is passed through the AND gate element in the 0 circuit 710, which passes the lower 12-bit data as is. b of the input data
The state gate 722 coupled to it12 is R1="work" (
romal instruction) and S are turned off by the signal "0" applied via the inverter 720 coupled to the signal R1, and instead, the three-state gate 724 coupled to A12 is made conductive by the signal R1 to output bit 12 of the output data. occurs. The shift mask circuit 726 selectively converts bits 15 to 4 of the input data into bits 14 to 4 of the output data.
Shift to bit3, bit2 to bit10 of output data
This is a circuit to mask R3=“1” to “0”.
(roma3 instruction) and the signal "l" from inverter 728 coupled to S@signal R3 performs this conversion.

Therefore, the data conversion circuit 70 converts the non-conversion instruction ROM
ao (R1=R2=R3=“0”), the input 16-bit data is passed through as is, and when the special waveform read command romal (R1=“1”), the upper 4 bits of the input address (bits 15 to 15) are passed through. bit12) is “0”
000" (when A12=O) or "0001" (A1
2=l), the lower 12 bits of the output data are used as the lower 12 bits of the input data (A1
2=O and S), or convert the lower 12 bits of the output data into data in which the lower 12 bits of the input data are inverted (A12=1), and issue a partial read command roma2( R2-“1”), the upper 8 bits of the output data are all zeros, and the lower 8 bits of the output data are the lower 8 bits of the input data (A15).
= O), or convert the data so that the upper 8 bits of the output data are all zeros and the lower 8 bits of the output data become the upper 8 bits of the input data (when A15 = 1), and shift read. Instruction roma3 (R3=1)
When , the lower 3 bits of the output data (bjto"bit
2) is all zero, and bit3 to bft1 of the output data
4 is bit 4 to bit 15 of input data, and bit 15 (MSB) of output data is bit 15 of input data.
In this way, the data conversion function described in FIG. 28 is achieved.

As described above, the address conversion circuit 60 and the data conversion circuit 7
The advantage of providing 0 is obvious. That is, C
For the PUl0120, just by executing the access command r o m a to the external memory 90, which is a data memory, the conversion functions of the circuits 60 and 70 can immediately obtain data that has undergone the desired conversion. After the data in the external memory 90 is loaded into the internal RAM 106.206, which is the calculation memory,
There is no need to perform conversion via an ALU such as the LU unit 108.208, which has the advantage of speeding up processing.

Note that the list of access commands roma shown in FIG. 28 is merely an example, and can be easily expanded and modified.

<DAC Sampling (!33.M34)> In this embodiment, the DAC 100 converts the digital musical tone signal generated by the MCPUIO and the 5 CPU 20 into an analog musical tone signal. As shown in 5-5 in Figure 5, the MCPU
IO is performed by MC in the timer interrupt processing routine.
A sample of the digital musical tone signal generated by the PUIO and the 5CPU 20 is set in the DAC 100. This process 5-5
The average execution interval of timer interrupt generator 1 is
16, but the actual execution interval varies due to program operations. Therefore, if D/A conversion is performed using the execution interval of process 5-5 as the conversion period of D/A conversion, a large distortion will occur in the analog musical tone signal.

FIG. 33 shows an example of the configuration of the right DAC 100R or the left DAC 100L. In the configuration shown in FIG. 33(A), when processing 5-5 is executed, the internal The waveform addition register in the RAM 106 is designated, and the latest digital musical tone data stored therein is taken out and placed on the data bus.

Then, at the timing when the digital musical tone data is on the data bus, a strobe program control signal is input to the clock input of the latch 1004 to the operating control circuit 1.
12 and the data on the data bus is set,
New digital musical tone data from latch 1004 is D/A
It is input to converter 1002. Therefore, the 34th rI
! As shown in J(A), the digital musical tone data input to the D/A converter 1002 is switched at an unstable cycle due to program control. D/A converter 10
If the conversion period (sampling period) of 02 is not very stable, large distortions will occur in the conversion.

This problem can be solved by adopting a configuration as shown in FIG. 33(B). That is, between the soft control latch 1004 controlled by the program control signal from the operation control circuit 112 and the D/A converter 1002 that converts the digital musical tone signal into an analog musical tone signal,
An interrupt control latch 1006 is provided which is controlled by an interrupt signal INT, which is a precise timing signal from the interrupt generator 116. The generation period of the interrupt signal follows the stability of the clock oscillator, so it is extremely stable. The output of the latch 1006 is switched at the timing of the interrupt signal. That is, the generation cycle of the interrupt signal becomes the conversion (sampling) cycle of the D/A converter 1002. The timing chart for the configuration of FIG. 33(B) is shown in FIG. 34(B), and as shown in FIG. A latch 1006 that operates with an interrupt signal, although it varies depending on the time fil (length of the shaded part).
Therefore, the timing at which the input data of the D/A converter 1002 switches is synchronized with the interrupt signal. This solves the distortion problem in the configuration of FIG. 33(A).

[Modifications] This concludes the description of the embodiments, but various modifications and changes can be made without departing from the scope of the present invention.

The present invention relates to parallel processing technology in a digital microcomputer having multiple CPUs. Therefore, the application (electronic musical instrument in the embodiment) to which this digital microcomputer is applied is not particularly limited.

Furthermore, there are no restrictions on the content of processing shared by each CPU for parallel processing and the mode of sharing.

Further, in the embodiment, the processing shared by each CPU for parallel processing is based on the execution result of the main program of the main CPU, and is the processing assigned from the main program. Alternatively, the processing to be shared by each CPU may be processing that does not use the execution results of the main program, that is, processing that is independent from the processing of the main program.

In addition, in the embodiment, the sub CPU is in a stopped state when it is not executing the shared processing of parallel processing, but it may be configured to execute other processing (processing by another main program) depending on the application. In this case, the sub CPU responds to a signal from a parallel processing start signal generating means such as the interrupt control unit 116, interrupts the main program (other than the above) that is being executed, and performs the shared processing of the parallel processing. Shifts to the mode that executes the interrupt handling routine for
After the shared processing is completed, the interrupted main program is restarted. This type of configuration is applicable when the main program processing executed by the main CPU and the main program processing executed by the CPU are independent.1 For example, the processing results of the main program executed by the main CPU (7) are sent to each CPU.
This is particularly effective when the sub CPU is used for parallel processing executed in an interrupt processing routine, but the processing results of the main program of the sub CPU do not affect the processing of any other programs. In such an environment, for example, the internal memory of the sub CPU is divided into two, one internal data memory is used for processing the main program of the sub CPU, and the other internal data memory is used for processing from the main program of the main CPU. Used to write results and sub-C
Sub C
Two access paths are provided, one for the PU and one for the main CPU.
In a mode in which the sub CPU executes the main program, the access path from the main CPU is used as the access path to the other internal data memory, and in a mode in which the sub CPU executes an interrupt processing routine, the access path to the other internal memory is used. as sub CPU
By using the access path from the sub-CPU, the sub-CPU can execute the main program of the sub-CPU without interrupting the other internal memory access operation by the main program of the main CPU, resulting in more efficient operation. is guaranteed.

In addition, in the embodiment, the microcomputer obtains the parallel processing start signal from the interrupt generation section 116, but for example, it may be applied to an application where the parallel processing start signal is received from an input wave W external to the microcomputer (for example, from another microcomputer). This invention can also be applied to.

It has possible advantages, etc.

[Effects of the Invention] Finally, the effects and advantages of the invention described in the claims will be described.

According to claim 1, a plurality of CPUs simultaneously start their assigned processing in response to the parallel processing start signal, thereby achieving the highest possible level of parallelism and significantly improving the performance of the digital microcomputer. . The configuration of claim 1 is suitable for applications that require periodic large amount of data processing (which may include input/output processing), or for processing large amounts of data within a limited time from the occurrence of an event due to changes in the environment. Particularly suitable for applications that must be carried out.

In addition, the configuration of claim 2 is particularly suitable for applications that periodically process a large amount of data, and also has the advantage that it can minimize accesses between CPUs that cause a decrease in system operating efficiency. All C by program
Unified control of PU

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of a processing device for an electronic musical instrument to which the present invention is applied, Fig. 2 is a block diagram of the MCPU shown in Fig. 1, Fig. 3 is a block diagram of the 5 CPUs of the 1FgJ, and Fig. 4 is a block diagram of the 5 CPU of the 1FgJ. Figure 5 is a flowchart of the main program executed by the MCPU, Figure 5 is a flowchart of the interrupt processing routine executed by the MCPU, Figure 6 is a flowchart of the program executed by the 5CPU, Figure W117 is a flowchart of sound source processing, Figure 8 is the passage of time. Figure 9 is a flowchart of channel sound source processing, Figure 1θ is a diagram showing waveform data, Figure 11 is a diagram showing a RAM table for sound source processing, and Figure 12 is a diagram showing the start and end of 5 CPU operation. Figures 13, 14, and 15 are time charts of the operation of the circuit in Figure 12. Figure 16 is a block diagram of a circuit with an interrupt mask function. Figure 17 is a block diagram of a circuit related to the function. A flowchart of envelope setting processing using the interrupt mask method. Figure 18 is a block diagram of a circuit that has a function to prohibit interruption of the main program due to an interrupt signal while multiple data are transferred by a single command. Figure 19 is a block diagram of a circuit that has a function to prevent interruption of the main program by an interrupt signal while multiple data are transferred by a single instruction. FIG. 20 is a diagram showing an example of a memory map of a RAM suitable for transferring data using a single instruction. FIG. 20 is a diagram showing a comparison between operations using a plurality of transfer instructions and operations using a single transfer instruction. Figure 21 is a flowchart of envelope setting processing using the single transfer command method, Figure 22 is a flowchart used to explain the 5CPU7 access function from the MCPU using the 5CPU stop mode, and Figure 23 is instantaneous forced access to 5CPUs. Figure 24 is a block diagram of 5 CPUs that are compatible with the instantaneous forced access function for SCPυ, and Figure 1425 is a block diagram of the internal RAM of 5 CPUs from MCPU.
Figure 26 is a time chart of the operation when writing data to the memory device conflict avoidance circuit shown in Figure 1.
Figure 27 is a time chart of the operation of the circuit in Figure 26, Figure 28 is a diagram showing a list of external memory access instructions including instructions to convert and import data from external memory, @291gI is the first 30 is a block diagram of the address conversion circuit shown in FIG. 29, FIG. A block diagram of the data conversion circuit of J, Figure 1432 is a circuit diagram of the data conversion circuit, and Figure 33 is a block diagram of the data conversion circuit of M4.
FIG. 2 is a diagram showing a comparison between a configuration in which the sampling period of the DAC shown in FIG. 1 is unstable and a configuration in which the sampling period is stabilized; FIG. 34 is a diagram showing a comparison of a time chart when the sampling period of the DAC is unstable and a time chart when the sampling period is stable.

Claims (2)

[Claims] (1) A plurality of CPUs, a parallel processing start generation means for generating a parallel processing start signal, and a predetermined processing execution mode in which each CPU shares the mode of each CPU in response to the parallel processing start signal. A CPU that performs switching control to realize parallel processing by the plurality of CPUs.
A digital microcomputer comprising: U mode control means. (2) a main CPU containing a main program and an interrupt processing routine; and at least one sub-CPU containing a program for executing processing assigned by the main program of the main CPU; an interrupt generating means for generating an interrupt signal; and a mode for interrupting the main program being executed in the main CPU and executing the interrupt processing routine in response to the interrupt signal.
main CPU mode control means for controlling switching of a mode of a PU and returning the mode of the main CPU to a mode in which the main program is executed again in response to completion of execution of the interrupt processing routine; a sub-C that controls switching of the mode of the sub-CPU from a stopped state to a mode that executes the program, and controls the mode of the sub-CPU to return to the stopped state in response to completion of execution of the program;
A digital microcomputer comprising: PU mode control means;