JPH0459686U - - Google Patents
Info
- Publication number
- JPH0459686U JPH0459686U JP10326590U JP10326590U JPH0459686U JP H0459686 U JPH0459686 U JP H0459686U JP 10326590 U JP10326590 U JP 10326590U JP 10326590 U JP10326590 U JP 10326590U JP H0459686 U JPH0459686 U JP H0459686U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- input
- input level
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229940028444 muse Drugs 0.000 claims description 7
- GMVPRGQOIOIIMI-DWKJAMRDSA-N prostaglandin E1 Chemical group CCCCC[C@H](O)\C=C\[C@H]1[C@H](O)CC(=O)[C@@H]1CCCCCCC(O)=O GMVPRGQOIOIIMI-DWKJAMRDSA-N 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000003321 amplification Effects 0.000 claims 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Television Receiver Circuits (AREA)
- Color Television Systems (AREA)
- Television Systems (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
各部の波形を示す図、第３図はアツプダウン信号
の出力回路の一例を示す図である。
１２……可変増幅回路、Ａ……ＭＵＳＥ信号、
Ｂ……ＭＵＳＥ信号、Ｅ……ダウン信号（入力レ
ベル判定信号）、Ｆ……アツプ信号（入力レベル
判定信号）、２０……ＭＵＳＥ信号処理回路、２
６……アツプダウンカウンタ、２８……Ａ／Ｄ変
換器（変換回路）、Ｊ……可変抵抗制御信号（制
御信号）、Ｄ……フレームパルス（一定周期パル
ス信号）、１８……可変抵抗回路。
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing waveforms of various parts, and FIG. 3 is a diagram showing an example of an up-down signal output circuit. 12...Variable amplifier circuit, A...MUSE signal,
B...MUSE signal, E...Down signal (input level judgment signal), F...Up signal (input level judgment signal), 20...MUSE signal processing circuit, 2
6...Up-down counter, 28...A/D converter (conversion circuit), J...variable resistance control signal (control signal), D...frame pulse (constant period pulse signal), 18...variable resistance circuit .
Claims (1)
号Ａを増幅する可変増幅回路１２と、この可変増
幅回路１２の出力Ｂのレベルが、「大」「小」で
あることを示す入力レベル判定信号Ｅ，Ｆ及び一
定周期パルス信号Ｄを出力する回路２０とを有す
るＭＵＳＥ信号入力レベル制御回路に於いて、 前記入力レベル判定信号Ｅ，Ｆによりダウン又
はアツプされるアツプダウンカウンタ２６と、 このアツプダウンカウンタ２６の出力をアナロ
グ信号に変換する変換回路２８と、 この変換回路２８からの制御信号Ｊにより前記
可変増幅回路１２の増幅度を制御する可変抵抗回
路１８と、 を備えるＭＵＳＥ信号入力レベル制御回路。 (2) ＭＵＳＥ信号を入力信号として、該入力信
号Ａを増幅する可変増幅回路１２と、この可変増
幅回路１２の出力Ｂのレベルが、「大」「小」で
あることを示す入力レベル判定信号Ｅ，Ｆ及び一
定周期パルス信号Ｄを出力する回路２０とを有す
るＭＵＳＥ信号入力レベル制御回路に於いて、 前記入力レベル判定信号Ｅ，Ｆと前記一定周期
パルス信号Ｄのアンド出力によりダウン又はアツ
プされるアツプダウンカウンタ２６と、 このアツプダウンカウンタ２６の出力をアナロ
グ信号に変換する変換回路２８と、 この変換回路２８からの制御信号Ｊにより前記
可変増幅回路１２の増幅度を制御する可変抵抗回
路１８、 を備えるＭＵＳＥ信号入力レベル制御回路。[Claims for Utility Model Registration] (1) A variable amplifier circuit 12 that uses the MUSE signal as an input signal and amplifies the input signal A, and that the level of the output B of this variable amplifier circuit 12 is "high" or "low". In a MUSE signal input level control circuit having input level determination signals E, F indicating that there is a A down counter 26, a conversion circuit 28 that converts the output of the up/down counter 26 into an analog signal, and a variable resistance circuit 18 that controls the amplification degree of the variable amplifier circuit 12 using a control signal J from the conversion circuit 28. A MUSE signal input level control circuit comprising: (2) A variable amplifier circuit 12 that uses the MUSE signal as an input signal and amplifies the input signal A, and an input level determination signal that indicates whether the level of the output B of the variable amplifier circuit 12 is "high" or "low". In a MUSE signal input level control circuit having a circuit 20 that outputs E, F and a constant period pulse signal D, the input level determination signal E, F and the constant period pulse signal D are output by an up-down counter 26, a conversion circuit 28 that converts the output of this up-down counter 26 into an analog signal, and a variable resistance circuit 18 that controls the amplification degree of the variable amplification circuit 12 using a control signal J from this conversion circuit 28. , A MUSE signal input level control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990103265U JP2550995Y2 (en) | 1990-09-28 | 1990-09-28 | MUSE signal input level control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990103265U JP2550995Y2 (en) | 1990-09-28 | 1990-09-28 | MUSE signal input level control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0459686U true JPH0459686U (en) | 1992-05-21 |
| JP2550995Y2 JP2550995Y2 (en) | 1997-10-15 |
Family
ID=31848074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990103265U Expired - Fee Related JP2550995Y2 (en) | 1990-09-28 | 1990-09-28 | MUSE signal input level control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550995Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6220406A (en) * | 1985-07-19 | 1987-01-29 | Nec Home Electronics Ltd | Automatic gain controller for muse system |
| JPS62165415A (en) * | 1986-01-17 | 1987-07-22 | Matsushita Electric Ind Co Ltd | Automatic gain control circuit |
-
1990
- 1990-09-28 JP JP1990103265U patent/JP2550995Y2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6220406A (en) * | 1985-07-19 | 1987-01-29 | Nec Home Electronics Ltd | Automatic gain controller for muse system |
| JPS62165415A (en) * | 1986-01-17 | 1987-07-22 | Matsushita Electric Ind Co Ltd | Automatic gain control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2550995Y2 (en) | 1997-10-15 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |