JPH0375678U - - Google Patents
Info
- Publication number
- JPH0375678U JPH0375678U JP13488889U JP13488889U JPH0375678U JP H0375678 U JPH0375678 U JP H0375678U JP 13488889 U JP13488889 U JP 13488889U JP 13488889 U JP13488889 U JP 13488889U JP H0375678 U JPH0375678 U JP H0375678U
- Authority
- JP
- Japan
- Prior art keywords
- level
- synchronization signal
- detection circuit
- circuit
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 6
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は、この考案による映像信号のオートゲ
インコントロール回路の一実施例を示す回路図、
第２図は第１図の実施例における回路各部の信号
波形図である。
２…同期信号検出回路、３ａ，３ｂ…遅延回路
、４ａ，４ｂ…サンプルパルス発生回路、５ａ，
５ｂ…サンプルホールド回路、６…差動増幅器、
７…Ａ／Ｄ変換器、８…マルチプレクサ、９…演
算増幅器。
FIG. 1 is a circuit diagram showing an embodiment of an automatic gain control circuit for video signals according to this invention;
FIG. 2 is a signal waveform diagram of each part of the circuit in the embodiment of FIG. 1. 2... Synchronization signal detection circuit, 3a, 3b... Delay circuit, 4a, 4b... Sample pulse generation circuit, 5a,
5b...sample hold circuit, 6...differential amplifier,
7... A/D converter, 8... Multiplexer, 9... Operational amplifier.
Claims (1)
路と、 前記同期信号検出回路で検出された同期信号の
ボトムレベルとペデスタルレベルを検出するレベ
ル検出回路と、 前記レベル検出回路で検出された前記ペデスタ
ルレベルとボトムレベルの差を同期信号レベルと
して出力する同期信号レベル検出回路と、 前記同期信号レベルに基づいて、前記映像信号
を増幅する増幅器の利得を調整する利得調整回路
と、 を備えて成ることを特徴とする映像信号のオート
ゲインコントロール回路。[Claims for Utility Model Registration] A synchronization signal detection circuit that detects a synchronization signal of a video signal; a level detection circuit that detects a bottom level and a pedestal level of a synchronization signal detected by the synchronization signal detection circuit; and the level detection circuit. a synchronization signal level detection circuit that outputs the difference between the pedestal level and the bottom level detected by the circuit as a synchronization signal level; and a gain adjustment circuit that adjusts the gain of an amplifier that amplifies the video signal based on the synchronization signal level. An automatic gain control circuit for a video signal, comprising: and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13488889U JPH0375678U (en) | 1989-11-22 | 1989-11-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13488889U JPH0375678U (en) | 1989-11-22 | 1989-11-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0375678U true JPH0375678U (en) | 1991-07-30 |
Family
ID=31682192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13488889U Pending JPH0375678U (en) | 1989-11-22 | 1989-11-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0375678U (en) |
-
1989
- 1989-11-22 JP JP13488889U patent/JPH0375678U/ja active Pending