JPH033827U - - Google Patents
Info
- Publication number
- JPH033827U JPH033827U JP6336089U JP6336089U JPH033827U JP H033827 U JPH033827 U JP H033827U JP 6336089 U JP6336089 U JP 6336089U JP 6336089 U JP6336089 U JP 6336089U JP H033827 U JPH033827 U JP H033827U
- Authority
- JP
- Japan
- Prior art keywords
- offset
- converter
- gain
- multiplier
- analog signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000003252 repetitive effect Effects 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Description
第1図は本考案の一実施例のブロツク図、第2
図乃至第4図は第1図の動作を説明する波形図、
第5図は従来の装置のブロツク図、第6図は時間
に従つて振幅が減衰する繰返波形例図である。
1,2……波形メモリ、4,5,14〜17…
…D/A変換器、6,7……アツテネータ、8…
…クロツク発生器、9……演算制御部(CPU)
、10……掛算器、11……アンプ、12……切
換スイツチ。
Fig. 1 is a block diagram of an embodiment of the present invention;
4 to 4 are waveform diagrams explaining the operation of FIG. 1,
FIG. 5 is a block diagram of a conventional device, and FIG. 6 is an example of a repetitive waveform whose amplitude attenuates over time. 1, 2...Waveform memory, 4, 5, 14-17...
...D/A converter, 6, 7...Attenuator, 8...
...Clock generator, 9...Arithmetic control unit (CPU)
, 10...multiplier, 11...amplifier, 12...changeover switch.
Claims (1)
フセツトの調整が可能な各D/A変換器に読み出
してそれぞれのアナログ信号に変換する同一クロ
ツク及び同一位相で駆動される2系統の波形発生
系統と、 これら2系統のアナログ信号出力を乗算する掛
算器と、 該掛算器のアナログ信号出力をデジタル信号に
変換してDCオフセツト及びDCゲインを測定す
るA/D変換器と、 該A/D変換器の測定結果を取り込み、前記掛
算器のゲイン及びオフセツトの校正を行うために
前記各D/A変換器のゲイン及びオフセツトを調
整するのに必要なデータを出力する演算制御部、 とで構成されたことを特徴とする任意波形発生
器。[Claims for Utility Model Registration] Each waveform data is read out from each waveform memory to each D/A converter whose gain and offset can be adjusted, and converted into each analog signal. Driven by the same clock and the same phase. a multiplier that multiplies the analog signal outputs of these two systems; an A/D converter that converts the analog signal output of the multiplier into a digital signal and measures DC offset and DC gain; an arithmetic control unit that takes in the measurement results of the A/D converter and outputs data necessary to adjust the gain and offset of each D/A converter in order to calibrate the gain and offset of the multiplier; , An arbitrary waveform generator comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6336089U JPH033827U (en) | 1989-05-31 | 1989-05-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6336089U JPH033827U (en) | 1989-05-31 | 1989-05-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH033827U true JPH033827U (en) | 1991-01-16 |
Family
ID=31593334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6336089U Pending JPH033827U (en) | 1989-05-31 | 1989-05-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH033827U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002300069A (en) * | 2001-03-30 | 2002-10-11 | Matsushita Electric Ind Co Ltd | Case for storing wireless communication card |
-
1989
- 1989-05-31 JP JP6336089U patent/JPH033827U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002300069A (en) * | 2001-03-30 | 2002-10-11 | Matsushita Electric Ind Co Ltd | Case for storing wireless communication card |
JP4531283B2 (en) * | 2001-03-30 | 2010-08-25 | パナソニック株式会社 | Storage case for wireless communication card |
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