JPH0459639U

JPH0459639U -

Info

Publication number: JPH0459639U
Application number: JP10257990U
Authority: JP
Priority date: 1990-09-28
Filing date: 1990-09-28
Publication date: 1992-05-21

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例を示すＰＭＯＳト
ランジスタを用いた論理レベル出力回路の回路構
成図、第２図は、第１図の論理レベル出力回路の
出力電流―出力電圧特性図、第３図は、第１図の
論理レベル出力回路における出力用トランジスタ
のゲート電圧―出力電圧特性図、第４図は、ＰＭ
ＯＳトランジスタを用いた論理レベル出力回路の
第２実施例を示す回路図、第５図は、ＰＭＯＳト
ランジスタを用いた論理レベル出力回路の第３実
施例を示す回路図、第６図〜第８図は、従来例を
示し、第６図は、ＰＭＯＳトランジスタを用いた
論理レベル出力回路の回路図、第７図は、ＮＭＯ
Ｓトランジスタを用いた論理レベル出力回路の回
路図、第８図は、第７図の回路の出力電流―出力
電圧特性図である。１……出力用トランジスタ、２……ゲート電圧
制御回路、３……ＰＭＯＳトランジスタ、４……
ＮＭＯＳトランジスタ、５……接続点、６……電
圧上昇用トランジスタ、７……インバータ。 FIG. 1 is a circuit configuration diagram of a logic level output circuit using PMOS transistors showing an embodiment of the present invention, FIG. 2 is an output current-output voltage characteristic diagram of the logic level output circuit of FIG. 1, and FIG. Figure 3 is a gate voltage-output voltage characteristic diagram of the output transistor in the logic level output circuit of Figure 1, and Figure 4 is a PM
A circuit diagram showing a second embodiment of a logic level output circuit using OS transistors, FIG. 5 is a circuit diagram showing a third embodiment of a logic level output circuit using PMOS transistors, FIGS. 6 to 8. shows a conventional example, FIG. 6 is a circuit diagram of a logic level output circuit using PMOS transistors, and FIG. 7 is a circuit diagram of a logic level output circuit using PMOS transistors.
FIG. 8, a circuit diagram of a logic level output circuit using S transistors, is an output current-output voltage characteristic diagram of the circuit shown in FIG. 1... Output transistor, 2... Gate voltage control circuit, 3... PMOS transistor, 4...
NMOS transistor, 5... connection point, 6... voltage increase transistor, 7... inverter.

Claims

[Scope of utility model registration request]

PMOS as logic level output transistor
In addition to using a transistor, the output voltage of the PMOS transistor is amplified/level shifted,
This is fed back to the gate electrode of the output transistor via a feedback circuit, and the gate voltage of the PMOS transistor is continuously changed in conjunction with the output voltage.
Logic level output circuit using OS transistors.