JPH0459611U - - Google Patents
Info
- Publication number
- JPH0459611U JPH0459611U JP10326290U JP10326290U JPH0459611U JP H0459611 U JPH0459611 U JP H0459611U JP 10326290 U JP10326290 U JP 10326290U JP 10326290 U JP10326290 U JP 10326290U JP H0459611 U JPH0459611 U JP H0459611U
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- terminal
- circuit
- output
- stop signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims description 31
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は本考案に係る二端子型ＬＣ発振回路の
第１の実施例を示す回路図、第２図は本考案に係
る二端子型ＬＣ発振回路の第２の実施例を示す回
路図、第３図は本考案に係る二端子型ＬＣ発振回
路の第３の実施例を示す回路図、第４図は本考案
に係る二端子型ＬＣ発振回路の第４の実施例を示
す回路図、第５図は従来例に係る二端子型ＬＣ発
振回路を示す回路図、第６図は従来例に係る二端
子型ＬＣ発振回路の動作波形図である。
Ｃ１，Ｃ２……容量、Ｌ……インダクタンス、
ＩＮ……入力端子、ＯＵＴ……出力端子、ＮＡＮ
Ｄ……ナンド回路、Ｒ……出力抵抗、ＩＮＶ……
インバータ、ＳＴＯＰ……発振停止信号、
……発振停止信号ＳＴＯＰの反転信号、ＶＤＤ
……電源電圧、ＶＳＳ……接地電圧、ＱＰ１，Ｑ
Ｐ２……Ｐチヤンネルトランジスタ、ＱＮ１，Ｑ
Ｎ２……Ｎチヤンネルトランジスタ、ＮＯＲ……
ノア回路。
FIG. 1 is a circuit diagram showing a first embodiment of a two-terminal LC oscillation circuit according to the present invention, and FIG. 2 is a circuit diagram showing a second embodiment of a two-terminal LC oscillation circuit according to the present invention. FIG. 3 is a circuit diagram showing a third embodiment of the two-terminal LC oscillation circuit according to the present invention, and FIG. 4 is a circuit diagram showing a fourth embodiment of the two-terminal LC oscillation circuit according to the present invention. FIG. 5 is a circuit diagram showing a conventional two-terminal LC oscillation circuit, and FIG. 6 is an operating waveform diagram of the conventional two-terminal LC oscillation circuit. C 1 , C 2 ... Capacity, L ... Inductance,
IN...Input terminal, OUT...Output terminal, NAN
D...NAND circuit, R...Output resistance, INV...
Inverter, STOP...Oscillation stop signal,
...Inverted signal of oscillation stop signal STOP, VDD
...Power supply voltage, VSS...Ground voltage, QP 1 , Q
P 2 ...P channel transistor, QN 1 ,Q
N2 ...N channel transistor, NOR...
Noah circuit.
Claims (1)
を固定電圧に固定することによつて発振を停止さ
せる発振停止手段を具備することを特徴とする二
端子型ＬＣ発振回路。 (2) 前記発振停止手段が前記発振回路の入力端
子と電源電圧の間に接続され、発振停止信号によ
つて制御されたＰチヤンネルＭＯＳトランジスタ
と、 前記入力端子と前記発振回路の出力端子の間に
設けられ、出力が前記出力端子に接続され、前記
発振停止信号によつて制御されたナンド回路から
成り、発振停止信号が出たときに前記入力、出力
端子が電源電圧に固定され発振をすみやかに停止
することを特徴とする請求項第１項記載の二端子
型ＬＣ発振回路。 (3) 前記発振停止手段が前記発振回路の入力端
子と接地電圧の間に接続され、発振停止信号によ
つて制御されたＮチヤンネルトランジスタと、 前記入力端子と前記発振回路の出力端子の間に
設けられ、出力が前記出力端子に接続され、前記
発振停止信号によつて制御されたノア回路から成
り、発振停止信号が出たときに前記入力、出力端
子が接地電圧に固定され発振をすみやかに停止す
ることを特徴とする請求項第１項記載の二端子型
ＬＣ発振回路。[Claims for Utility Model Registration] (1) A two-terminal type LC oscillation circuit, characterized in that it is equipped with oscillation stopping means for stopping oscillation by fixing the two terminals to a fixed voltage. LC oscillation circuit. (2) The oscillation stop means is connected between the input terminal of the oscillation circuit and a power supply voltage, and is controlled by an oscillation stop signal, and a P-channel MOS transistor; and between the input terminal and the output terminal of the oscillation circuit. The circuit is provided with a NAND circuit whose output is connected to the output terminal and is controlled by the oscillation stop signal, and when the oscillation stop signal is output, the input and output terminals are fixed to the power supply voltage to quickly stop oscillation. 2. The two-terminal LC oscillation circuit according to claim 1, wherein the two-terminal LC oscillation circuit stops at . (3) The oscillation stop means is connected between the input terminal of the oscillation circuit and ground voltage, and is controlled by an oscillation stop signal, and an N-channel transistor, and the oscillation stop means is connected between the input terminal and the output terminal of the oscillation circuit. It consists of a NOR circuit whose output is connected to the output terminal and controlled by the oscillation stop signal, and when the oscillation stop signal is output, the input and output terminals are fixed to the ground voltage and the oscillation is immediately stopped. 2. The two-terminal LC oscillation circuit according to claim 1, wherein the two-terminal LC oscillation circuit stops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990103262U JPH071853Y2 (en) | 1990-09-28 | 1990-09-28 | Two-terminal LC oscillator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990103262U JPH071853Y2 (en) | 1990-09-28 | 1990-09-28 | Two-terminal LC oscillator circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0459611U true JPH0459611U (en) | 1992-05-21 |
| JPH071853Y2 JPH071853Y2 (en) | 1995-01-18 |
Family
ID=31848070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990103262U Expired - Lifetime JPH071853Y2 (en) | 1990-09-28 | 1990-09-28 | Two-terminal LC oscillator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071853Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55114006A (en) * | 1979-02-27 | 1980-09-03 | Matsushita Electric Ind Co Ltd | Synchronous type crystal oscillator |
-
1990
- 1990-09-28 JP JP1990103262U patent/JPH071853Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55114006A (en) * | 1979-02-27 | 1980-09-03 | Matsushita Electric Ind Co Ltd | Synchronous type crystal oscillator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH071853Y2 (en) | 1995-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0250947A3 (en) | Bimos logic gate | |
| JPS5996937U (en) | Schmitt trigger circuit | |
| JPH0459611U (en) | ||
| JPH01195720A (en) | Semiconductor integrated circuit | |
| JPH0555905A (en) | Cmos logic gate | |
| JPH0263219A (en) | Charge pump circuit | |
| JPS6243367B2 (en) | ||
| JP2712432B2 (en) | Majority logic | |
| JPH0268526U (en) | ||
| JPH0348928U (en) | ||
| JPS57180224A (en) | Flip-flop circuit | |
| JPH03125531U (en) | ||
| JPS63305615A (en) | Buffer circuit | |
| JPS5893014U (en) | Complementary output circuit | |
| JPS5973846U (en) | semiconductor circuit | |
| JPS6312911U (en) | ||
| JPS5897921A (en) | Monolithic integrated inverter buffer | |
| JPH0320546U (en) | ||
| JPS62154749U (en) | ||
| JPS6295321U (en) | ||
| JPS5942051U (en) | integrated circuit | |
| JPH03142786A (en) | Semiconductor memory device | |
| JPH0253638U (en) | ||
| JPH02134721U (en) | ||
| JPH0466815U (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |