JPH03142786A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress the reduction of an H output accompanying the operation of a peripheral circuit during a data H output period by connecting an FET, which defines a control signal as a gate input, serially to an FET with high ability which defines a data signal as a gate input, making this FET parallel to the FET with low ability, which defines the data signal as the gate input, and connecting the gate nodal point of an output transistor with a power supply line. CONSTITUTION:When the peripheral circuit is operated and a nodal point VCC1 is fluctuated, a nodal point VCC2 is also fluctuated. However, since an integration circuit with a large time constant is formed by the high ON resistance of an FET Q5 and the gate capacity of an FET Q1, the rapid fluctuation of the nodal point VCC1 is absorbed and fluctuation is suppressed at a gate nodal point N1 of the FET Q1. Further, since the nodal point VCC3 as the drain of the FET Q1 is connected through parasitic resistors R1 and R3 to the nodal point VCC1, the fluctuation of the nodal point VCC3 caused by the operation of the peripheral circuit is suppressed and the current ability of the Q1 does not depend on the VCC3. Thus, since the ability of the FET Q1 is not almost lowered regardless of the fluctuation in the nodal point VCC1, the reduction of an H output level at an output terminal OUT can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a data output buffer that outputs a high level using an N-type MOS field effect transistor.

[Prior Art] Conventionally, this type of semiconductor memory device uses an N-type enhancement type MOS field effect transistor (hereinafter abbreviated as FET) as a data output buffer, thereby achieving a high level (hereinafter abbreviated as H). ) is output. That is, when a P-type MOSFET is used as an output transistor in a semiconductor memory device that allocates data input and output to a common terminal, when a voltage higher than the power supply voltage is applied to the input/output common terminal, the P-type MOSFET latches. An N-type MOSFET is used because this causes an up phenomenon that leads to destruction of the element.

FIG. 2 shows a conventional semiconductor memory device. φH2φL are data signals Ql, Q2 . Q4 is N type MOSFET
, Q3 is P-type MO5FET, Gl is inverter, OUT
is the data output terminal, R1゜R2, R3 are wiring parasitic resistances,
VCCO, VCCI.

vCC2 and vCC3 are nodes on the electric R line, Nl.

N2 is a node, CL is an external load capacitor, R4 is a pull-up resistor, R5 is a pull-down resistor, and vCC is an external power supply.

FIG. 4 shows signal waveforms of the main parts of the circuit shown in FIG. 2.

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to FIG. 4.

First, if data reading is not permitted, both data signals φH2φL are at H (period t1).

At this time, nodes Nl and N2 are both at a low level (hereinafter abbreviated as L), and FETs QI and Q2 are both turned off, so the data output terminal OUT is high impedance and is composed of resistors R4, R5, and load capacitance CL. This is the potential given by the external circuit. Next, when data reading is permitted, if the read data is L, the data signal φL becomes L and the data signal φH becomes H. At this time, the node N2 becomes H due to the inverter G1, and the FET Q2
is turned on, the charge stored in the external load capacitor CL is discharged to the ground line via the FET Q2, and the data output terminal OUT becomes L. Also, the read data is H
If so, the data signal φH becomes L, and the data signal φH becomes H (period t2). At this time, FETQ3. The inverter configured by Q4 causes node N1 to become H, and F
Since ETQI is turned on, the external load capacitance CL is
Charged from the power supply line via QI, data output terminal OU
T becomes H. Here, FETQI is an N-type enhancement type, and node N1 is an FET with high transistor performance.
The power level is connected to the power line via ETQ3. Therefore, if the potential of node N1 at the time of data H output is V(Nl), and the input threshold voltage of FETQI is VT, the potential V(OUT) of data output terminal OUT is V(
Nl) - VT. Furthermore, in the above external circuit, the data output terminal OUT is connected to the external power supply and the ground line through the pull-up resistor R4 and the pull-down resistor R5, respectively, so that the data output terminal OUT is kept at H as FETQI continues to flow current. ing. Node V
Assuming that the potential of CC3 is V (vCC3), when the data output terminal OUT maintains H, V (Nl) < V (vCC3) + VT...
・・・・・・・・・・・・(1) Therefore, FETQI is operating in the saturation region, and the current flowing through FETQI is β I= (V(Nl)− V(OUT)-VT)2・
...-(2) It is expressed as. That is, the current flowing through FETQI strongly depends on the potential of node N1, and does not depend on the potential of node VCC3 as long as equation (1) holds true.

Also, when outputting H to the data output terminal, FETQ
1 suddenly flows current from the off state, the level of the power supply line connected to the output transistor drops rapidly due to the inductance component parasitic to the power supply line, and this level fluctuation (hereinafter referred to as power supply noise) causes Peripheral circuits malfunction. Therefore, due to the layout, the power supply line for the output transistor and the power supply line for the peripheral circuit are run separately, and the noise is absorbed by the integration circuit formed by the wiring resistance and parasitic capacitance. This prevented malfunctions.

[Problems to be Solved by the Invention] The conventional semiconductor memory device described above has an H
Since the gate node of the output transistor that outputs a signal is connected to the power supply line common to the peripheral circuit through a FET with high performance, when the peripheral circuit operates when H is output to the data output terminal, the Since the level of the power supply line is lowered and the output transistor gate node is lowered, the ability of the output transistor is lowered and the H output level is lowered.

This has the disadvantage that the output logic level is inverted.

[Differences between the invention and the prior art] In contrast to the conventional semiconductor memory device described above, the present invention connects a high-capacity FET that receives a data signal as a gate input in series with an FET that receives a control signal as its gate input. The difference is that by paralleling low-performance FETs that use data signals as gate inputs and connecting the gate node of the output transistor to the power supply line, the drop in H output due to the operation of peripheral circuits during the data H output period is suppressed. Has a point.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a first N-type MOS field effect transistor provided in an output section and having a drain connected to a power supply line, and a first N-type MOS field effect transistor having a source connected to a power supply line and transmitting data. The second P-type MOS field-effect transistor includes a second P-type MOS field-effect transistor whose gate receives a signal, and a third N-type MOS field-effect transistor whose source is connected to a ground line and whose gate receives a data signal. type field effect transistor and the third N type M
The drain of the OS field effect transistor is connected to the first N-type MO
In a semiconductor memory device having a data output buffer as a gate input of an S field effect transistor, a fourth P type MOS field effect transistor is interposed between the source of the second P type MOS field effect transistor and a power supply line. , the control signal delayed with respect to the data signal is input to the gate of the fourth P-type MO8 field effect transistor, while the gate is the data signal, the source is the power supply line, and the drain is the first P-type MOS field effect transistor. The present invention is characterized in that fifth P-type MOS field effect transistors each having a lower capability than the second and fourth P-type MO5 field effect transistors are connected to the gates thereof.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Hereinafter, the same parts as those of the conventional semiconductor memory H arrangement shown in FIG. 2 will be described with the same reference numerals. Q5. Q6 is P type MOSFE
It is T. The transistor capacity of FETQ6 is FETQ3
It is almost the same as that of FETQ5, and the transistor capacity of FETQ5 is F
ETQ3. It is lower than that of Q6. That is,
The on-resistance of FETQ5 is the same as that of FETQ3 connected in series.
．． It is assumed that the on-resistance is larger than that of Q6. φ is Q
When the data signal φH is H in the control signal 6, the control signal φ is L, and the control signal φ becomes H after a certain period of time after the data signal φH becomes L.

FIG. 3 shows signal waveforms of the main parts of the circuit shown in FIG. 1. The operation of the circuit shown in FIG. 1 will be explained with reference to FIG.

First, when data reading is not permitted, the data signal φH is H, so the control signal φ is high as described above (period t1). At this time, FETQ6 is on, but FETQ3. Since Q5 is off and Q4 is on, the node Nl is at L and the data output terminal OUT is at high impedance. Read is allowed here and H
When data is read, data signal φH becomes L, and Q
Since FET Q3.3 is on and Q4 is off, it has high transistor performance and low resistance. The node Nl is rapidly charged to H by the series circuit of Q6, and H is outputted to the data output terminal OUT by FETQI (period t2).

At this time, FETQ5 is also turned on at the same time, but since FETQ5 has low capability and high resistance, it does not contribute much to charging of node N1.

When φ becomes H after a certain period of time after data signal φH becomes L, FET Q6 turns off, so H node N1 is connected to power supply line VCC2 only via FET Q5 with high on-resistance (period t4).

During this period, when the peripheral circuit operates and node VCCI fluctuates, node VCC2 also fluctuates, but because the high on-resistance of FETQ5 and the gate capacitance of FETQI form an integrating circuit with a large time constant, the sudden change in node VCCI The fluctuation is absorbed, and the fluctuation of the gate node N1 of FET Ql is suppressed. Furthermore, the node VCC3 which is the train of FETQI
is connected to node VCCI via parasitic resistors R1 and R3, so fluctuations in node VCC3 due to operations of peripheral circuits are suppressed, and the current capability of Ql does not depend on VCC3. Therefore, the ability of FETQI hardly decreases despite the fluctuation of node vcci, so the output terminal OUT
It is possible to significantly reduce the decrease in the H output level.

FIG. 5 shows an example of a circuit that generates the control signal φ. DL is a signal delay element, and G2 is a NOR gate.

This circuit can generate the control signal φ as shown in FIG. 3 based on the data signal φH.

[Effects of the Invention] As explained above, the present invention shuts off high-capacity transistors after a certain period of time after outputting H, and sets the gate node of the transistor that outputs H to the data output terminal of only low-capacity transistors to H. This has the effect of significantly reducing the drop in the H output level due to sudden power fluctuation noise caused by peripheral circuits.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional example, Fig. 3 is a signal waveform diagram of main parts of the circuit shown in Fig. 1, and Fig. 4 is a circuit diagram showing a conventional example. FIG. 5 is a circuit diagram of a circuit for generating control signals in an embodiment of the present invention. φH2φL... Data signal that changes according to data read from the internal storage cell, φ・ ・ ・ ・ ・ ・ Ql, G2. G4 ・・Control signal, ・N-type MOS FET, G3. G5. G6 ・ G1 ・ ・ ・ ・ ・ ・ ・ G2 ・ ・ ・ ・ ・ DL ・ ・ ・ ・ ・ ・ OUT ・ ・ ・ ・ ・ ・ R1, R2, R3 ・ ・P-type MOSFET, ・Inverter, ・Noah gate,・Signal delay element, ・Data output terminal, ・Wiring parasitic resistance, VCGO, VCCI. VCC2, VCC3... Nodes in the power supply line, Nl
, N2◆ CL ・ ・ ・ ・ R4 ◆ ・ ◆ R5 ◆ ・ ・ VCC ◆ ◆ ・Node, ・External load capacitance, ・Pull-up resistor, ・Pull-down resistor, ・External power supply.

Claims (1)

[Claims] A first N-type MOS field effect transistor provided in the output section and having a drain connected to a power supply line, and a second PMOS field effect transistor having a source connected to the power supply line and having a data signal input to its gate.
type MOS field effect transistor and a third N type MO whose source is connected to the ground line and whose gate is inputted with a data signal.
A semiconductor memory having a data output buffer comprising an S field effect transistor, and the drains of the second P type field effect transistor and the third N type MOS field effect transistor are input to the gate of the first N type MOS field effect transistor. In the device, a fourth P-type MOS field-effect transistor is interposed between the source of the second P-type MOS field-effect transistor and the power supply line, and a control signal delayed with respect to the data signal is transmitted to the fourth P-type MOS field-effect transistor. The gate is connected to the data signal, the source is connected to the power supply line, and the drain is connected to the gate of the first P-type MOS field-effect transistor. A semiconductor memory device characterized in that a fifth P-type MOS field effect transistor having a lower capability than an effect transistor is provided.