JPH045858A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the number of steps and to stably separate elements by burying a multilayer epitaxial layer in a trench formed in a semi-insulating board, and exposing part of a high concentration impurity layer of the lowermost layer of the multilayer epitaxial layer on the surface of the board. CONSTITUTION:A mask 16 of an insulating film is formed on a semi-insulating compound semiconductor substrate 1, and etched. An n<+> type GaAs layer 2 of an epitaxial layer including high concentration n-type impurity is formed by a selective burying growth method in the formed trench. After the insulating film mask 16 is removed, an insulating film mask 14 is again formed, and the layer 2 is etched. Thereafter, a collector layer 3 of the layer 2, a base layer 4, an emitter layer 5, an n<+> type GaAs 6 are sequentially formed by burying growth technique. Then, after a sidewall 17 is formed, an emitter electrode 9 is formed. Subsequently, using the sidewall 17 and the electrode 9 as a mask it is etched to the layer 4, and opened. Further, after a sidewall 15 is formed, a base electrode 9 is formed. Then, a collector electrode 7 is formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a compound semiconductor device characterized by having a multilayer structure composed of different types of semiconductors and a method of manufacturing the same. be.

[Prior Art] Hereinafter, as a conventional example of the present invention, a method for manufacturing a hetero bipolar transistor (HB, T) will be described as an example.

FIG. 3 shows an example of the structure of a conventional HBT. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a collector n
” GaAs layer, 3 is collector n-GaAs layer, 4
5 is the base p-GaAs layer, and 5 is the emitter n-AlG layer.
aAs1! ! , 6 is an n''-GaAs layer of the emitter. Also, 7 is a collector electrode, 8 is a base electrode, 9 is an emitter electrode, 10 is an insulating film for protecting the emitter electrode, 11.
12 and 13 are insulating side walls.

The sidewall 11 is for preventing short circuit with the emitter when forming the base electrode 8, and the sidewall 12 is a mask for processing the base electrode into the emitter and self-alignment line. The sidewall 13 is for preventing short circuit with the base when forming the collector electrode 7. The insulating film 10 protects the emitter electrode 9 in all the steps described above.

Next, the manufacturing method will be explained using FIG. 4.

First, a collector 2.3, a base 4,
Each layer having the desired composition and impurity concentration to become the emitter 5.6 is grown over the entire surface.

Next, metal that will become the emitter electrode 9 is deposited on the entire surface of the wafer,
An insulating film 10 is deposited thereon. A mask for forming an emitter is formed by photolithography, and the insulating film is anisotropically etched using the mask, and subsequently, the emitter electrode is also etched using the insulating film as a mask. Further, the shrimp growth is etched until the base layer 4 is exposed (FIG. 4(a)).

Next, an insulating film is deposited on the entire surface and etched back by anisotropic etching to form a sidewall 11 (see FIG. 4).
Ha)).

Next, after depositing the base electrode 8, an insulating film is deposited again, and the sidewall 12 is formed by etching back (the fourth
Figure (C)).

Next, after applying and planarizing a resist, the entire surface is etched back to expose the base electrode metal portion on the insulating film 10, and this portion is removed by etching. After removing the resist, the shrimp growth layer is etched using the insulating film 12 as a mask until the collector layer 2 is exposed (see FIG. 4).
B)).

Next, the collector electrode 7 is formed by vapor deposition lift-off (FIG. 4(e)).

After the resist is coated and flattened, only the collector electrode metal portion attached to the insulating film 10 is exposed by etchback, and this is removed by etching. Thereafter, the resist is removed to complete the HBT having the desired structure (Figure 4).

[Problem to be solved by the invention]

As described above, the conventional HBT manufacturing method cannot obtain a planar element structure and is disadvantageous for IC fabrication.Also, in order to take out the electrodes from the base layer and collector layer, it is necessary to remove the shrimp layer. Etching is performed twice, which increases the number of steps that require precise etching control.Furthermore, it is necessary to perform element isolation after element formation, but this element isolation is performed by ion implantation. Seventh, there was a problem with its thermal stability, and when mesa etching was performed, there was a problem that the level difference further increased.

This invention was made to solve the above-mentioned problems, and it is possible to planarize a device consisting of multiple epitaxial layers, reduce the number of etching steps for the shrimp layer, and achieve stable device separation. It is an object of the present invention to provide a semiconductor device that can obtain characteristics and a method for manufacturing the same.

[Means to solve the problem]

A semiconductor device according to the present invention is formed by embedding a multilayer epitaxial layer in a trench formed in a semi-insulating substrate, and exposing a part of the lowest high concentration impurity layer of the multilayer epitaxial layer to the substrate surface. This is what I did.

Further, in the method of manufacturing a semiconductor device according to the present invention, first, a high concentration impurity layer for making electrical contact is embedded and grown from a quantification layer of a multilayer epitaxial layer, and then a trench is formed in this high concentration impurity layer. Then, a multilayer epitaxial layer, which will become the active layer of the device, is embedded and grown with a central axis different from the central axis during growth of the high concentration impurity layer, and the bottom layer is grown to a sufficient size on the substrate surface. The active layer is etched to a desired layer to take out the electrode, and the electrode is also taken out from the surface of the high concentration impurity layer.

[Effect]

In the semiconductor device according to the present invention, the multilayer epitaxial layer is buried and grown in the trench of the semi-insulating compound semiconductor substrate, so that the device structure can be basically flat with respect to the substrate. Not only that, but element isolation will also be performed on the semi-insulating substrate itself.

Furthermore, in the semiconductor device manufacturing method of the present invention, the buried growth layer is not grown at once, but is grown in two steps.
By shifting the center axis when growing the high concentration impurity layer and the center when growing the active layer, the high concentration impurity layer is exposed over a sufficiently large area on the substrate surface, and from the exposed part to the top of the active layer. Since the electrode is formed to make electrical contact with the underlying high-concentration impurity layer, the step of exposing the lowest layer of the active layer by etching is unnecessary.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the structure of a semiconductor device according to an embodiment of the present invention, and this is an example in which the present invention is applied to an HBT. In the figure, 1 is a semi-insulating compound semiconductor substrate, 2 is a collector n''-GaAs layer, and 3 is a collector n-GaAs layer.
Asjii, 4 is the base pGaAs layer, 5 is the emitter n-A I Ga As layer, 6 is the emitter n
"-GaAs layer, 7 is a collector electrode, 8 is a base electrode, and 9 is an emitter electrode. 14 is an insulating film used as a mask for selective buried growth, and 15 is to prevent short circuit with the emitter electrode when forming the base electrode. An insulating film sidewall 17 is an insulating film sidewall used when forming an emitter electrode.

Next, a method for manufacturing this HBT will be explained using figures.

Figure 2 is a cross-sectional view following the manufacturing flow.
An insulating film mask 16 is formed on the semi-insulating compound semiconductor substrate 1, and the semi-insulating compound substrate 1 is etched using this as a mask. In the trench thus formed, there is an n”-GaA layer containing a high concentration of n-type impurities.
Reduce pressure of sjii2 OMV P E (Organic
Meta Vaper Phase Epitaxy)
selective embedding growth using the method (Fig. 2(a)).

Next, after removing the insulating film mask 16, again as shown in FIG. 2(b).
As shown in FIG. 2, an insulating film mask 14 covering the substrate 1 and a part of the n"-GaAs layer 2 is formed, and the n"-GaAs layer 2 is etched using this as a mask. After that, in the trench of the etched n+-GaAs layer 2, the collector n-GaAs 1i3, the base p-GaAs layer 4,
Emitter nAlGaAsR15, n+-CyaAs6
are sequentially embedded and grown (Fig. 2(b)).

Next, after forming the sidewall 17 on the insulating film mask portion, the emitter electrode 9 is formed by vapor deposition lift-off (
Figure 2 (C)).

Next, using the sidewall 17 and emitter electrode 9 as a mask, the base layer 4 is etched to form an opening (see FIG. 2(d)).
).

Then, after forming a sidewall 15 on the side wall of the opening, a base electrode 8 is formed by vapor deposition lift-off (FIG. 2(e)).

Next, the insulating film 1 in the region corresponding to the collector electrode forming part is
4 is removed by etching, and a collector electrode 7 is formed on the etched portion by vapor deposition lift-off (FIG. 2(f)).

In this example, the multilayer epitaxial layer serving as the active layer is buried in the trench of the semi-insulating compound semiconductor substrate, so the device structure is basically flat with respect to the substrate, and the IC A structure that is advantageous for oxidation can be obtained. In addition, since element isolation is also performed on the semi-insulating substrate itself, the process for element isolation can be omitted, and unlike conventional element isolation processes, element characteristics deteriorate and step portions increase. There is no fear of this, and stable element isolation characteristics can be obtained.

In addition, the buried growth layer is not grown in one step, but is divided into two steps, and the center axis when growing the high concentration impurity layer 2 made of n4 GaAs layer and the n-GaA
s1i3. p-GaAs layer 4, n-AlGaAs layer 5
．． Since the central axis of the growth of the n'-GaAs layer 6 is shifted, the high concentration impurity layer 2 is exposed on the surface of the substrate 1 in a sufficiently large area. Therefore, the electrode that makes electrical contact with the high concentration impurity layer 2, which is the lowest layer of the active layer, can be taken out from the exposed part of the substrate surface, so the lowest layer of the active layer can be exposed by etching. The etching process can be reduced.

〔Effect of the invention〕

As described above, in the present invention, since an active layer consisting of a multilayer epitaxial layer is formed on a semi-insulating substrate by selective buried growth, a planar device structure can be achieved and device isolation can be automatically performed.

In addition, the buried growth of the multilayer epitaxial layer described above was
Since the second buried growth is grown off-center from the first, it is possible to make contact with the bottom layer of the multilayer epitaxial layer from the substrate surface. Etching eliminates the need for exposure, which has the effect of reducing the number of steps.

Although the above embodiments have been explained using HBT as an example, the present invention is applicable to HET (Hot-Electron-Trans).
istor), RHE T (Resonance H
Of course, the present invention can also be applied to other devices such as ot-Electron-Transistors, and the same effects as in the above embodiment can be achieved in this case as well.

[Brief explanation of drawings]

FIG. 1 shows a semiconductor device HB according to an embodiment of the present invention.
2 is a diagram showing a method of manufacturing the semiconductor device of FIG. 1, FIG. 3 is a diagram showing the structure of a conventional HBT, and FIG. 4 is a diagram showing the manufacturing method of the semiconductor device of FIG. 3. FIG. 2 is a diagram illustrating the method. 1 is a semi-insulating compound semiconductor substrate, 2 is the collector n”-
GaAsll, 3 is collector n-GaAsN, 4 is base p-GaAs layer 6.5 is emitter n-AlGa
As layer, 6 is emitter n4G a A, s layer, 7 is collector electrode, 8 is base electrode, 9 is emitter electrode, 1
4.16 is an insulating film, and 15°17 is an insulating film sidewall. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a semiconductor device having an active layer consisting of a multilayer epitaxial layer, the multilayer epitaxial layer is formed by being buried in a trench provided in a semi-insulating compound semiconductor substrate, and the lowermost layer of the multilayer epitaxial layer has a high concentration. A semiconductor device, wherein a part of the impurity layer is exposed on the surface of the semi-insulating compound semiconductor substrate. (2) A first step of etching away a desired portion of the semi-insulating compound semiconductor substrate, and using the mask used in the first step, a crystal containing a high concentration of impurities is added to the etched portion. a second step of selectively growing the high concentration impurity layer to form a high concentration impurity layer; a third step of etching away a part of the high concentration impurity layer; a fourth step of selectively growing a crystal having an active layer consisting of multiple layers with a central axis different from the central axis during growth of the high concentration impurity layer in the second step; A method for manufacturing a semiconductor device, comprising: a fifth step of etching the layer to take out the electrode; and a sixth step of drawing out the electrode from the surface of the high concentration impurity layer.