JPS62112369A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To form buried layers for leading out electrodes easily by a method wherein a compound semiconductor substrate is etched through apertures formed in a dielectric film to form holes. CONSTITUTION:A collector layer, a base layer and an emitter layer 12-16 are formed on a GaAs substrate 11. After semi-insulating buried layers 17 are formed in the substrate 11, an SiO2 film is deposited on the substrate surface and apertures are made in the parts where P-type buried layers 18 for leading out base electrodes 21 are to formed. Then holes are drilled by etching through the apertures and the P-type buried layers 18 are formed in the holes. Then, likewise, N-type buried layers 19 are formed. After that, an emitter electrode 20, the base electrodes 21 and collector electrodes 22 are formed on the layer 16, the layers 18 and the layers 19 respectively. With this constitution, the buried layers for leading out electrodes can be formed easily and a transistor which has a flat top surface can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bipolar transistor using a compound semiconductor, and particularly to a heterojunction bipolar transistor.

(Prior Art) A heterojunction bipolar transistor using a compound semiconductor, for example a heterojunction bipolar transistor using a combination of GaAs l AlxGa1-xAs, is excellent as an amplification number or switching element for ultra-high frequencies with a high blocking frequency. The technology related to its manufacturing method is described in the literature Extended Abstracts of the Sixteenth Conference J. Solid State Devices and Materials (E.
xtendedAbstracts of the 1
6th (1984 International)C
onferece on 5olid 5tate D
evices and Materials) August 30, 1984 Sponsored by Niza Ji 4. Nokun Science of Applied Physics (THE JAPAN 5)
OCIETY OF APPLIED PI (YSIC
8) pp. 343-346.

In the following, only a heterojunction bipolar transistor using a combination of GaAs and A11-xGaxAll will be described. To fabricate a conventional device, a highly concentrated n-type GaAs (hereinafter referred to as red) layer and an n-type GaAs (hereinafter referred to as n-GaAs) layer are formed on a semi-insulating GaAs substrate.
A collector layer consisting of a high concentration p-type GaAs layer (
n-A1 on the base layer of the layer (hereinafter referred to as p-GaAs)
An emitter layer composed of a 1-x GaXAs layer and an n-GaAs layer is crystal-grown in sequence.

After that, when each electrode is taken out to the outside, mesa etching is usually performed with high precision to expose the collector layer or base layer to the surface, and metal electrodes are formed on top of the collector layer or base layer to establish ohmic contact.

(Problems to be Solved by the Invention) However, in the manufacturing method described above, the substrate is subjected to mesa etching to expose the collector layer and/or the base layer on the surface, and metal electrodes are formed on each layer. Since it is in ohmic contact, strict accuracy is required for the Elatin 7'8'', and the finished l.
There is a problem in that the shape of the Lanzoster is not suitable for integration unless it is a flat structure.Therefore, the purpose of the present invention is to solve the problems described in "-" and to create a structure with good/damage properties. ) A method for manufacturing a heterojunction bipolar transistor that does not require strict etching accuracy is provided.

(Means for Solving the Problem Z) In order to solve the above problems, the present invention provides a compound semiconductor substrate in which an emitter layer, a base layer forming a heterojunction with the emitter layer, and a collector layer are cured in order from the surface. A dielectric film having an opening in a predetermined first region is prepared, and etching is performed using this opening to form a hole exposing the base layer, and a vapor phase is applied to fill the hole. A base region is formed in this hole using an epitaxial growth method, and a predetermined second region is covered with a dielectric film having an opening, and etching is performed using this opening to form a hole that exposes the collector layer. A collector region is formed in this hole using a vapor phase epitaxial growth method so as to fill this hole, and then electrodes are formed on the emitter layer, the base region, and the collector region, respectively.

(Function) As described above, in the present invention, holes are formed in the compound semiconductor substrate by etching the silicon compound semiconductor substrate through the openings formed in the heat-resistant dielectric film. Even if a compound containing impurities is grown using the vapor phase epitaxial growth method, most of the impurity will not adhere, or even if it does, it will be incomplete and will be removed at the same time as the dielectric film is removed. A compound semiconductor containing impurities can be formed only in the hole portion, and the hole portion can be filled to form a bipolar transistor with a flat surface.

(Example) FIG. 1 is a cross-sectional view of the structure of a bipolar transistor for which the present invention will not be explained in detail, and will be explained below with reference to the drawings.

11 to 16 are semi-insulating GaAs substrates in order from the bottom.
n GaAs layer, n,-GaAs layer r p-GaA
g layer.

n-AAxGa +-, Al1 layer (or about 0.3)
, n-GaAs layer, 12 to 16 are GaAs
MBE (molecular beam epitaxy) on the substrate 11
The crystals are grown sequentially using an epitaxial growth method such as a metal organic chemical vapor deposition (MOCVD) method or MOCVD (metal organic chemical vapor deposition) method. Note that the n-AlxGa1-xAs layer 15 can also have a composition gradient. The thickness of each layer varies depending on the required performance of the transistor, but the approximate thickness is that the n-GaAs layer 12 has a thickness of 5,000 to 10,000×, an n-
Ga/vq layer 13 is 2000-3000A, p-Ga
The As layer 14 is about 100OAIn-AlxGa1-,
As layer 15 is about 1000 A, n-GaAs layer 1
6 is approximately 10001. After forming each of these layers 12 to I6, a 5i02 film (not shown) is deposited on the surface of the substrate, and an opening is formed in a portion corresponding to the semi-insulating buried layer 17 for element isolation. This opening is etched using an anisotropic etching solution such as Br2-based to form a hole exposing the lower plane of the crystal in the semi-insulating buried layer 17, and then a semi-insulating layer is formed using MOCVD. The remaining S
Almost no G a A, s adheres to the TO 2 film, or even if it does adhere, it is incomplete, and is removed at the same time as the 5i0 2 film is removed after growth.

The selective growth of n-GaAa proceeds to backfill the hole, and the growth is terminated when the surface of the warp becomes flat.

Thereafter, the remaining 5i02 film is removed, a further 5i02 film is deposited on the substrate surface, and an opening is formed in the 5i02 film at a portion corresponding to the p-type buried layer Z8 from which the base electrode is taken out. From this opening, a hole is formed in the p-type buried layer 18 portion exposing the low-order plane of the crystal of the p-GaAs layer 14 by etching using an anisotropic etching solution such as Br2-based etching liquid, and then MOCVD is performed. The sill-type buried layer 18 is formed by selectively growing p-GaAS containing Zn or the like which gives p-type trench conductivity. As described above, GaAs hardly adheres to the SiO□ film, or even if it does adhere, it is incomplete, and is removed at the same time as the 5i02 film is removed after growth. The selective growth of semi-insulating GaAs proceeds to backfill the hole, and m1 in the table below is flat.
! When it reaches tζ, end the growth.1. Zara;・
C1 Using the same method as described above, an n-type buried layer 19 for taking out the first electrode is formed of n-Ga or As containing a memory giving n-type conductivity.

After that, the n-GaAs layer 16. An emitter base electrode 21 and a collector electrode 22 are formed in ohmic contact with the respective soils of the p-type buried layer 18 and the n-type buried layer 19.

In addition, in the embodiment of the present invention, semi-insulating
Or a model for selective growth of p-Ga, As.
Although the SiO□ film was used in the above, other films can be used as long as they are heat resistant.Also, as a method to avoid etching the substrate 11, an anisotropic etchant of Br2 may be used. However, it is also possible to use an etching method and an etching solution that can expose the lower-order planes of the substrate crystal. , semi-insulating buried layer 17. Although the MOCVD method is used as the growth method for the p-type buried layer 18 and the n-type buried layer 19, other methods can also be used as long as it is a VPE method.

In the embodiments of the present invention, a method for manufacturing a bipolar transistor using a GaAs substrate as the substrate 11 has been described. The manufacturing method of the present invention is also applicable to a compound semiconductor heterojunction bipolar transistor using a combination with yPy. It can also be used in only one or more layers.

According to an embodiment of the present invention, the substrate 11 is etched through an opening formed in the 5i02 film to etch the semi-insulating buried layer 17. A p-type buried layer 18 and an n-type buried layer 19 are formed with holes, and a GaAF layer having semi-insulating property, p-type groove conductivity, and n-type conductivity is formed on the surface by MOCVD.
Since N is grown, the G is selectively applied only to the hole portion.
AAs can be grown, and the hole portion can be filled with a predetermined portion of the GaAs to form a bipolar transistor with a flat plane.

(Effects of the Invention) As described in detail above, according to the present invention, there is a semi-insulating buried layer for element isolation, an n-type buried layer for taking out the collector electrode, and a p-type buried layer for taking out the base electrode (-). The buried layer can be easily formed and a transistor with a flat structure can be manufactured.Therefore, the manufacturing method of the present invention is suitable for integrated circuit devices of bipolar transistors.

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of a parapolar transistor for explaining the present invention in detail. + 77-...Semi-insulating GaAs substrate, 12 =・n −G
aAs layer, 13- n-GaAs layer, 14 □-p-G
aAs layer, 15-n-AI3xGa 1-xAs layer, J
6.=n-GaAs layer, I7...semi-insulating buried layer, 18...p-type buried layer, 19...n
Mold embedding layer, 20...emitter electrode, 21...base electrode, 22...collector electrode.

Claims (1)

[Claims] A step of preparing a compound semiconductor substrate having, in order from the surface, an emitter layer, a base layer forming a heterojunction with the emitter layer, and a collector layer; and a dielectric film having an opening in a predetermined first region. forming a hole exposing the base layer by covering and etching using the opening; and forming a base region in the hole using a vapor phase epitaxial growth method so as to fill the hole. , a step of forming a hole exposing the collector layer by covering a dielectric film having an opening in a predetermined second region and performing etching using the opening, and vapor phase epitaxial growth to fill the hole. A bipolar transistor comprising the steps of: forming a collector region in the hole using a method; and then forming electrodes on the emitter layer, the base region, and the collector region, respectively. manufacturing method.