JPH0458587A - Chip packaging structure - Google Patents

Chip packaging structure

Info

Publication number
JPH0458587A
JPH0458587A JP17089190A JP17089190A JPH0458587A JP H0458587 A JPH0458587 A JP H0458587A JP 17089190 A JP17089190 A JP 17089190A JP 17089190 A JP17089190 A JP 17089190A JP H0458587 A JPH0458587 A JP H0458587A
Authority
JP
Japan
Prior art keywords
chips
chip
close contact
chip components
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17089190A
Other languages
Japanese (ja)
Inventor
Yasuhiro Tanaka
田中 康廣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP17089190A priority Critical patent/JPH0458587A/en
Publication of JPH0458587A publication Critical patent/JPH0458587A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Abstract

PURPOSE:To make compact the structure of an electronic circuit by bringing each chip into close contact with each other so that they may be integrally mounted where outer electrode for a plurality of chips are electrically connected with each other. CONSTITUTION:Chips 2 are integrally mounted with a board 1 under close contact where mounting electrodes 3 are installed to mount the chips 2. Outer electrodes 4 which constitute the circuit are electrically connected with each other and their end faces are brought into close contact with each other under the condition stated above. Since the chips 2 can be mounted with the board 1 with high packaging density, it is possible to make compact the structure of the electrode circuit. Furthermore, the chips 2 themselves are provided with wiring functions, which can eliminate the board 1. Or the chips 2 can be produced more easily on a modular basis or a unit basis by standardizing the outside dimension of the chips 2, and the formation and positions of the outer electrode 4.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は各種の電子回路を構成するチップ部品の実装構
造に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a mounting structure for chip components constituting various electronic circuits.

更未の及朱上!1 従来、チップ部品の実装は、第5図に示すように、実装
基板31の表面に各種のチップ部品32を個々に離して
取り付けていた。このため、チップ部品間を接続するた
めの回路パターン30が必要となり、面積の広い実装基
板31を使用しなければならず、電子回路をコンパクト
に構成する際の支障の一つとなっていた。
The unsurpassed progress! 1. Conventionally, chip components have been mounted by attaching various chip components 32 to the surface of a mounting board 31 separately, as shown in FIG. Therefore, a circuit pattern 30 is required to connect the chip components, and a mounting board 31 with a large area must be used, which is one of the obstacles in constructing a compact electronic circuit.

そこで、本発明の課題は、電子回路をコンパクトに構成
することができるチップ部品の実装構造を提供すること
にある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a mounting structure for chip components that allows an electronic circuit to be configured compactly.

課題を解決するための手段 以上の課題を解決するため、本発明に係るチップ部品の
実装構造は、複数の外部電極を備えた複数個のチップ部
品が集合し、各チップ部品の外部電極のうち、回路を構
成する外部電極相互を電気的に接続した状態で、各チッ
プ部品を一体的に密着させて実装したことを特徴とする
Means for Solving the Problems In order to solve the problems above, the chip component mounting structure according to the present invention includes a plurality of chip components each having a plurality of external electrodes. , the chip components are integrally mounted in close contact with each other with the external electrodes constituting the circuit electrically connected to each other.

作用 回路を構成する外部電極相互を電気的に接続した状態で
、各チップ部品を一体的に密着させて実装したため、従
来、外部電極相互の接続に必要であった回路パターンの
引き回しが不要となり、実装基板はその面積が小きくな
る。特に、全てのチップ部品の外部電極相互を直に接続
すれば、実装基板は必ずしも必要としない。
The external electrodes that make up the working circuit are electrically connected to each other, and each chip component is mounted in close contact with each other, which eliminates the need to route circuit patterns, which was conventionally necessary to connect external electrodes to each other. The area of the mounting board becomes smaller. In particular, if the external electrodes of all chip components are directly connected to each other, a mounting board is not necessarily required.

衷農舅 以下、本発明に係るチップ部品の実装構造の実施例を添
付図面を参照して説明する。
Embodiments of the mounting structure for chip components according to the present invention will be described below with reference to the accompanying drawings.

[第1実施例、第1図] 第1図に示すように、実装基板1の上面には、チップ部
品2が一体的に密着して取り付けられている。実装基板
1には、チップ部品2を取り付けるための取付は電極3
が設けられている。チップ部品2は、それぞれ複数の外
部電極4をその端面部に設けている。外部電極4のサイ
ズや位置は組み合わきれるチップ部品2の関係で決定き
れる。
[First Embodiment, FIG. 1] As shown in FIG. 1, chip components 2 are integrally attached to the upper surface of a mounting board 1 in close contact with each other. Mounting board 1 has electrodes 3 for mounting chip components 2.
is provided. Each chip component 2 is provided with a plurality of external electrodes 4 on its end surface. The size and position of the external electrode 4 can be determined depending on the chip components 2 that can be combined.

各チップ部品2は、外部電極4のうち、回路を構成する
外部電極4相互を電気的に接続した状態で、端面を密着
させてブロック状に一体的に組み合わ許れている。外部
電極4相互の接続は半田付は又は導電シートを挟着する
方法あるいは、インターコネクタを介する方法等で行な
われる。
Each chip component 2 is allowed to be integrally assembled into a block shape with the end surfaces of the external electrodes 4 in close contact with each other, with the external electrodes 4 constituting the circuit being electrically connected to each other. The external electrodes 4 are connected to each other by soldering, by sandwiching a conductive sheet, or by using an interconnector.

こうしてチップ部品2を実装した実装基板1は、ラジオ
受侶機等に組み込まれて使用される。
The mounting board 1 on which the chip components 2 are mounted in this manner is used by being incorporated into a radio receiver or the like.

本実施例では、全てのチップ部品2の外部電極相互間を
直に接続させる方法を採用したため、実装基板1に取付
は電極3以外の回路パターンを形成していない。即ち、
チップ部品自身が配線機能を兼ね備えた構造となってい
る。
In this embodiment, since the method of directly connecting the external electrodes of all the chip components 2 to each other is adopted, no circuit pattern other than the electrodes 3 is formed on the mounting board 1. That is,
The chip components themselves have a structure that also has wiring functions.

こうして、実装基板1上のチップ部品2は高密度で実装
できるため、電子回路をコンパクトに構成することがで
きる。
In this way, the chip components 2 on the mounting board 1 can be mounted with high density, so that the electronic circuit can be configured compactly.

チップ部品保護のために、実装後に保護カバーや樹脂コ
ーティングをチップ部品2に施せばより侶頼性、安全性
が高められて好ましい。
In order to protect the chip components, it is preferable to apply a protective cover or resin coating to the chip components 2 after mounting, since reliability and safety can be further improved.

[第2実施例、第2図及び第3図コ 本実施例は、2個のチップ部品を組み合わせて発振回路
を構成した例である。第2図に示すように、実装基板1
1の上面には、3端子のコンデンサ内蔵型圧電発振子1
2と2端子のチップ抵抗13とが端面を密着させて半田
付けにて取り付けられている。実装基板11には、発振
子12の外部電極12a。
[Second Embodiment, Figures 2 and 3] This embodiment is an example in which an oscillation circuit is constructed by combining two chip components. As shown in FIG. 2, the mounting board 1
On the top surface of 1 is a piezoelectric resonator 1 with a built-in three-terminal capacitor.
2 and a two-terminal chip resistor 13 are attached by soldering with their end faces in close contact. On the mounting board 11, an external electrode 12a of the oscillator 12 is provided.

12b、L2cを取り付けるための取付は電極17a、
 17b。
The mounting for attaching electrodes 12b and L2c is electrode 17a,
17b.

1000該軍極17a、 17b、 17cに接続する
回路パターン18a、 18b、 18cが設けられて
いる。発振子12の外部電極12a、12cは抵抗13
の外部電極13a、13bに半田付けにて電気的に接続
している。こうして得られた発振回路の等価電気回路を
第3図に示す。電極17g、17c間に抵抗Rと発振子
が並列関係で接続され、電極17a、 17b間及び電
極17c、 17b間にコンデンサC1,C2が挿入き
れている。
1000 circuit patterns 18a, 18b, and 18c are provided to connect to the military poles 17a, 17b, and 17c. External electrodes 12a and 12c of the oscillator 12 are resistors 13
It is electrically connected to external electrodes 13a and 13b by soldering. An equivalent electrical circuit of the oscillation circuit thus obtained is shown in FIG. A resistor R and an oscillator are connected in parallel between electrodes 17g and 17c, and capacitors C1 and C2 are inserted between electrodes 17a and 17b and between electrodes 17c and 17b.

[他の実施例コ なお、本発明に係るチップ部品の実装構造は前記実施例
に限定するものではなく、その要旨の範囲内で種々に変
形することができる。
[Other Embodiments] Note that the mounting structure of the chip component according to the present invention is not limited to the above-mentioned embodiments, and can be variously modified within the scope of the gist.

前記第1実施例において、チップ部品相互間の密着力だ
けで十分な機械的強度が保証できる環境の下では実装基
板1を使用しない場合もある。
In the first embodiment, the mounting board 1 may not be used in an environment where sufficient mechanical strength can be guaranteed only by the adhesion between the chip components.

また、チップ部品相互間の密着は平面的な結合に限定さ
れるものではなく、第4図に示すように、実装基板20
の上面に複数個のチップ部品21を積み重ねて、外部電
極22により立体的な結合を行なってもよい。
Further, the close contact between chip components is not limited to planar bonding, and as shown in FIG.
A plurality of chip components 21 may be stacked on the top surface of the device, and three-dimensional bonding may be performed using the external electrodes 22.

きらに、チップ部品相互間はすべて隙間なく密着してい
る必要はなく、第4図の上から2段目に示すように空の
領域23を一部有していてもよい。
Furthermore, it is not necessary that the chip components are in close contact with each other without any gaps, and they may have some empty areas 23 as shown in the second row from the top in FIG.

光yしυ1釆 本発明は、複数個のチップ部品の外部IE極相亙を電気
的に接続した状態で、各チップ部品を一体的に密着許せ
て実装したため、回路パターンの引き回しが不要となり
、チップ部品を高密度に実装でき、電子回路をコンパク
トに構成することができる。特に、全てのチップ部品の
外部電極相互間を直に接続すれば、実装基板を省くこと
ができ、より一層のコンパクト化を図ることができる。
In the present invention, the external IE poles of a plurality of chip components are electrically connected and each chip component is mounted in close contact with each other, so there is no need to route circuit patterns. Chip components can be mounted with high density, and electronic circuits can be configured compactly. In particular, if the external electrodes of all chip components are directly connected to each other, a mounting board can be omitted, and further compactness can be achieved.

また、チップ部品の外寸並びに外部電極の形成位置等を
標準化することにより、チップ部品のモジュール化、ユ
ニット化が簡単になり、ICカードラジオ等の高付加価
値商品への適用が可能である。
Furthermore, by standardizing the external dimensions of chip components, the formation positions of external electrodes, etc., it becomes easy to modularize and unitize chip components, and it is possible to apply the present invention to high value-added products such as IC card radios.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1実施例であるチップ部品の実装構
造を示す斜視図である。第2図及び第3図は本発明の第
2実施例を示すもので、第2図は発振回路を構成するチ
ップ部品の実装構造を示す斜視図、第3図は電気等価回
路図である。第4図は本発明の他の実施例を示す正面図
である。第5図は従来のチップ部品の実装構造を示す斜
視図である。 2・・・チップ部品、4・・・外部電極、12・・・チ
ップ部品(圧電共振子)、12a、12b、12cm外
部電極、13・・・チップ部品(チップ抵抗)、13a
、 13b・・・外部電極、21・・・チップ部品、2
2・・・外部電極。 特許出願人  株式会社村田製作所
FIG. 1 is a perspective view showing a mounting structure of a chip component according to a first embodiment of the present invention. 2 and 3 show a second embodiment of the present invention, in which FIG. 2 is a perspective view showing a mounting structure of chip components constituting an oscillation circuit, and FIG. 3 is an electrical equivalent circuit diagram. FIG. 4 is a front view showing another embodiment of the present invention. FIG. 5 is a perspective view showing a conventional chip component mounting structure. 2... Chip component, 4... External electrode, 12... Chip component (piezoelectric resonator), 12a, 12b, 12cm external electrode, 13... Chip component (chip resistor), 13a
, 13b... External electrode, 21... Chip component, 2
2...External electrode. Patent applicant Murata Manufacturing Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 1.複数の外部電極を備えた複数個のチップ部品が集合
し、各チップ部品の外部電極のうち、回路を構成する外
部電極相互を電気的に接続した状態で、各チップ部品を
一体的に密着させて実装したことを特徴とするチップ部
品の実装構造。
1. A plurality of chip components each having a plurality of external electrodes are assembled, and each chip component is integrally brought into close contact with the external electrodes of each chip component that make up the circuit electrically connected to each other. A mounting structure for a chip component, characterized in that the chip component is mounted using the same method.
JP17089190A 1990-06-27 1990-06-27 Chip packaging structure Pending JPH0458587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17089190A JPH0458587A (en) 1990-06-27 1990-06-27 Chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17089190A JPH0458587A (en) 1990-06-27 1990-06-27 Chip packaging structure

Publications (1)

Publication Number Publication Date
JPH0458587A true JPH0458587A (en) 1992-02-25

Family

ID=15913237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17089190A Pending JPH0458587A (en) 1990-06-27 1990-06-27 Chip packaging structure

Country Status (1)

Country Link
JP (1) JPH0458587A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022002260A (en) * 2020-06-22 2022-01-06 株式会社村田製作所 Surface-mounted passive component

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142891A (en) * 1986-12-05 1988-06-15 日本電気株式会社 Chip parts mounting structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142891A (en) * 1986-12-05 1988-06-15 日本電気株式会社 Chip parts mounting structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022002260A (en) * 2020-06-22 2022-01-06 株式会社村田製作所 Surface-mounted passive component

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