JPH045783A - Ic card data read write device and ic card - Google Patents

Abstract

PURPOSE:To improve the transmission speed of a data and to reduce noise at the time of using a non-contact system by providing a microcomputer controlling the read/write of a built-in memory and a direct read/write means with the IC card to use them by switching. CONSTITUTION:In an IC card 1, a microcomputer 12 is provided to control the read/write of a built-in memory 11, and also a direct reading/writing means 13 is provided. When selecting the means 13 by a selection means 12b of this microcomputer 12, a switch request signal is supplied through a switch request means 12c to a reader/writer 2, and a clock supplied from the device 2 is switched to a high-speed clock by a clock switch means 23 to improve the speed of the data transmission while the read/write of the memory is performed rapidly. Along with this, the time of exposing the data to noise from the outside is shortened, and the noise can be reduced in the non-contact system electromagnetic coupling, etc., the IC card.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to microcomputers (hereinafter referred to as C
An IC card with a built-in IC card (called PU), and a data read/write system that receives read data from the IC card and sends data to be written to the IC card. The present invention relates to an IC data reading/writing device and an IC card including an IC data reading/writing device.

[Conventional technology]

Conventionally, in addition to memory, IC cards have a built-in CPU that controls reading/writing data to the memory and performs predetermined arithmetic processing. Some are designed to perform maintenance management, etc. When reading/writing data to/from the memory of such an IC card, the IC card must be connected to a reader/writer (R).
/W) in a contact or non-contact manner, and attach it to the R/W).
A predetermined device such as a host computer and an IC via W
By connecting the card, data is exchanged between the memory in the IC card and the host computer, and data is read/written.

[Problem to be solved by the invention] Currently, the access speed between an IC card with a built-in CPLI and the R/W is limited to the speed of the interface (T/F) between the host computer and the R/W, regardless of whether it is a contact type or a non-contact type. It is matched to the transmission speed. This is because the IC card has no choice but to depend on the processing speed of the built-in CPU. On the other hand, memory cards that do not have a built-in CPU perform DMA transfer with the card using the CPU on the R/W, or use a high-speed I/F to achieve high-speed data transmission.

In short, since IC cards have a built-in CPLI, their access speed or access time is significantly slower than that of memory cards, which is a major drawback. For this reason, when the coupling between the IC card and the R/W is made non-contact by electromagnetic coupling, etc., the longer it takes to access data, the more the noise is affected by noise interference, and the data reliability is affected. customer loyalty will decrease.

Therefore, in view of the above-mentioned conventional problems, it is an object of the present invention to provide an IC card with a built-in CPU that increases the data transmission speed and reduces the influence of noise even if it is a non-contact type. .

[Means for Solving the Problems] In order to solve the above problems, an IC card data reading/writing device made according to the present invention includes a memory 11 and a memory 1. a microcomputer 12 that performs control to read data stored in the memory or write predetermined data to the memory, perform predetermined arithmetic processing, etc.; An IC card 1 has a direct read/write means 13 for reading data stored in the memory, and the IC card 1 is removably installed, receives read data from the IC car 11, and Data read/ that sends data for writing to card 1
a data classification determination means 12 comprising a writing device 2 and for determining data classification by the IC card 1 based on a data classification command inputted from the data reading/writing device 2;
a, a selection means 12b for selectively operating the direct read/write means 13 according to the determination result by the data classification determination means 12a, and the data classification determination means 12.
The data read/write device 2
The data reading/writing device 2 has a switching requesting means 12C that sends a clock switching request signal to the IC card 1, and the data reading/writing device 2 has a switching requesting means 12C for sending a clock switching request signal to the IC card 1. - It is characterized by the presence of a switch switching means 23.

Further, as shown in the basic configuration diagram of FIG. 1, the IC card according to the present invention includes a memory 11, control for reading out data stored in the memory 11 or writing predetermined data into the memory 11, and a predetermined control function. a microcomputer 12 that performs arithmetic processing, etc.; a direct read/write means 13 that directly writes data to the memory 11 or reads data stored in the memory without using the microcomputer 12; data classification determining means 12a that determines the data classification based on a data classification command input from the data classification command; and selecting means 12b that selectively activates the direct reading/writing means 13 based on the determination result of the data classification determining means 12a.
and a switching requesting means 12c which sends a clock switching request signal to the outside based on the determination result by the data classification determining means 12b.

[Operation] In the above configuration, the microcomputer I2 in the IC card 1 reads/writes data from/to the memory 11.
It performs writing control and predetermined calculation control. Further, the direct reading/writing means 13 is operated by the selecting means 12b according to the data classification determination result performed by the data classification determining means 12a based on the data classification command inputted from the data reading/writing device 2. Furthermore, the switching requesting means 12
C sends a clock switching request signal to the data reading/writing device 2, and in response to this, the clock switching means 23 in the data reading/writing device 2 switches the speed of the clock to the IC card l. Therefore, the data transmission speed for reading and writing the IC card in the IC card data reading/writing device can be switched between high and low depending on the type of data.

In addition, the direct reading/writing means 1 in the IC card 1
3 is selectively operated by the selection means 12b according to the data classification determination result performed by the data classification determination means 12a based on the data classification command inputted from the outside. Then, based on the judgment result by the data classification judgment means 12a, the switching requesting means 12C sends a clock switching request signal to the outside, so that reading is performed using a clock manually inputted from the outside in response to the switching request signal. And the data transmission speed for writing can be switched high or low depending on the type of data.

Therefore, data can be read from or written to the memory 11 at a higher speed than when all data is read from or written to the memory 11 by the microcomputer 12 in the IC card.

〔Example〕

Hereinafter, embodiments of the present invention will be described based on the drawings.

FIG. 2 shows an embodiment of the IC card according to the present invention. In the figure, 1 is a non-contact type IC card that does not have a contact terminal, and the IC card 1 is internally configured with an EPROM, EEPROM, etc. data memory 11,
CPU 12, direct memory access controller (hereinafter referred to as DMAC) 13, 110 switching circuit 14, serial/parallel conversion circuit 15, parallel/serial conversion circuit 16, demodulation circuit 17, modulation circuit 18, and reception coil 19 , a transmitting coil 20 , a rectifying smoothing and voltage stabilizing circuit 21 , and an oscillating circuit 22 .

In addition, 2 is a reader/writer (R/W), and the R/W2
is an I10 switching circuit 2I, a command discrimination circuit 22, a timing control circuit 23, a buffer memory 24, an interface 25, and a serial/parallel conversion circuit 26.
, a parallel/serial conversion circuit 27, and a demodulation circuit 28
, a modulation circuit 29 , a receiving coil 30 , and a transmitting coil 3
1 and an oscillation circuit 32.

In the above configuration, when the IC card 1 is attached to the R/W 2 in a non-contact manner, the transmitter coil 31°20 and the receiver coil 19,30 are electromagnetically coupled to each other, and changes in the magnetic field generated by the transmitter coil are received. The coil extracts the induced current and transmits and receives data and supplies power without connecting. In addition to electromagnetic coupling, optical coupling and microwaves can also be used to transmit and receive data without contact.

The CPU 12 in the IC card 1 outputs a read/write control signal (hereinafter referred to as an R/W signal) and an address signal to the memory 11.
Data of 1 is input/output to the I10 switching circuit 14. Furthermore, the CPU 12 has a DMA in its internal microprogram.
It has a built-in C program.

In addition, DMACl3 provides an R/W signal to the memory 11.
An address signal is output, and data in the memory 11 is directly input/output to the I10 switching circuit 14.

The I10 switching circuit 14 outputs a request signal for direct memory access (hereinafter referred to as DMA) to the DMAC 13, and
MACl3 outputs a DMA permission signal to the I10 switching circuit 14, which causes the 110 switching circuit 14 to
Reading/writing data via UI 2 and CP
Data reading/writing to/from memory 11 is switched directly without going through U12. Parallel data from the memory 11 is inputted to the parallel/serial conversion circuit 16 via the 1 to 110 switching circuit 14 and converted to serial data, which is further modulated by the modulation circuit 18 and sent to the transmitting coil 20.
is input.

On the other hand, the serial data received by the receiving coil 19 is demodulated by the demodulation circuit 17 and converted into parallel data by the serial/parallel conversion circuit 15.
4 is input. Further, the power received by the reception coil 19 is rectified, smoothed and voltage stabilized by a rectification, smoothing and voltage stabilization circuit 21, and then supplied to each part. Further, the oscillation circuit 22 provides an operating clock to the CPUI 2 and DMACl3.

The memory 11 includes a general-purpose data area 111 that stores various general-purpose data such as processing results and temporary data, and an identification code (
It has a registration data area 112 for registering predetermined data such as ID). Specifically, the registration data (card setting data) includes: - Starting up the IC card 1 from a personal computer or data management device, and configuring the CP in the IC card 1.
Data for activating IJ12, ■Validity f1'
ID data for processing such as fE authentication, ■Memory 1
There is data for managing and setting the system in the IC card 1, and general-purpose data includes daily report data stored in the memory 11 in the IC card 1. In short, the registration data is so-called card control data that configures the system of the rC card 1, and the general-purpose data is data that is generally not related to the contents of the IC card 1 and is exchanged between the IC card 1 and the device after the above settings are completed. It is. In addition, DMACl3, as shown by the dotted line in the same figure,
It may be composed of the CPU 12 and one chip.

In the R/W 2, the R/W signal input from the host computer 3 via the interface 25 is input to the buffer memory 24 and the f10 switching circuit 21. Also, read/write data from the host computer 3 is transferred to the ■/○ switching circuit 21 via the buffer memory 24.
input and output to. Then, the memory 11 in the IC card 1
When reading out data stored in the memory 11, the reception coil 30 receives the data in the memory 11, and the demodulation circuit 2
8 demodulates this data, converts it into parallel data in the serial/parallel converter circuit 26, and sends it to the command discrimination circuit 22.
The signal is input to the I10 switching circuit 21 via the buffer memory 24 and the interface 25, and is output to the pothos computer 3 via the buffer memory 24 and interface 25. Also, data can be stored in memory 11.
When writing data and outputting R/W signals to the IC card 1, the data and R/W signals from the host computer 3 are transferred to the interface 25 and the buffer memory 2.
4. The signal is input to the parallel/serial circuit 27 via the I10 switching circuit 21 for serial conversion, further modulated by the modulation circuit 29, and output to the transmitting coil 31.

On the other hand, the address signal of the memory 11 from the host computer 3 is transmitted to the I10 switching circuit 2 via the interface 25, the timing control circuit 23, and the buffer memory 24.
1L: Input and output to the IC card 1 through the parallel/serial conversion circuit 27, modulation circuit 29, and transmission coil 31.

Based on the clock from the oscillation circuit 32, the timing control circuit 23 selectively outputs two types of clocks: a normal clock at a normal speed and a high speed clock at a high speed. When the normal clock is used, the CPU 12 reads data from/to the registered data area 112 of the memory 11.
Writing is performed, and when using a high-speed clock, reading/writing is performed to the general-purpose data area 111 by DMA.

In addition, the command discrimination circuit 22 is connected to an I
By decoding the speed conversion request signal output from the C card 1 and inputting the decoding result to the timing control circuit 23, the clock speed from the timing control circuit 23 is set. In addition, I10 switching circuit 14
．． 21 constantly monitors the clock speed to prevent timing deviation.

In order to do the above, commands for the IC card 1 such as "Write registered data", "Write general data 1", "Read registered data", and "Read general data" are prepared in advance. By decoding these commands with the IC card 1, it is possible to distinguish between registered data and general-purpose data, and between reading and writing. IC card 1 makes a speed switching request to R/W as described above, and for this purpose, IC card 1
The output circuit from the IC card uses a flip-flop, and sends out an output signal so that when the IC card performs activation (reset processing of the card such as program glue setting of the CPU 12), it is performed at the registered data rate. At this time, a signal is selected that does not overlap with other commands to prevent malfunction. The transmission speed between the IC card 1 and the R/W after the IC card 1 is activated is normally low, so the speed switching command should be used to distinguish between read and write general-purpose data on and off. can be controlled with.

FIG. 3 is a flowchart showing the work (including some processing of other circuits) executed by the CPU 12 in the rc card 1. The CPU 12 is activated when the IC card 1 is installed in the R/W 2, First, in step S1, the IC card 1 is activated, and the read/write speed of the memory 11 is set to the normal speed for reading/writing via the CPUI 2 to the timing control circuit 23, and the validity of the IC card 1 is verified. ensure that

Next, in step S2, the R/W input along with the data classification command is input from the host computer 3 via the R/W 2.
Based on the W signal, it is determined whether data is to be read or written to the memory 11, and if it is a read process, the process advances to step S3.

In step S3, a read command and an address signal are received from the R/W 2 via the receiving coil 19, the demodulating circuit 17, the serial/parallel converting circuit 15, and the I10 switching circuit 14. Next, in step S4, it is determined whether the data to be read is general-purpose data or registered data based on the data classification command, and if it is registered data, the process proceeds to step S5, where the registered data in the memory 11 is sent from the CPU 12. The area 112 is accessed, and in the next step S6, data at the accessed address is taken in, and is output to the R/W 2 via the I10 switching circuit 14, parallel/serial conversion circuit 16, modulation circuit 18, and transmission coil 20. let

As a result of the determination in step S4 above, if the data to be read is general-purpose data, the process advances to step S7, and the CPU 12 uses the DMA
Run the program. As a result, the CPU 12 becomes standby, and ownership of each lot of the R/W signal, address signal, and data is switched from the CPU 12 to the DMACl3.

That is, by executing step S4, the CPUI 2 performs the following operations based on the data classification command input together with the read command from the host computer 3, which is an external device.
DMACl3 as the direct read/write means
It functions as a means of selection that selectively activates the

Next, the process advances to step S8, and a speed switching request signal (high-speed clock request signal) is output to the R/W 2. Thereafter, in step S9, the R/W 2 receives this request signal with the receiving coil 30, and inputs it to the command discrimination circuit 22 via the demodulation circuit 28 and the serial/parallel conversion circuit 26, and decodes it. Then, in step S10, the timing control circuit 23 switches from normal speed to high speed clock oscillation. In the next step Sll, it is determined whether or not the speed has been switched. If the determination is YES, in step SL2, the read address signal is read from the R/W 2 to the IC card l and sent to the parallel/serial conversion circuit 27 and the modulation circuit 29. , is output via the transmitting coil 31. Next, the process advances to step S13, where DMACl3
accesses the general-purpose data area 111 of the memory 11 using the sea address signal, and outputs the data recorded there to the R/W 2 via the parallel/serial conversion circuit 16, modulation circuit 18, and transmission coil 20. . The above steps 810 to S13 are DMA transfer processing.

Then, in step S14, after sending the data, R
/W2 outputs a speed switching request signal to switch to normal speed again, in step S15 the command discrimination circuit 22 decodes this, and in step S16 the timing circuit 23 uses the decoded output to generate normal clock oscillation at normal speed. Switch to Then step S17
, it is determined whether or not the speed has been switched to normal speed, and if YES, the process proceeds to step S33, and the DMAC 13
It outputs a DMA transfer processing end signal and a CPU active signal to the CPU 12, ends the DMAC program, and passes control to the CPU 12. As a result, ownership of the lotus is returned to CP.
U12, and the main program is executed.

If the result of the determination in step S2 is that data is to be written to the memory 11, the process advances to step 518. In this step S18, a write command and an address signal are received from the R/W 2 via the receiving coil 19, the demodulating circuit 17, the serial/parallel converting circuit 15, and the I10 switching circuit 14. Next, in step S19, it is determined whether the write data is registered data or general-purpose data, and if it is registered data, the process advances to step S20.
The registered data area 112 of the memory 11 is accessed, and in the next step S21, the write data from the host computer 3 is inputted via the R/W 2, and the receiving coil 19, demodulation circuit 17, serial/parallel conversion circuit 15, The write data is inputted through the ■/○ switching circuit 14 and written to the address accessed above.

Further, as a result of the determination in step SL9, if the data to be read is general-purpose data, the process proceeds to step S22, where the program branches to the DMA program and the main program is stopped. This puts CPUI 2 on standby and R/
The ownership of each lotus of W signal, address signal, and data is CP.
Switches from U12 to DMACl3. That is, by executing step S19, the CPU 12 functions as a selection means for selectively operating the DMAC 13 as the direct read/write means based on the data classification command input together with the write command 'from the host computer 3, which is an external device. ing.

Next, the process advances to step S23, and the DMAC 13 outputs a speed switching request signal (high speed clock request signal) to the R/W 2. The R/W 2 receives the request signal with the receiving coil 30, and sends the request signal to the command discriminating circuit 22 via the demodulating circuit 28 and the serial/parallel converting circuit 26 in step S24.
and decode it. And step S25
At this point, the timing control circuit 23 switches from normal speed to high speed clock oscillation. In the next step S26, it is determined whether or not the speed has been switched. If YES, in step S27, the write address signal and write data are transferred from the R/W 2 to the IC card l by the parallel/serial conversion circuit 27 and the modulation circuit. 29, transmitting coil 3
1. Next, the process proceeds to step S28, where the DMACl3 accesses the general-purpose data area 111 of the memory 11 based on the address signal, and writes and stores the write data. The above steps 325 to S28 are D
This is MA transfer processing.

Then, in step S29, after writing the data, a speed switching request signal is output to the R/W 2 to switch to the normal speed again, the command discrimination circuit 22 decodes this in step S30, and the timing circuit 23 decodes this in step S31. This decode output switches to normal clock oscillation at normal speed. and step S
32, it is determined whether the speed has been switched to normal speed or not, and YE
If S, go to step 333, and DMACl3 is CPU
It outputs a DMA transfer processing end signal and a CPU active signal to I2, ends the DMAC program, and passes control to the CPU 12. As a result, the ownership of the lotus becomes CPtJ12's again, and the main program is executed.

In the above embodiment, a non-contact type IC card has been described, but a contact type IC card may be used. However, when applied to a contactless IC card, the time that data exists in the space between the IC card and the transmitting/receiving means is shortened.
The reliability of data against external noise etc. is improved.

〔effect〕

As explained above, according to the present invention, the direct reading/writing means directly reads/writes data to/from the memory regardless of the microcomputer, so reading/writing data from/to the memory is not possible. , compared to what is done by a microcomputer, and it is also possible to read/write a large amount of data in a short time, so even if it is a contactless IC card, the data will not be affected by external noise. Since the exposure time is shortened, the reliability of data against external noise and the like is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an IC card data read/write device and an IC card according to the present invention, FIG. 2 is a diagram showing an embodiment of the IC card data read/write device according to the present invention, and FIG. The figure is a flowchart diagram showing the work performed by the CPLI in FIG. DESCRIPTION OF SYMBOLS 1...IC card, 11...Memory, 12...Microcomputer (CPU), 12a...Data classification determination means, 12b...Selecting means, 12c...Switching requesting means, 13...・Direct reading/writing means (
DMAC), 2... Data reading/writing device (reader/writer), 23... Clock switching means.

Claims (2)

[Claims] (1) A memory, a microcomputer that reads data stored in the memory, controls writing predetermined data to the memory, performs predetermined arithmetic processing, etc., and directly writes data to the memory without using the microcomputer. an IC card having a direct read/write means for writing data to or reading data stored in the memory; , a data reading/writing device that sends data for writing to an IC card, and the IC card determines data classification based on a data classification command input from the data reading/writing device. a data classification determination means for determining the data classification, a selection means for selectively operating the direct reading/writing means according to the determination result by the data classification determination means, and a selection means for selectively operating the direct reading/writing means according to the determination result by the data classification determination means. a switching requesting means for sending out a clock switching request signal, and the data reading/writing device has a clock switching means for switching the clock speed in response to a switching request signal from the switching requesting means of the IC card. An IC card data reading/writing device characterized by: (2) A memory, a microcomputer that performs control to read data stored in the memory or write predetermined data to the memory, perform predetermined arithmetic processing, etc.; direct reading/writing means for writing data to or reading data stored in the memory; data classification determining means for determining data classification based on a data classification command input from the outside; The data processing apparatus further comprises a selection means for selectively operating the direct read/write means according to a determination result by the determination means, and a switching request means for transmitting a clock switching request signal to the outside according to a determination result by the data classification determination means. An IC card featuring