JP2003023366A - Data carrier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that it is difficult to provide long-distance communication because of the decrease of an internal voltage caused by the load switch ON of a load modulation system in the up link of a data carrier. SOLUTION: EOF in a transmitting instruction signal 50 from a reader/writer is detected and a useless demodulation circuit 3 during the up link period of the data carrier is stopped so that total internal resistance can be decreased, namely, a degree of decrease in the internal voltage according to a time constant in the ON state of a transistor 6 for load switch is relaxed. Thus, the data carrier can be operated by low power and long-distance communication is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data carrier, and more particularly, to an improvement for reducing the power consumption in the uplink from the data carrier to the reader / writer to achieve long distance communication.

[0002]

2. Description of the Related Art Conventionally, when responding to a reader / writer from a data carrier, that is, at the time of uplink, a load modulation type modulation circuit using a load switch is used.

FIG. 8 shows a conventional data carrier. Reference numeral 1 is an antenna coil that transmits and receives radio waves to and from an external reader / writer (not shown), 2 is a rectifier circuit that rectifies the induced voltage of the antenna coil 1, 3 is a demodulation circuit that demodulates, 14 is a reference potential generation circuit, 4 Is a control circuit having a signal output function for processing an input signal from the demodulation circuit 3 and performing control at the time of uplink, 6 is a load switch transistor operated by a control signal from the control circuit 4, and 5 is the transistor 6 It is a modulation circuit composed of a load.

The downlink logic 45 in the control circuit 4 is a logic circuit for processing the demodulated signal, the memory 47 is an area for storing data, and the uplink logic 46 is a control signal to the modulation circuit 5. Each of the logics operates according to the input of the CLK generation circuit 48.

The transmission / reception operation of the conventional data carrier will be described separately for the downlink and the uplink. First, during downlink, the transmission instruction signal S1 from the reader / writer is received by the antenna coil 1 by electromagnetic induction and rectified by the rectifier circuit 2. The signal data rectified by the rectifying circuit 2 is restored by the demodulating circuit 3 from the modulated wave, that is, demodulated. The gate of the demodulation circuit operation control transistor 13 of the demodulation circuit 3 is always supplied with the potential from the reference potential generation circuit 14, and the demodulation circuit 3 is in the operating state.

Thereafter, the downlink logic 45, which operates according to the CLK generation circuit 48, carries out the processing, and the reading / writing operation to / from the memory 47 is carried out according to the instruction content of the transmission instruction signal.

At the time of uplink transmission from the reader / writer to the data carrier, a response signal in response to the reader / writer is determined and output by the uplink logic 46 that operates according to the CLK generation circuit 48, and the load in the modulation circuit 5 is performed. A signal wave is converted into a modulated wave, that is, modulation is performed by controlling the switching transistor 6 to be turned on and off, and the antenna coil 1 transmits a response signal to the reader / writer.

The relationship between the internal voltage of the conventional data carrier and the characteristics of the load switch that perform such a transmission / reception operation will be described with reference to FIGS. 4, 5 and 8.
First, FIG. 4 shows the relationship between the communication distance between the data carrier and the reader / writer and the voltage that can be supplied at that distance. Generally, the shorter the communication distance is, the higher the supply voltage is, and the longer the communication distance is. The possible voltage is reduced.

FIG. 5 shows the relationship between the internal voltage of the data carrier and the load switch. In FIG. 8, when the load switch transistor 6 is in the OFF state during uplink,
The internal voltage after the rectifier circuit 2 has a voltage level rectified by the rectifier circuit 2 and exhibits a characteristic like A1. Next, the load switch transistor 6 is turned on during uplink.
In this state, the load of the modulation circuit is turned on and the input voltage level of the rectifier circuit 2 is reduced, so that the rectifier circuit 2 is turned off and the voltage supply from the reader / writer to the inside of the rectifier circuit 2 and thereafter is interrupted.

Therefore, the internal voltage after the rectifier circuit 2 is consumed according to the time constant of the sum of the internal resistance of the demodulation circuit and the internal resistance of the control circuit 4 other than the demodulation circuit and the smoothing capacitance, so that A
2 shows a characteristic that the internal voltage sharply decreases.

The decrease of the internal voltage due to the time constant causes a margin to the operation lower limit internal voltage like B in the case of short distance communication with the reader / writer, that is, during short-distance communication capable of supplying sufficient voltage. However, the distance to the reader / writer is long, that is, it affects the lower limit of operation like A2 during long-distance communication.

[0012]

As described above, the conventional data carrier has a problem that it is difficult to realize long-distance communication due to the decrease of the internal voltage due to the load modulation type load switch being turned on during the uplink.

It is an object of the present invention to realize an excellent data carrier capable of long-distance communication on the uplink in the data carrier using the load modulation method.

[0014]

To achieve this object, the data carrier of the present invention reduces the total internal resistance, that is, the internal voltage is reduced by stopping unnecessary downlink circuits during uplink. It has a configuration for relaxing the degree of decrease according to the time constant.

With this configuration, the load switch is turned on.
Since the decrease of the internal voltage can be mitigated even in the state,
Long-distance communication can be realized without sacrificing the communication distance of the data carrier.

The data carrier according to claim 1 of the present invention rectifies the voltage induced in the antenna to cover the necessary electric power, and at the same time, the signal received from the antenna is demodulated by the demodulation circuit to recognize the instruction content. In a data carrier for accessing the memory and transmitting the contents read from the memory from the antenna via a load modulation type modulation circuit, a control means is provided for stopping the demodulation circuit during an uplink period in which the transmission is executed. It is characterized by

A data carrier according to claim 2 of the present invention is the data carrier according to claim 1, wherein the control means includes an end part (EOF) in a transmission instruction signal transmitted in a downlink period of a transmission instruction to the data carrier. It is characterized by comprising a detection circuit for detecting, and an instruction circuit for stopping the demodulation circuit in the uplink period by using the output of the detection circuit as a trigger.

A data carrier according to a third aspect of the present invention rectifies a voltage induced in an antenna to cover required power, demodulates a signal received from the antenna by a demodulation circuit, and outputs the signal from the demodulation circuit. The signal is processed by the downlink logic, the instruction content from the downlink logic is recognized, the memory is accessed, and the content read from the memory is transmitted from the antenna via the load modulation type modulation circuit. And a control means for stopping the downlink logic during an uplink period in which the transmission is performed.

A data carrier according to a fourth aspect of the present invention is the data carrier according to the third aspect, wherein the control means includes an end portion (in the transmission instruction signal transmitted in the downlink period of the transmission instruction from the reader / writer to the data carrier). A detection circuit for detecting EOF) and an instruction circuit for stopping the downlink logic by using the output of the detection circuit as a trigger are provided.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. In addition, FIG. 8 showing a conventional example
Those having the same operation as will be described with the same reference numerals.

(Embodiment 1) FIGS. 1 to 5 show (Embodiment 1) of the present invention. FIG. 1 shows a data carrier of (Embodiment 1), and compared with FIG. 8 of a conventional example, an EOF constituting a control means for stopping the demodulation circuit 3 in an uplink period in which the data carrier responds to a reader / writer.
A detection circuit 7, a counter 8, a NAND circuit 12, a switch 15 and the like are added.

First, the transmission instruction signal transmitted from the reader / writer to the data carrier will be described. FIG. 3 shows an example of a packet format of a transmission instruction signal transmitted from the reader / writer to the data carrier.

The transmission instruction signal 50 is a transmission instruction signal head portion 51 (hereinafter referred to as SOF51) which means the start of the transmission instruction signal.
And a transmission instruction signal end unit 53 (hereinafter referred to as EOF 53) that means the end of the transmission instruction signal, and the SO
The instruction content 52 is sandwiched between the F51 and the EOF 53.

In FIG. 1, E provided in the control circuit 4
The OF detection circuit 7 detects the end portion, that is, EOF, in the transmission instruction signal transmitted from the reader / writer to the data carrier.

The counter 8 outputs a demodulation circuit stop start signal 9 and a demodulation circuit stop end signal 10 by using the output from the EOF detection circuit 7 as a trigger. Specifically, the 0th internal counter is output as the demodulation circuit stop start signal 9, and the nth internal counter that includes the uplink response signal period and can be arbitrarily set according to each communication protocol is output as the demodulation circuit stop end signal 10. .

The NAND circuit 12 receives the demodulation circuit stop start signal 9 and the signal obtained by inverting the demodulation circuit stop end signal 10 by the inverter 11 and outputs a demodulation circuit operation stop signal 12A.

The switch 15 is provided in the path from the reference potential generating circuit 14 to the gate of the demodulation circuit operation control transistor 13, and is controlled by the demodulation circuit operation stop signal 12A to prevent unnecessary demodulation circuit 3 at the time of uplink. It is configured to stop.

A control function for stopping the unnecessary demodulation circuit 3 at the time of uplink will be described with reference to FIG. Here, the EOF detection circuit 7 has a logical configuration that outputs "H" when EOF is detected and outputs "L" when it is not detected.

The counter 8 is normally "L" output, and the "H" output from the EOF detection circuit 7 is used as a trigger to output "H" as the demodulation circuit stop start signal 9 at the 0th time of the internal counter, and the uplink response signal period. , The internal counter n which can be arbitrarily set according to each communication protocol is output as "H" as the demodulation circuit stop end signal 10, and the "H" output of the demodulation circuit stop start signal 9 is held, and the demodulation circuit is held. The logical configuration is such that it is reset to "L" when the stop end signal 10 becomes "H" output.

In the demodulation circuit operation control transistor 13, the demodulation circuit operation stop signal 12A from the NAND circuit 12 which receives the inverted logic signal 11A of the demodulation circuit stop start signal 9 and the demodulation circuit stop end signal 10 is "H" logic. At this time, the switch 15 supplies the potential from the reference potential generating circuit 14 so that the drain-source is turned on, and the output signal 12A is at the "L" logic.
Therefore, the demodulation circuit operation stop signal 12A is supplied with the "L" potential and turned off.

With this configuration, the transmission instruction signal from the reader / writer is received by the antenna coil 1 by electromagnetic induction at the time of downlink, but here, the CLK generating circuit 48 causes the uplink logic 46 to operate constantly. Since the control signal to the load switch transistor 6 is “H” output, the load switch transistor 6 is
Is OFF, and the rectifier circuit 2 is turned ON to rectify the signal data.

Next, the demodulation circuit 3 turns on the switch 1 when the demodulation circuit operation stop signal 12 from the control circuit 4 is "H".
5 supplies the potential from the reference potential generation circuit 14 to the demodulation circuit operation control transistor 13, that is, demodulates from the operating state, performs processing by the downlink logic 45, and stores the memory according to the instruction content of the transmission instruction signal. 47
Read and write to. After that, the EOF detection circuit 7 detects EOF in the transmission instruction signal and outputs "H", and the counter 8 receives this signal and outputs and holds the demodulation circuit stop start signal 9 "H" logic at the 0th time of the internal counter. Demodulation circuit stop end signal 10 "L" output inverted signal 11A "H"
By this NAND, the demodulation circuit operation stop signal 12A becomes "L", and this "L" level is input to the demodulation circuit operation control transistor 13 as it is through the switch 15, and the demodulation circuit operation control transistor 13 is turned off, that is, the demodulation circuit 3 Is stopped. Further, the uplink logic 46, which is constantly operating by the CLK generation circuit 48, determines a response signal in response to the reader / writer according to the instruction content of the transmission instruction signal, and outputs a signal for controlling the ON / OFF switching of the load switch transistor 6. Then, the modulation circuit 5 performs modulation, and the antenna coil 1 transmits a response signal to the reader / writer. During the period from the EOF in this transmission instruction signal to the waiting time and response signal, the demodulation circuit operation control transistor 13 is OF
F, that is, the operation of the demodulation circuit 3 is stopped.
Thereafter, in the control circuit 4, the demodulation circuit stop end signal 10 "H" is generated at the n-th internal counter (which can be arbitrarily set according to each communication protocol) including the waiting time between the transmission instruction signal and the response signal and the response signal period. Output the inverted signal 11A
The demodulation circuit operation stop signal 12A becomes "H" by the NAND of "L" and the "H" logic of the demodulation circuit stop start signal 9, and the potential of the reference potential generation circuit 14 is changed via the switch 15 to the demodulation circuit operation control transistor 13. , The demodulation circuit operation control transistor 13 is turned on, that is, the demodulation circuit 3 is in a normal operation state. Further, the counter 8 receives the demodulation circuit stop end signal 10 "H", and the "H" output of the demodulation circuit stop start signal 9 is reset to be "L" logic.

The relationship between the internal voltage of the data carrier and the characteristics of the load switch in one embodiment of the present invention that performs such a transmission / reception operation will be described. First, at the time of downlink, since the control signal from the uplink logic 46 to the load switch transistor 6 is “H”, the load switch transistor 6 is OFF and the rectifier circuit 2 is ON. Further, the EOF detection circuit 7 outputs the "L" logic because the non-EOF is detected. The demodulation circuit stop start signal 9 is "L", the demodulation circuit stop end signal 10 is "L", and the inverted signal 11A is Since it is "H", the demodulation circuit operation stop signal 12A is "H",
That is, since the demodulation circuit operation control transistor 13 is in the ON state, the demodulation circuit 3 is in the normal operation state.

Therefore, the total internal resistance after the rectifier circuit 2 is the sum of the internal resistance of the control circuit 4 and the internal resistance of the demodulation circuit 3, and the internal voltage after the rectifier circuit 2 is always constant. Next, the relationship and operation between the internal voltage and the load switch during uplink will be described.

FIG. 5 is a diagram showing the relationship between the internal voltage of the data carrier and the load switch according to the present invention and the related art.
First, in FIG. 2, from the waiting time before the uplink,
Since the EOF detection circuit 7 detects the EOF in the transmission instruction signal and the demodulation circuit 3 is stopped according to the above operation, the total internal resistance after the rectification circuit 2 is only the internal resistance of the control circuit 4 excluding the demodulation circuit 3. Becomes When the load switch transistor 6 is OFF in the state of this internal resistance, the rectifier circuit 2 is in the ON state, the voltage supply to the inside after the rectifier circuit 2 is constant, and the internal voltage shows a characteristic like C1.

Next, the load switch transistor 6 is turned off.
At N, the resistance in the modulation circuit 5 becomes conductive and the input voltage level of the rectifier circuit 2 decreases, so the rectifier circuit 2 is turned off, the voltage supply to the inside after the rectifier circuit 2 is interrupted, and the internal voltage is controlled. It is consumed according to the time constant of the internal resistance and the smoothing capacitance of the circuit 4, and exhibits a characteristic like C2. Since the total internal resistance at this time excludes the internal resistance of the demodulation circuit 3 from the conventional product, the decrease of the internal voltage is gentler than that of the conventional A2 characteristic, and the operation is possible even at a lower internal voltage. Become. Since it is possible to operate with a low internal voltage, that is, it is possible to operate with a low supply voltage, it becomes possible to perform long-distance communication with the reader / writer as compared with the conventional product as shown in FIG.

The instruction circuit for stopping the demodulation circuit 3 in the uplink period by using the output of the EOF detection circuit 7 as a trigger is composed of the counter 8, the NAND circuit 12, the switch 15, etc., but is not limited to this. Absent.

(Embodiment 2) FIGS. 6 and 7 show (Embodiment 2) of the present invention. In the first embodiment, the demodulation circuit is configured to be stopped during the uplink period, but in the second embodiment, the downlink logic 45 is configured to be stopped during the uplink period. And downlink logic 4 during the uplink period
As a control means for stopping 5, the EOF detection circuit 37, the counter 38, the AND circuit 42, the NAND circuits 43 and 44.
Etc. are provided.

In FIG. 6, 31 is an antenna coil for transmitting and receiving radio waves to and from a reader / writer, 32 is a rectifying circuit for rectifying, 33 is a demodulating circuit for demodulating, and 34 is a demodulating circuit 33.
Control circuit having a function of outputting a response signal for processing the transmission instruction signal from the control circuit 36 and controlling the modulation circuit 35, 36 is a load switch transistor operated by the control signal from the control circuit 34, and the modulation circuit 35 is the transistor 36. And load.

Further, in the control circuit 34, a downlink logic 45 for processing the signal from the demodulation circuit 33, a memory 47 for reading and writing data according to the instruction content,
Uplink logic 46 that controls the signal to modulation circuit 35, EOF detection circuit 37 that detects the end of the transmission instruction signal transmitted from the reader / writer to the data carrier, that is, EOF, and EOF detection circuit 37 The output is used as a trigger, the internal processing period of the downlink is included, and the arbitrarily set internal counter n1 is output as the output signal 39, and the response signal period of the uplink is included.
Internal counter n2 that can be set arbitrarily according to each communication protocol
The counter 38 having a function of outputting the second time as the output signal 40, and the inverter 4 for the output signal 39 and the output signal 40.
The AND circuit 42 is provided with the inverted logic inverted by 1 as an input and outputting the output signal 42A.

The downlink logic 45 is CL
The output signal of the NAND circuit 43 (downlink logic stop signal) 43A which operates by receiving the output of the K generation circuit 48 and the output signal of the AND circuit 42 (downlink logic stop signal) 42A is used as a control signal.

The uplink logic 46 operates with the output signal 44A of the NAND circuit 44 to which the output of the CLK generation circuit 48 and the inverted signal of the output signal 42A of the AND circuit 42 are connected as the control signal.

That is, it has a configuration in which unnecessary logics are switched and stopped at the time of uplink and at the time of downlink. With this configuration, a control function capable of stopping an unnecessary logic circuit at the time of uplink and downlink will be described with reference to FIG.

Here, the EOF detection circuit 37 has a logical configuration that outputs "H" when EOF is detected and outputs "L" when it is not detected. The counter 38 normally outputs "L" and outputs "H" from the EOF detection circuit 37. "The output is a trigger, and the internal counter n1st time that is arbitrarily set to include the internal processing period of the downlink is output as the" H "output signal 39, and the response signal period of the uplink is included. The internal counter n that can be set to
A logic configuration in which the "H" output is set to 0, the "H" output of the output signal 39 is held, and is reset to "L" when the output signal 40 becomes the "H" output, downlink logic stop The signal 43A is the output of the CLK generation circuit 48 and the output signal 42A of the AND circuit 42, and the downlink logic stop signal 44A is the NAND output of the output of the CLK generation circuit 48 and the inverted signal of the output signal 42A. 45 and logic 4 for uplink
Both 6 use a configuration in which they operate when the downlink logic stop signal 43A and the uplink logic stop signal 44 are "H" and stop when they are "L".

First, the transmission instruction signal from the reader / writer is received by the antenna coil 31 by electromagnetic induction. Here, the load switch transistor 3 is received from the control circuit 34.
Since the control signal to 6 is "H" output, the load switch transistor 36 is in the OFF state, and the rectifying circuit 32 is turned on to rectify the signal data.

Next, the demodulation circuit 33 performs demodulation and the control circuit 3
Processing is performed at 4. In the control circuit 34, the downlink logic 45 performs processing in accordance with the transmission instruction content, and then the memory 47 performs a read / write operation. Further, the EOF detection circuit 37 detects the EOF in the transmission instruction signal through the downlink logic 45 and outputs “H”, and the counter 3
8 receives this signal and outputs the output signal 3 at the first time of the internal counter n1 which is arbitrarily set including the internal processing period of the downlink.
9 “H” logic is output and held, and output signal 42 is output by ANDing with output signal 40 “L” output inverted signal 41A “H”
A becomes "H", and downlink logic stop signal 4
3A is "L" output by the CLK generation circuit 48 and the output signal 42A of the AND circuit 42, that is, the downlink logic 45 is in a stopped state.

Further, the logic stop signal 44 for uplink is used.
A is an "H" output by NAND of the signal of the CLK generation circuit 48 and the inverted signal of the output signal 42A of the AND circuit 42, that is, the uplink logic 46 is in the operating state.

Next, the control circuit 34 determines a response signal in response to the reader / writer according to the instruction content of the transmission instruction signal, and outputs a signal for controlling the ON / OFF switching of the load switch transistor 36 by the uplink logic 46. The modulation circuit 35 performs modulation, and the antenna coil 31 transmits a response signal to the reader / writer. During the period from the arbitrarily set waiting time including the downlink internal processing period after EOF in the transmission instruction signal to the response signal, the downlink logic stop signal 43A outputs “L”, that is, the downlink logic 45 When stopped, the uplink logic stop signal 44A is "H".
The output, ie the uplink logic 46, is active.

Thereafter, in the control circuit 34, from the waiting time arbitrarily set to include the downlink internal processing period after EOF in the transmission instruction signal, the internal counter n2 times including the response signal period (each communication protocol) Output signal 40 "H" with an inversion signal 41A
The AND of the "L" and the "H" logic of the output signal 39 causes the output signal 42A to be "L", the downlink logic stop signal 43A to be "H" output, that is, the downlink logic 45 to be in an operating state, On the other hand, the uplink logic stop signal 44A outputs "L", that is, the uplink logic 46 is stopped. Further, the counter 38 receives the "H" output of the output signal 40, and the "H" output of the output signal 39 is reset to the "L" logic.

The relationship between the internal voltage of the data carrier and the characteristics of the load switch will be described. First, at the time of downlink, since the control signal from the control circuit 34 to the load switch transistor 36 is “H” output, the load switch transistor 36 is in the OFF state, and the rectifier circuit 3
2 is an ON state. Further, the EOF detection circuit 37 is a non-EO
Since the F detection is performed, the logic "L" is output. The output signal 39 is "L", the output signal 40 is "L", and the inverted signal 41A is "H" through the counter 38. Therefore, the output signal 42A is "L". ,
That is, since the downlink logic stop signal 43A is in the "H" state, the downlink logic 45 is in the normal operation state, and the uplink logic stop signal 44A.
Is in the "L" state, the uplink logic 46 is stopped. Therefore, the total internal resistance after the rectifier circuit 32 is the sum of the demodulation circuit 33 and the internal resistance excluding the uplink logic 45 in the control circuit 34, and the internal voltage after the rectifier circuit 32 is always constant.

Next, the relationship and operation between the internal voltage and the load switch during uplink will be described. FIG. 5 is a diagram showing the relationship between the internal voltage of the data carrier and the load switch according to the present invention and the related art. First, in FIG. 7, from the “H” period of the output signal 39 arbitrarily set to include the downlink internal processing period after EOF in the transmission instruction signal to the output signal 40 including the response signal period after waiting time. Since the downlink logic 45 is stopped until the “H” period, the total internal resistance after the rectifier circuit 32 is the internal resistance of the demodulation circuit 33 and the internal resistance of the control circuit 34 excluding the downlink logic 45. And the sum. When the load switch transistor 36 is OFF in the state of this internal resistance, the rectifier circuit 32 is in the ON state, the voltage supply to the inside after the rectifier circuit 32 is constant, and the internal voltage shows a characteristic like C1.

Next, when the load switch transistor 36 is ON, the resistance in the modulation circuit 35 becomes conductive and the rectification circuit 3
The rectifier circuit 32 is OF
In the F state, the voltage supply to the inside after the rectifier circuit 32 is cut off, and the internal voltage is consumed according to the time constant of the internal resistance of the demodulation circuit 33 and the internal resistance of the control circuit 34 excluding the downlink logic and the smoothing capacitance. , C2. Since the total internal resistance at this time excludes the internal resistance of the downlink logic 45 from the conventional product, the decrease of the internal voltage becomes slower than that of the conventional A2 characteristic, and the operation is possible even at a lower internal voltage. It will be possible. Since it is possible to operate with a low internal voltage, that is, it is possible to operate with a low supply voltage, it becomes possible to perform long-distance communication with the reader / writer as compared with the conventional product as shown in FIG.

The instruction circuit for stopping the downlink logic 45 by using the output of the EOF detection circuit 37 as a trigger includes a counter 38, an inverter 41, and an AND circuit 4.
2, NAND circuits 43, 44, etc., but the invention is not limited to this.

[0054]

As described above, according to the present invention, when performing uplink on a data carrier using a load modulation method,
An excellent data carrier capable of long-distance communication can be realized by stopping the unnecessary operation of the downlink circuit and mitigating the decrease in the internal voltage due to the time constant.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data carrier according to (Embodiment 1) of the present invention

FIG. 2 is a timing chart diagram of a communication signal between a reader / writer and a data carrier and the inside of the data carrier in the embodiment.

FIG. 3 is a format diagram of a transmission instruction signal according to the same embodiment.

FIG. 4 is a diagram showing a relationship between a communication distance and a supply voltage in the same embodiment.

FIG. 5 is a diagram showing a relationship between an internal voltage and a load switch according to the same embodiment.

FIG. 6 is a configuration diagram example of a data carrier according to (Embodiment 2) of the present invention

FIG. 7 is a timing chart diagram of communication between reader / writer data carriers and the inside of the data carrier in the embodiment.

FIG. 8 is a block diagram of a conventional data carrier.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 antenna coil 2 rectification circuit 3 demodulation circuit 4 control circuit 5 modulation circuit 6 load switch transistor 7 EOF detection circuit 8 counter 9 demodulation circuit stop start signal 10 demodulation circuit stop end signal 11A inverted signal 12A demodulation circuit operation stop signal 13 demodulation circuit Operation control transistor 14 Reference voltage generation circuit 15 Switch 31 Antenna coil 32 Rectifier circuit 33 Demodulation circuit 34 Control circuit 35 Modulation circuit 36 Load switch transistor 37 EOF detection circuit 38 Counter 39 Output signal 40 Output signal 41 Inverter 42 AND circuit 43, 44 NAND circuit 43A Downlink logic stop signal 44A Uplink logic stop signal 45 Downlink logic 46 Uplink logic 47 Memory 48 CLK generation circuit 50 Transmission instruction signal 51 Signal instruction signal start part (SOF) 52 Instruction content 53 Transmission instruction signal end part (EOF) A1 Conventional long-distance internal voltage characteristic during load switch OFF period A2 Conventional long-distance internal voltage characteristic during load switch ON period B load Conventional short-distance internal voltage characteristic during switch OFF and ON periods C1 Long-distance internal voltage characteristic of the present invention during load switch OFF period C2 Long-distance internal voltage characteristic of the present invention during load switch ON period

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2C005 MA29 MB03 MB10 NA08 SA01                       SA21 SA25 SA30                 5B035 AA05 BB09 CA23                 5K011 DA02 DA15 DA26 DA29 EA05                       GA05 JA00 KA03                 5K012 AB05 AB12 AB18 AC06 AC09                       AC11 AE13 BA02

Claims (4)

[Claims] 1. A voltage induced in an antenna is rectified to supply necessary power, a signal received from the antenna is demodulated by a demodulation circuit to recognize an instruction content, a memory is accessed, and read from the memory. A data carrier for transmitting the content from the antenna through a load modulation type modulation circuit, the data carrier comprising control means for stopping the demodulation circuit during an up ring period during which the transmission is executed. 2. A control circuit for detecting an end portion (EOF) in a transmission instruction signal transmitted during a downlink period of a transmission instruction to a data carrier, and an output of the detection circuit as a trigger. An instruction circuit for stopping the demodulation circuit during the uplink period.
Data carrier described in. 3. A voltage induced in an antenna is rectified to supply necessary power, a signal received from the antenna is demodulated by a demodulation circuit, and a signal from the demodulation circuit is processed by a downlink logic. The transmission is executed in a data carrier that recognizes the instruction content from the downlink logic, accesses the memory, and transmits the content read from the memory from the antenna via a load modulation type modulation circuit. And a control means for stopping the downlink logic during an uplink period. 4. The end means (EO) in the transmission instruction signal transmitted during the downlink period of the transmission instruction from the reader / writer to the data carrier.
The data carrier according to claim 3, further comprising: a detection circuit that detects F); and an instruction circuit that stops the downlink logic by using an output of the detection circuit as a trigger.