JP5359625B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing apparatus.

  A data processing device in a communication system is required to have real-time processing. The real-time property is to guarantee that the processing is completed within a predetermined time from the request for processing. In particular, the communication control data and the like need to be processed in real time in order to maintain the communication state. . Therefore, the data processing performance of the data processing device in the communication system is determined based on the maximum load amount or the maximum processing amount of the assumed processing.

  FIG. 1 is a diagram showing the relationship between the execution time and the remaining data amount (load amount) when a processor that performs data processing processes one frame of data at each of the supplied clock frequencies f1 and f2. Solid lines L1 to L3 represent the remaining data amounts when the frames are subjected to data processing at the frequencies f1 and f2, respectively, enclosed in parentheses.

  In a communication system in which data is transmitted and received in frame units, it is required to complete processing within a specified frame length FL. Therefore, the maximum clock frequency f1 is determined based on the maximum data amount W1 assumed for the frame and the specified frame length FL. As a result, as shown by the solid line L1, even if the frame has the maximum data amount W1, the processing is completed with the frame length FL by performing data processing at the maximum frequency f1. That is, the real-time property described above is ensured. In the case of the data amount W2 (<W1), as shown by solid lines L2 and L3, the clock frequency of data processing can be lowered from the maximum frequency f1 to the clock frequency f2 while guaranteeing real-time performance.

  Furthermore, low power consumption is required for communication systems in which battery-powered devices such as mobile phone systems are used.

  FIG. 2 is a diagram illustrating an example of a method for reducing power consumption in a communication system. The frame length FL and the maximum frequency f1 in FIG. 2 correspond to the frame length FL and the maximum frequency f1 shown in FIG. The frames F1 to F3 received by the receiving device are processed at the maximum frequency f1 by the data processing device. Then, the data processing apparatus sets the clock supplied to the data processing processor or the like at the time points Te1 to Te3 when the data processing is completed for each frame F1 to F3, and lowers the power supply voltage. That is, in the period Tp1 to Tp3, data processing can be stopped, and low power consumption is realized.

  FIG. 3 is a diagram illustrating a general formula for power consumption. As shown in FIG. 3, the total power consumption E of the processor or the like that performs data processing is obtained based on the supplied clock frequency fc, the power supply voltage VDD, the leak current Ilkg or the capacitance C of the processor, or the like. The first term of power consumption E represents dynamic power consumption E1, and the second term represents static power consumption E2. Thus, the dynamic power consumption E1 of the power consumption E is proportional to the square of the power supply voltage VDD. Therefore, reducing the power supply voltage supplied to the processor or the like is the most effective means for reducing power consumption.

  Therefore, as another method for reducing power consumption, control by DVFS (Dynamic Voltage and Frequency Scaling) is performed. This control is a technique for dynamically controlling the power supply voltage and the clock frequency during data processing.

  FIG. 4 is a diagram illustrating a relationship between a clock frequency and a power supply voltage supplied to a processor or the like that performs data processing. In FIG. 4 (a) and FIG. 4 (b), the data amount of the frame F4 processed is the same.

  As shown in FIG. 4A, when data processing is performed on the frame F4 at the clock frequency f, the processing is completed at time T. In addition, as shown in FIG. 4B, when data processing is performed at a clock frequency f / 2 that is 1/2 with respect to the frame F4, it takes twice the time 2T to complete the processing. As shown in 4 (c), the power supply voltage can be lowered to the power supply voltage corresponding to the clock frequency f / 2 during that time.

  In this way, in the control by DVFS, the corresponding power supply voltage can be lowered by lowering the clock frequency during data processing, so that a significant reduction in power consumption is realized as described above.

  The data processing apparatus regarding the above is described in patent documents 1 to 4, for example.

JP 2008-282150 JP JP-A-8-76874 JP 2005-236867 JP JP 2008-113319 JP

  However, if the clock frequency is too low due to control by DVFS, the time required for data processing becomes long, so the real-time property of the data processing described above may not be guaranteed. Such a situation corresponds to, for example, the case where the data processing clock frequency for the frame having the data amount W2 is lowered below the frequency f2 in FIG. In order to avoid this, the data processing apparatus must always monitor the data processing status and appropriately control the clock frequency by DVFS. However, a large amount of resources are consumed for monitoring the data processing status. Is done. That is, constantly monitoring the data processing status leads to high overhead.

  Accordingly, an object of the present invention is to provide a data processing apparatus that realizes low power consumption by DVFS with low overhead while guaranteeing real-time performance.

  According to one aspect, a data processing device of a communication system that receives received data for each frame processes the received data for each frame based on a supplied clock and a power supply voltage, and performs a head portion of the frame. A data processing unit that completes the time constraint processing corresponding to the data included in the frame within a unit time given to the frame, and a power supply / clock that generates the clock and the corresponding power supply voltage and supplies the clock to the data processing unit A generator, a frame head detector that detects the head of the frame, and a clock frequency determiner that determines a clock frequency based on the amount of unprocessed data in the data processor, the power supply / clock generator The data processing unit can operate in response to the timing of the frame head detection by the frame head detection unit. A clock frequency setting timing within a unit time of the frame after the clock of the maximum frequency and the power supply voltage corresponding to the clock of the maximum frequency are supplied to the data processing unit and the data processing unit completes the time constraint processing A first frequency clock lower than the maximum frequency clock, the first frequency clock determined by the clock frequency determination unit based on the amount of unprocessed data at the clock frequency setting timing, and the first frequency A power supply voltage corresponding to a clock having a frequency of 1 is supplied to the data processing unit.

  According to the above invention, it is possible to provide a data processing device that realizes low power consumption by DVFS with low overhead while guaranteeing real-time performance.

FIG. 5 is a diagram illustrating a relationship between an execution time and a remaining data amount (load amount) when a processor that performs data processing processes one frame at each of the supplied clock frequencies f1 and f2. It is a figure which shows an example of the low power consumption method in a communication system. It is a figure showing the formula of a general power consumption. It is a figure which shows the relationship between the clock frequency supplied to the processor etc. which perform data processing, and a power supply voltage. It is an example of the block diagram of the data processor in this Embodiment. It is an example of the data format of the frame which the data processor in this Embodiment processes. It is a figure which shows the operation example of the data processor in this Embodiment. The relationship between the processing execution time for the frame with the maximum data amount and the frequency of the clock CLK supplied to the processor 4 is shown. 6 is an example of a method for determining a clock frequency based on the amount of unprocessed data in the performance determination unit 412. The operation of the data processing apparatus when the aggregation of the unprocessed data amount in the data amount aggregating unit 411 is completed at the timing of completion of the time constraint processing is shown. It is an example of the data format of the frame which the data processor in this Embodiment processes.

  Hereinafter, embodiments will be described with reference to the drawings. However, the technical scope is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

[First embodiment]
FIG. 5 is an example of a block diagram of the data processing apparatus according to the present embodiment. This data processing apparatus can be implemented in all devices that perform data processing for each data unit such as a frame in a wired or wireless communication system.

  This data processing device has a power supply / clock generation unit 1, a data reception unit 2, a data transmission unit 3, a processor 4, and an input / output device 5, and performs data processing on received data RD of received frames and processing of processed data. Perform output, etc. The clock frequency determination unit 41 and the data processing unit 42 in the processor 4 correspond to functions realized by executing a software program.

  The data receiving unit 2 includes a radio synchronization and demodulation / decoding unit 21 and a data buffer 22, and performs reception processing on the received data RD of the frame.

  FIG. 6 is an example of a data format of a frame processed by the data processing apparatus according to the present embodiment. The frame includes a frame synchronization symbol FH, communication control data CD, and user data UD1 to UD3. The frame length FL from the head FS of the frame to the end FE of the frame is a unit time given to the frame, and the reception data RD of the frame is normally required to complete processing within this unit time. The frame length FL is specified for each system, and for example, is specified as 10 ms in a W-CDMA system which is one of communication systems.

  The processing corresponding to the communication control data CD includes time constraint processing that requires real-time performance in order to maintain the communication state after the next frame, and the time constraint processing must be completed within the frame length FL. Therefore, normally, the communication control data CD is included in the head portion of the frame. This is because if included in the rear part of the frame, the time constraint processing may not be completed by the next frame. Then, the data processing apparatus processes these time constraint processes at the maximum frequency. Examples of the time constraint process include a transmission power control process and a communication state report process, and the specific contents thereof will be described later.

  In addition, the processing corresponding to the user data UD1 to UD3 is processing without time restriction that allows a delay of about several frames until the processing is completed. Then, the data processing apparatus processes these processes without time constraints at an optimal low clock frequency.

  Returning to FIG. 5, the radio synchronization and demodulation decoding unit 21 of the data reception unit 2 performs synchronization processing, demodulation decoding processing, and demodulation decoding processing on the frame received based on the frame synchronization symbol FH shown in FIG. The received data RD is sequentially output to the data buffer 22. Thereafter, the data processing unit 42 processes the reception data RD output to the data buffer 22 in parallel with the demodulation and decoding of the reception data RD of the frame in the radio synchronization and demodulation decoding unit 21.

  Further, the radio synchronization and demodulation decoding unit 21 obtains the reception data amount of the reception data RD obtained by demodulating and decoding the reception data RD of the frame, and the reception data amount is obtained from the reception data amount totaling unit 416 which is a software program of the processor 4. Output to. The received data amount totaling unit 416 will be described later.

  Since the timing at which the received data amount of the frame is obtained in this way is after the demodulation and decoding of the received data RD of the frame has been completed, the processing of the demodulated and decoded received data RD in the data processing unit 42 is started. It is later than the timing. Furthermore, the timing at which the received data amount is obtained depends on the received data amount to be demodulated and decoded for each frame, and therefore differs for each frame.

  The radio synchronization / demodulation decoding unit 21 detects the beginning of the frame based on the frame synchronization symbol FH, and outputs the frame start detection signal S1 to the power / clock generation unit 1 at the detection timing.

  The data buffer 22 temporarily stores the received data RD in the demodulated and decoded frame.

  The power / clock generator 1 includes a power generator 11 and a clock generator 12, and the clock CLK generated by the clock generator 12 based on the input signals S1 and S5 shown in FIG. 5 and the corresponding power generator The power supply voltage Vc generated by 11 is supplied to the processor 4.

  Here, the power supply / clock generation unit 1 responds to the input of the frame head detection signal S1 output from the above-described wireless synchronization and demodulation decoding unit 21, and the clock CLK of the maximum frequency at which the processor 4 can operate and the corresponding power supply Supply voltage to processor 4.

  The processor 4 executes a computer program having the functions of the clock frequency determination unit 41 and the data processing unit 42 based on the clock CLK supplied from the power / clock generation unit 1 and the power supply voltage Vc corresponding thereto. That is, the data processing unit 42 sequentially processes input data based on the clock CLK and the power supply voltage Vc.

  Based on the above operation, the data processing apparatus starts processing the received data of the frame at the maximum frequency in response to detection of the head of the received frame. Thereby, the time constraint processing corresponding to the data included in the head portion of the frame is automatically processed at the maximum frequency. Moreover, since the control to the maximum frequency is performed in response to the detection of the head of the frame, no special monitoring process is required.

  In addition, the data processing unit 42 includes the received data of the current frame being received and temporarily received in the data buffer 22 and the received data of the unprocessed previous frame, the transmission data input from the input / output device 5, and the like. Process. The data processed by the data processing unit 42 is output to the input / output device 5 or the data transmission unit 3, for example.

  Further, the data processing unit 42 outputs the time constraint processing completion signal S3 to the clock frequency determination unit 41 after completing the above-described time constraint processing. As a method for detecting the completion of the time constraint process, for example, the data processing unit 42 first separates data corresponding to the time constraint process and data corresponding to the process without the time constraint from the input frame. The data processing unit 42 detects the completion of each process by managing each of these individually.

  The clock frequency determining unit 41 determines the frequency of the clock CLK based on the amount of unprocessed data that has not been processed by the data processing unit. For this purpose, the clock frequency determining unit 41 includes a data amount totaling unit 411, a performance determining unit 412, a data processing management function unit 413, a transmission data amount totaling unit 414, an unprocessed received data amount totaling unit 415, and a received data amount totaling unit. 416.

  The transmission data amount totaling unit 414 totals the amount of data to be processed among the transmission data input from the input / output device 5 or the like. Alternatively, the total value of the data amount may be a fixed value defined as an allowable amount of transmission data for each communication system.

  The unprocessed received data amount totaling unit 415 refers to the data buffer 22 and totals the unprocessed data amount of the previous frame stored in the data buffer 22 and staying there.

  The received data amount totaling unit 416 totalizes the received data amount of the current frame output from the above-described wireless synchronization and demodulation decoding unit 21 as a total value.

  The data amount totaling unit 411 totalizes each data amount totaled by the transmission data amount totaling unit 414, the unprocessed received data amount totaling unit 415, and the received data amount totaling unit 416 as an unprocessed data amount. Here, the timing at which the summation of each data amount is started is the timing at which the received data amount summation unit 416 acquires the received data of the current frame. That is, at the timing when the received data amount totaling unit 416 acquires the received data of the current frame from the wireless synchronization and demodulation / decoding unit 21, the transmission data amount totaling unit 414 and the unprocessed received data amount totaling unit 415 Start counting. Then, after completion of all the aggregations, the data amount aggregation unit 411 aggregates the data amounts aggregated by the aggregation units 414 to 416 as unprocessed data amounts. This unprocessed data amount represents the current processing status of the so-called data processing device, and the clock frequency determination unit 41 determines the optimum clock frequency corresponding to the current processing status based on this data processing amount.

  Further, the data amount totaling unit 411 outputs a data amount totaling completion signal S6 to the data processing management function unit 413 at the timing when the totaling of the unprocessed data amount is completed.

  The data processing management function unit 413 manages the timing of completion of the time constraint processing in the data processing unit 42 and the timing of completion of aggregation of the unprocessed data amount in the data amount aggregation unit 411, respectively. The performance determination unit 412 described below determines the clock frequency at any one of these timings, but these timings are different for each frame.

  For example, when the amount of received data in a frame is large but the amount of data corresponding to the time constraint process included in the frame is small, the timing for completing the time constraint process is early. In addition, since the radio synchronization and demodulation / decoding processing in the demodulation / decoding unit 21 takes time, the timing for completing the totalization of the unprocessed data amount is delayed. In this case, the performance determination unit 412 may not complete the aggregation of the unprocessed data amount at the completion timing of the time constraint process, and cannot determine the clock frequency based on the unprocessed data amount.

  Therefore, in response to the time constraint processing completion signal S3 from the data processing unit 42, the data processing management function unit 413 first aggregates the unprocessed data amount based on the data amount aggregation completion signal S6 from the data amount aggregation unit 411. Determine whether completed or incomplete. Then, the data processing management function unit 413 outputs a clock frequency determination signal S4 corresponding to the determination result to the performance determination unit 412. In other words, the clock frequency determination signal S4 includes information on whether or not the processing of the unprocessed data amount has been completed.

  Further, when the total amount of unprocessed data in the data amount totaling unit 411 has not been completed, the data processing management function unit 413 generates a data amount totaling completion signal S6 from the data amount totaling unit 411 after the completion of the totalization. receive. Then, the data processing management function unit 413 outputs a second clock frequency determination signal S4 indicating the completion of aggregation to the performance determination unit 412 in response to the data amount aggregation completion signal S6.

  The performance determination unit 412 determines an optimal clock frequency for the unprocessed data in response to the clock frequency determination signal S4 described above. In other words, when the clock frequency determination signal S4 indicates that the unprocessed data amount has been totaled, the performance determining unit 412 determines the clock frequency based on the unprocessed data amount totaled by the data amount totaling unit 411. Then, the processor 4 outputs a clock frequency setting signal S5 corresponding to the clock frequency to the power / clock generator 1.

  On the other hand, when the clock frequency determination signal S4 indicates that the unprocessed data amount has not been aggregated, the performance determination unit 412 determines the clock frequency determined in the same manner in the processing for the previous frame as the clock frequency. Then, the processor 4 outputs a clock frequency setting signal S5 corresponding to the clock frequency to the power / clock generator 1. That is, since the aggregation of the amount of unprocessed data is incomplete, the clock frequency cannot be determined based on the amount of unprocessed data, but the time constraint processing is complete, so it was determined in the previous frame. The subsequent processing is executed at a low clock frequency and a corresponding power supply voltage.

  Further, in this case, the performance determination unit 412 receives the second clock frequency determination signal S4 indicating the completion of the aggregation of the unprocessed data amount in the data amount aggregation unit 411 from the data processing management function unit 413. Therefore, the performance determination unit 412 determines the clock frequency based on the amount of unprocessed data in response to the second clock frequency determination signal S4. Then, the processor 4 outputs a clock frequency setting signal S5 corresponding to the clock frequency to the power / clock generator 1.

  The data transmission unit 3 includes a modulation and coding unit 31 and a data buffer 32, and performs transmission processing on the transmission data processed by the data processing unit. The data buffer 32 temporarily stores the transmission data TD. Also, the modulation and coding unit 31 performs modulation and coding on the transmission data TD stored in the data buffer 32 and outputs a transmission frame.

  FIG. 7 is a diagram illustrating an operation example of the data processing apparatus according to the present embodiment. FIG. 7 shows the relationship between the processing execution time and the frequency of the clock CLK supplied to the processor 4 when the data processing apparatus sequentially receives the frames F11, F12,. FIG. 7 shows the operation of the data processing apparatus when the total amount of unprocessed data in the data amount totaling unit 411 is incomplete at the timing of completion of the time constraint processing. In the parentheses, clock frequencies f10 to f13 supplied to the data processing unit 42 at each execution time are shown.

  Times Ts1 to Ts4 are timings when the beginning of the frame is detected, times Td1 to Td3 are timings for completion of time constraint processing in the data processing unit 42, and times Tc1 to Tc3 are data amount totaling unit 411 This is the timing of completing the aggregation of the amount of unprocessed data.

  Hereinafter, the operation of the data processing apparatus will be described with reference to FIGS.

  At time Ts1, the data receiving unit 2 receives the frame F11. Then, the radio synchronization and demodulation decoding unit 21 detects the head and outputs a frame head detection signal S1 to the power / clock generation unit 1.

  The received data of the frame F11 is demodulated and decoded and temporarily stored in the data buffer 22. The received data output to the data buffer 22 in parallel with the demodulation and decoding of the received data of the frame is sequentially processed by the data processing unit 42.

  In response to the input timing of the frame head detection signal S1, the power supply / clock generation unit 1 supplies the data processing unit 42 with the clock CLK having the maximum frequency f1 at which the data processing unit 4 can operate and the corresponding power supply voltage Vc. Supply to the processor 4 having. Specifically, the power / clock generator 1 raises the power supply voltage Vc supplied to the processor 4 to the power supply voltage Vc corresponding to the maximum frequency f1, and then changes the frequency of the clock CLK to the maximum frequency f1. This is because even if the clock CLK is first changed to the maximum frequency f1, if the corresponding power supply voltage Vc is not supplied, the processor 4 does not operate at the maximum frequency f1 and may malfunction.

  The data processing unit 42 processes the received data of the frame F11 stored in the data buffer 22 after time Ts1. Then, the time constraint process corresponding to the communication control data CD included in the head portion of the frame F11 shown in FIG. 6 is automatically executed at the maximum frequency f1.

  Here, if the time constraint processing is executed within the frame length FL, the real-time property is guaranteed, but the reason why the time constraint processing is always executed at the maximum frequency f1 will be described below.

  FIG. 8 shows the relationship between the processing execution time for the frame having the maximum data amount and the frequency of the clock CLK supplied to the processor 4. Here, FIG. 8 shows the communication control data CD and user data UD in one frame as in FIG. 6, and the time constraint processing corresponding to the communication control data CD included in the head portion of the frame is first. To be executed. Also, the total data amount of the frames shown in FIGS. 8 (a) and 8 (b) is the same, and is the maximum data amount assumed for the system.

  As shown in FIG. 8 (a), when the data processing device processes a frame with the maximum data amount assumed, if the processing is performed at the maximum frequency f1, the processing is completed with one frame length FL. As described with reference to FIG. 1, the maximum frequency f1 of the data processing apparatus is designed to be a frequency at which processing of a frame with the maximum data amount assumed in the system can be completed within one frame length FL.

  In addition, the data processing apparatus cannot predict the data amount of the frame before starting the processing. Therefore, the data processing apparatus sets the processing speed to the maximum frequency f1 in response to detection of the head of the frame in order to guarantee the completion of the processing within one frame length FL even for the frame having the maximum data amount.

  On the other hand, as shown in Fig. 8 (b), the time constraint processing is completed within the frame length FL even if the processing speed when detecting the beginning of the frame is not set to the maximum frequency f1, but is set to a lower frequency f3. Therefore, its real-time property is guaranteed.

  However, when the user data UD has the maximum data amount, the processing without the time constraint corresponding to the user data UD is not completed within the frame length FL even if it is executed at the maximum frequency f1. As a result, the user data UD shown in the period FLp stays in the data buffer 22 as unprocessed received data of the frame. As a result, even if a delay of several frames is allowed for processing without time constraints corresponding to the user data UD, if reception of a frame with the maximum amount of data continues, unprocessed received data staying in each frame The data buffer 22 may overflow and the system may be destroyed.

  As described above, the data processing device responds to the detection of the beginning of the frame and automatically processes regardless of the amount of unprocessed data at that point in order to avoid system corruption due to the retention of the received data amount of the frame. Set the speed to the maximum frequency f1. As a result, the time constraint processing corresponding to the communication control data CD included in the head part of the frame is automatically executed at the maximum frequency f1, and even if the user data UD reaches the maximum data amount, system breakdown is avoided. .

  Returning to FIG. 7, at the timing of completion of the time constraint processing at time Td1, the data processing unit 42 outputs a time constraint processing completion signal S3 to the data processing management function unit 413. Since the subsequent processing is processing without time restrictions corresponding to the user data UD1 to UD3, the clock frequency is set lower than the maximum frequency f1 if possible in order to reduce power consumption.

  In response to the time constraint processing completion signal S3 from the data processing unit 42, the data processing management function unit 413 refers to whether or not the data amount totaling completion signal S6 is received from the data amount totaling unit 411.

  As described above, in this operation example, the total amount of unprocessed data in the data amount totaling unit 411 is not completed at the timing Td1 when the time constraint processing is completed. This is because, for example, the amount of received data of the frame is large, and the radio synchronization and demodulation decoding unit 21 has not completed the demodulation and decoding process for the received data of the frame. Therefore, the data processing management function unit 413 has not received the data amount totaling completion signal S6 from the data amount totaling unit 411.

  Therefore, the data processing management function unit 413 outputs to the performance determining unit 412 a clock frequency determination signal S4 indicating that the total amount of unprocessed data is not completed.

  In response to the clock frequency determination signal S4, the performance determination unit 412 determines the clock frequency f10 determined based on the unprocessed data amount in the frame F10 immediately before the frame F11 as a new clock frequency. That is, the processing speed for the previous frame is taken over. Then, the processor 4 outputs a clock frequency setting signal S5 corresponding to the determined clock frequency to the power supply / clock generation unit 1.

  The power supply / clock generation unit 1 supplies the clock CLK having the frequency f10 corresponding to the clock frequency setting signal S5 and the power supply voltage Vc corresponding thereto to the processor 4 having the data processing unit 42. Thereafter, during time Td1 to Tc1, processing without time restriction corresponding to unprocessed data is executed at the clock frequency f10.

  At time Tc1, the radio synchronization and demodulation / decoding unit 21 completes the demodulation / decoding of the received data of the frame, obtains the received data amount, and outputs the received data amount to the received data amount totaling unit 416. Then, at the timing when the received data amount is input to the received data amount totaling unit 416, the transmission data amount totaling unit 414 and the unprocessed received data amount totaling unit 415 totalize the respective data amounts, and the data amount totaling unit 411 The data amount totaled by the totaling units 414 to 416 is totaled as the unprocessed data amount.

  Further, the data amount totaling unit 411 outputs a data amount totaling completion signal S6 to the data processing management function unit 413 at the timing when the totaling of the unprocessed data amount is completed.

  The data processing management function unit 413 outputs the second clock frequency determination signal S4 in response to the data amount totaling completion signal S6.

  In response to the second clock frequency determination signal S4 from the data processing management function unit 413, the performance determination unit 412 refers to the unprocessed data amount. This amount of unprocessed data corresponds to the current data processing status. Then, the performance determination unit 412 determines the clock frequency f11 based on the unprocessed data amount. Then, the processor 4 outputs a clock frequency setting signal S5 corresponding to the determined clock frequency to the power supply / clock generation unit 1. Here, the clock frequency f11 is, for example, the minimum clock frequency at which all processing corresponding to unprocessed data can be completed within the frame length FL.

  FIG. 9 is an example of a clock frequency determination method based on the amount of unprocessed data in the performance determination unit 412. A chart 91 shows the data amount totaled by the totaling units 414 to 416. The data amount totaling unit 411 totalizes the received data amount A, the unprocessed received data amount B, and the transmission data amount C that are totaled by the total units 414 to 416 as the unprocessed data amount.

  The chart 92 shows an example of midway calculation until the performance determining unit 412 determines the clock frequency based on the unprocessed data amount tabulated by the data tabulating unit 91.

  In the column p1, the unprocessed data amounts A, B, and C obtained by the performance determination unit 412 referring to the data totaling unit 411 are shown.

  In the column p2, coefficients X, Y, and Z based on the priority of data processing are shown. For example, if an increase in the amount of transmitted data is expected and the amount of unprocessed data increases and there is a possibility of system breakdown, increase the coefficient Z in order to process the transmitted data quickly. Increase processing priority.

  The column p3 shows the integrated values AX, BY, and CZ of the columns p1 and p2, and the column p4 shows the sum of these integrated values (AX + BY + CZ) as the final aggregated value D. Yes.

  The chart 93 is a correspondence table in which the relationship between the final total value D based on the amount of unprocessed data and the clock frequency corresponding thereto is defined. The performance determination unit 412 determines the clock frequency based on this correspondence table. For example, when the final total value D is 10000 bytes or more and less than 30000 bytes, the clock frequency is determined to be 100 MHz. The chart 93 shows the operating voltage corresponding to the clock frequency. As described above, the performance determining unit 412 may determine the operating voltage corresponding to the clock frequency. In Chart 93, the higher the clock frequency, the higher the corresponding operating voltage required for driving. As described above, since the power consumption is mainly proportional to the square of the power supply voltage, it is preferable to determine a lower clock frequency from the viewpoint of reducing the power consumption.

  In addition, as described above, when the coefficient Z is increased in order to quickly execute the processing corresponding to the transmission data, even if the transmission data amount C is small, the final aggregate value D is increased due to the coefficient Z, The clock frequency is determined to be a large value. That is, the priority of the data processing with respect to the transmission data amount C is reflected in the processing speed.

  5 and 7, the power / clock generator 1 supplies the data processor 42 with the clock CLK having the frequency f11 corresponding to the clock frequency setting signal S5 and the power supply voltage Vc corresponding thereto. Thereafter, during time Tc1 to Ts2, processing corresponding to unprocessed data is executed at the clock frequency f11.

  Next, at time Ts2, the data receiving unit 2 detects the beginning of the frame F12. In response to this, the clock frequency is again changed to the maximum frequency f1, and the power supply voltage Vc is also raised. Similarly, the time constraint process corresponding to the communication control data CD of the frame F12 is executed at the maximum frequency f1. After the time constraint processing is completed, the clock frequency f11 is changed to the clock frequency f11 determined in the previous frame F11 after the timing of the time constraint processing completion time Td1. Further, in response to the timing Tc2 for counting the unprocessed data amount, the clock frequency f12 is changed to a new clock frequency f12 determined based on the unprocessed data amount. Thereafter, the same processing is repeated for each frame as shown in FIG.

  As described above, the data processing apparatus according to the present embodiment automatically executes the time constraint processing corresponding to the data included in the head portion at the maximum frequency. Then, at the completion timing, if the aggregation of the amount of unprocessed data corresponding to the current data processing status is not completed, the data processing apparatus has no time constraint at the clock frequency determined in the previous frame. Execute the process. As a result, the data processing apparatus can reliably execute only the time constraint processing at the maximum frequency and can avoid performing the processing without the time constraint at the maximum frequency. Therefore, lower power consumption can be realized. .

  Further, at the timing of completion of totalization of the unprocessed data amount, the data processing apparatus executes processing without time constraint at the lowest possible clock frequency newly determined based on the unprocessed data amount. The setting of the clock frequency based on the amount of unprocessed data is performed only once within a prescribed frame length FL for each frame.

  As described above, the data processing apparatus according to the present embodiment completes the time constraint processing in real time, and realizes low power consumption while maintaining the communication state. In addition, this data processing device does not need to constantly monitor the data processing status to reduce power consumption, and only sets an appropriate clock frequency once at a predetermined timing for each frame. Is realized.

  FIG. 10 is a diagram illustrating an operation example different from that of FIG. 7 of the data processing apparatus according to the present embodiment. FIG. 10 shows the operation of the data processing apparatus when the total amount of unprocessed data in the data amount totaling unit 411 is completed at the timing when the time constraint processing is completed. Times Ts1 to Ts4 are timings when the beginning of the frame is detected, times Td1 to Td3 are timings for completing the time constraint processing in the data processing unit 42, and times Tc1 to Tc3 are not yet processed by the data amount totaling unit 411. This is the timing for completing the processing data amount.

  FIG. 10 shows in FIG. 7 that the timings Td1 to Td3 of completion of the time constraint processing in the data processing unit 42 are later than the timings Tc1 to Tc3 of completion of aggregation of the unprocessed data amount in the data amount aggregation unit 411. It is different from the operation example. Such an operation can occur, for example, when the amount of received data of the frame is small and the ratio of the data CD corresponding to the time constraint processing of the frame is large. In other words, since the received data amount of the frame is small, the demodulation and decoding process in the radio synchronization and demodulation and decoding unit 21 is completed early, and the received data amount of the frame is obtained at an early timing. The timing time Tc1 to Tc3 for completing the collection of the processing data amount is early. Further, since the ratio of the data CD corresponding to the time constraint processing of the frame is large, the timing Td1 to Td3 for completing the time constraint processing in the data processing unit 42 is relatively delayed.

  Hereinafter, the difference from the operation of FIG. 7 will be described with reference to FIGS.

  The received data of the frame F11 is demodulated and decoded and temporarily stored in the data buffer 22. Thereafter, the received data output to the data buffer 22 in parallel with the demodulation and decoding of the received data of the frame is sequentially processed by the data processing unit 42 at the maximum frequency f1.

  At time Tc1, the demodulation and decoding of the reception data of frame F11 is completed, the reception data amount of frame F11 is obtained, and the aggregation of the unprocessed data amount in data amount aggregation unit 411 is completed. Then, the data amount totaling unit 411 outputs a data amount totaling completion signal S6 to the data processing management function unit 413.

  Then, at the timing of completion of the time constraint processing at time Td1, the data processing unit 42 outputs a time constraint processing completion signal S3 to the data processing management function unit 413.

  The data processing management function unit 413 refers to whether or not the data amount totaling completion signal S6 is received from the data amount totaling unit 411 in response to the time constraint processing completion signal S3 from the data processing unit 42, and the unprocessed data A clock frequency determination signal S4 indicating completion of totaling the amount is output to the performance determination unit 412.

  In response to the clock frequency determination signal S4 from the data processing management function unit 413, the performance determination unit 412 determines a new clock frequency f11 based on the amount of unprocessed data aggregated by the data amount aggregation unit 411. Then, the processor 4 outputs a clock frequency setting signal S5 corresponding to the determined clock frequency to the power supply / clock generation unit 1. In response to this, the power supply / clock generator 1 lowers the clock CLK from the maximum frequency f1 to the clock frequency f11, and lowers the power supply voltage Vc from the maximum voltage corresponding to the maximum frequency f1 to the voltage corresponding to the clock frequency f11.

  After time Td1, the processing corresponding to the unprocessed data is executed at the clock frequency f11 until the head detection timing Ts2 of the frame 12. Thereafter, the same processing is repeated for each frame as shown in FIG.

  As described above, when the timing constraints Td1 to Td3 in the data processing unit 42 are completed later than the timings Tc1 to Tc3 in the data amount totaling unit 411, the present data processing The apparatus determines a new clock frequency based on the amount of unprocessed data at the former timings Td1 to Td3.

  As described above, this data processing apparatus realizes low overhead and low power consumption by the operation shown in FIG. 7 or the operation shown in FIG. 10 for each frame regardless of the nature of the received data of the frame.

  Also, since the radio synchronization and demodulation / decoding unit 21 detects the beginning of the frame and the processing of the received data of the frame is started by the data processing unit 42, demodulation / decoding processing, buffering, and the like are performed. A delay is assumed to occur. In such a case, it is not appropriate to supply the clock CLK having the maximum frequency to the processor 4 when the head of the frame is detected.

  Therefore, the radio synchronization / demodulation decoding unit 21 outputs the frame head detection signal S1 to the power / clock generation unit 1 at the timing when the data processing unit 42 starts the time constraint processing after the timing of the frame head detection.

  This is because, for example, the data processing unit 42 returns a signal (not shown) to the wireless synchronization and demodulation decoding unit 21 simultaneously with the start of processing of the communication control data CD included in the head portion of the frame, and the wireless synchronization and demodulation decoding unit 21 This is realized by outputting a frame head detection signal S1 in response to the signal. Alternatively, the above-described delay may be assumed at the time of system design, and the radio synchronization and demodulation / decoding unit 21 may output the frame head detection signal S1 with a delay corresponding to the delay.

  As a result, the data processing apparatus can apply the processing with the clock of the maximum frequency and the power supply voltage corresponding thereto only to the data corresponding to the time constraint processing.

  Next, transmission power control processing, communication status reporting processing, and MAP information analysis processing will be briefly described as specific examples of time constraint processing that requires real-time performance in order to maintain the communication status.

  In the first example, in the CDMA system in which all users use the same frequency carrier wave, if the mobile station emits radio waves with the same transmission power regardless of the distance from the base station, the radio waves from the near side are too strong. The problem arises that it becomes impossible to separate signals from a distant mobile station. This is referred to as a near-far problem, and in order to solve this problem, adaptive transmission power control in which each mobile station minimizes transmission power is indispensable.

  Therefore, the mobile station adjusts its own transmission power based on the radio signal strength of the uplink signal specified by the base station as the time constraint process. This adjustment process is required to be completed within the period of the frame.

  In the second example, the base station first instructs the mobile station to measure the radio signal strength of the downlink signal in order to adjust the radio signal strength of the downlink signal transmitted to the mobile station. In response to the instruction, the mobile station measures the radio field intensity of the downlink signal from the base station and reports the measurement result to the base station. This reporting process is also required to be completed within the period of the frame in which the command command from the base station is received.

  A third example is as follows. FIG. 11 is an example of a data format of a frame processed by the data processing device according to the present embodiment. FIG. 11 (a) shows a frame structure of the TDMA scheme, and radio resources are divided in the time domain. The map data M1 includes management information of a plurality of divided time slots SL1, SL2,..., For example, information on slot positions assigned to the map data M1.

  FIG. 11 (b) shows an OFDMA frame configuration adopted by mobile WiMAX, and radio resources are divided into a frequency domain and a time domain. This frame has a plurality of bursts B1, B2,... That are blocks for data transfer. The map data M2 includes management information of these bursts B1, B2,... In the frame, and includes reception parameters such as allocation information of each burst and extended control information.

  In order to process these received frames, the receiving side must first analyze the map data M1 and M2 to detect the position information of each slot and burst. Therefore, the analysis of the map data M1 and M2 is required to be completed at an early stage of the frame period. Therefore, the data processing apparatus performs analysis processing of the map data M1 and M2 as time constraint processing.

  The above embodiment is summarized as follows.

(Appendix 1)
In a data processing apparatus of a communication system that receives received data for each frame,
The received data is processed for each frame based on the supplied clock and power supply voltage, and the time constraint processing corresponding to the data included in the head portion of the frame is completed within the unit time given to the frame. A data processing unit;
A power supply / clock generator that generates the clock and a power supply voltage corresponding to the clock and supplies the clock to the data processor;
A frame head detection unit for detecting the head of the frame;
A clock frequency determining unit that determines a clock frequency based on the amount of unprocessed data in the data processing unit,
The power supply / clock generation unit generates a clock having a maximum frequency at which the data processing unit can operate in response to the timing of the frame start detection by the frame start detection unit and a power supply voltage corresponding to the clock with the maximum frequency. A clock having a first frequency lower than the maximum frequency clock at a clock frequency setting timing within a unit time of the frame after the data processing unit completes the time constraint processing. The clock frequency determination unit supplies the data processing unit with the first frequency clock determined based on the unprocessed data amount at the clock frequency setting timing and the power supply voltage corresponding to the first frequency clock. Data processing device.

(Appendix 2)
The power supply / clock generation unit responds to the completion timing of the time constraint processing by the data processing unit, and the clock of the second frequency temporarily determined in the previous frame before the clock frequency setting timing The data processing apparatus according to appendix 1, wherein a power supply voltage corresponding to the clock having the second frequency is supplied to the data processing unit.

(Appendix 3)
The data processing device according to appendix 1, wherein the unprocessed data includes reception data and transmission data of a current frame and a previous frame.

(Appendix 4)
The data processing device according to claim 3, wherein the amount of unprocessed data is obtained after a coefficient based on a priority order of data processing is added to each of reception data and transmission data of the current frame and a previous frame.

(Appendix 5)
The data processing apparatus according to appendix 1, wherein the clock frequency determination unit includes a correspondence table in which a clock frequency corresponding to the unprocessed data amount is defined, and determines the first frequency based on the correspondence table.

(Appendix 6)
The power / clock generator generates a clock of the maximum frequency and a power supply voltage corresponding thereto at the timing of the start of the time constraint processing by the data processor after the detection timing of the frame by the reception data head detector. The data processing apparatus according to appendix 1, which is supplied to the data processing unit.

(Appendix 7)
The communication system is a wireless communication system having a base station and a mobile station, and the time constraint processing is performed by the mobile station adjusting its transmission power based on a radio signal strength of an uplink signal designated by the base station. The data processing device according to supplementary note 1 including processing to perform.

(Appendix 8)
The communication system is a wireless communication system having a base station and a mobile station, and the time constraint processing measures the radio field intensity of a downlink signal transmitted from the base station and reports the measurement result to the base station. The data processing apparatus according to appendix 1, including processing.

(Appendix 9)
The communication system is a wireless communication system having a base station and a mobile station, wherein the frame has a plurality of bursts that are blocks for data transfer, and the time constraint processing includes a plurality of bursts in the frame. The data processing apparatus according to appendix 1, which is a process of analyzing map data including positional information or reception parameters.

1 Power supply / clock generator 2 Data receiver 3 Data transmitter
4 Processor 5 I / O device 41 Clock frequency determination unit 42 Data processing unit

Claims (4)

In a data processing apparatus of a communication system that receives received data for each frame,
The received data is processed for each frame based on the supplied clock and power supply voltage, and the time constraint processing corresponding to the data included in the head portion of the frame is completed within the unit time given to the frame. A data processing unit;
A power supply / clock generator that generates the clock and a power supply voltage corresponding to the clock and supplies the clock to the data processor;
A frame head detection unit for detecting the head of the frame;
A clock frequency determining unit that determines a clock frequency based on the amount of unprocessed data in the data processing unit,
The power supply / clock generation unit generates a clock having a maximum frequency at which the data processing unit can operate in response to the timing of the frame start detection by the frame start detection unit and a power supply voltage corresponding to the clock with the maximum frequency. A clock having a first frequency lower than the maximum frequency clock at a clock frequency setting timing within a unit time of the frame after the data processing unit completes the time constraint processing. and a power supply voltage in which the clock frequency determining unit corresponds to the clock of the clock frequency above the first frequency determined based on the raw data amount in the setting timing clock from the first frequency to the data processing unit supplied, in response to the timing of completion of the time constraint processing by the data processing unit, the black A second frequency clock and a power supply voltage corresponding to the second frequency clock determined in a frame before the frame on which the time constraint processing is performed by the data processing unit in a predetermined period before the clock frequency setting timing And a data processing device for supplying the data processing unit. The power supply / clock generation unit corresponds to the clock of the maximum frequency and the clock of the maximum frequency at the start timing of the time constraint processing by the data processing unit after the detection timing of the frame by the reception data head detection unit. The data processing apparatus according to claim 1, wherein a power supply voltage to be supplied is supplied to the data processing unit.   The communication system is a wireless communication system having a base station and a mobile station, and the time constraint processing is performed by the mobile station adjusting its transmission power based on a radio signal strength of an uplink signal designated by the base station. The data processing apparatus according to claim 1, further comprising:   The communication system is a wireless communication system having a base station and a mobile station, and the time constraint processing measures the radio field intensity of a downlink signal transmitted from the base station and reports the measurement result to the base station. The data processing apparatus according to claim 1, comprising a process.

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