JPH0457407A - Parallel generating circuit for serial pn patterns and configuration method for said circuit - Google Patents

Abstract

PURPOSE:To output a serial PN pattern of an optional degree in parallel at an optional width by forming a degree (n) feedback shift register circuit with n-stages of shift registers and an EOR circuit exclusively ORing an output of the final stage register and an output of the m-th stage and applying the EOR to the 1st stage register. CONSTITUTION:An nXn-dimension square matrix expressing the relation between an n-dimension numerical vector comprising each input of n-set of registers in an n-stages of feedback shift registers and an n-dimension numerical vector comprising each output is obtained and a square matrix being the I-th power of the nXn-dimension square matrix is obtained, and each square matrix being the p-th power of the nXn-dimension square matrix is obtained by each value (p) satisfying equation of J>=p>=I+1. Moreover, a matrix of (n+J-1)-rows and n-columns whose 1st-n-th row element is that of the nXn-dimension square matrix is obtained. Then circuits each relating each input to each output of each of the n-sets of registers as to each (p) in a range of J>=p>=I+1 are formed and a selector is provided, which selects only a circuit corresponding to the designated value (p) and makes required connection.

Description

[Detailed Description of the Invention] [Summary] Regarding a series PN pattern parallel generation circuit that generates series PN patterns (pseudo-random patterns) in parallel, it is possible to output series PN patterns of any order in parallel with any width. The purpose is to configure the width to be larger than the order of the PN pattern or to be variable within the following specified range, with p, n, m, I and J set to n≧ J≧p≧I,
When n>m is a natural number that satisfies E to be applied to the register in the first row
n consisting of the input values of each of n registers in an n-th order feedback shift register circuit comprising an OR circuit.
n× expressing the relationship between a dimensional number vector and an n-dimensional number vector consisting of the output values of each of the n registers.
A square matrix obtained by raising an n-dimensional square matrix to the first power, and the above J
For each position of p that satisfies ≧p≧I+1, based on the square matrix obtained by raising the square matrix to the pth power, the above J≧p≧I+1
For each position of p that satisfies
Form a matrix of n+J-I rows and n columns with one row element, and
an n-dimensional number vector consisting of the input values of each of the n registers, and an n-dimensional number vector consisting of the output value of each of the n registers;
The relationship with the dimension vector is n×n composed of the pth row to p+n−1 row elements of the n+J−I row n column matrix.
A circuit that connects the input and output of each register to each other as represented by a matrix is provided for each position of p in the range of J≧p≧I+1 using the n registers in common, and Of the circuits that connect the inputs and outputs of each register of the registers to each other for each position of p in the range of J≧p≧I+1, the selector selects and connects only the circuit corresponding to a specified p. Configure it so that

[Industrial application field]

The present invention uses a serial PN pattern (pseudorandom pattern)
This invention relates to a series PN pattern parallel generation circuit that generates PN patterns in parallel.

In order to generate a serial PN pattern (pseudo-random pattern), an M-sequence generation circuit with a period of 2''-1 based on an n-th order generator polynomial is used. In this case, the circuit that generates the serial output must also operate at a bit rate equal to this serial output, which may be difficult to implement or require the use of a circuit configuration that consumes a large amount of power in order to operate at high speed.

Therefore, the technique is to generate a parallel pattern that is equal to a predetermined length of a serial PN pattern by performing parallel/serial conversion, and then to obtain the desired serial pattern by performing parallel/serial conversion on this parallel pattern. It has been known. Thereby, the operating speed of the pseudo-random pattern generation circuit can be slowed down by a multiple equal to the width of the parallel pattern.

Such a series PN pattern (pseudorandom pattern)
The series PN pattern parallel generation circuit generates PN patterns of any order in parallel with any width (
It is desirable to be able to configure a circuit that outputs data with parallelism (degree of parallelism), and furthermore, when such a circuit is to be integrated into an LSI, it is desirable to be able to easily change the degree of parallelism in the same circuit.

[Prior art and problems to be solved by the invention] In the conventional technology, the first method of configuring a series PN pattern parallel generation circuit that generates series PN patterns (pseudorandom patterns) in parallel is to (Parallelism degree) This is used only when p satisfies p=2k, and when the degree of the generator polynomial is n, p identical −M sequences with the phase of the serial pattern shifted by 2”/p bits are used. This is by providing them in parallel.

In addition, the second method is used only when p≦n (p is less than or equal to n), and the n-th order generator polynomial Xh+X″1±1
(1<m<n), a number vector d whose elements are data inputs d+ (i=1 to n) of each of n flip-flop circuits constituting an M-sequence generation circuit with a period of 2111
A' is calculated based on the n-th order square matrix A where d=Aq represents the relationship between the number vector q whose elements are each data output Ql (1=1 to n), and each data input di
A number vector d whose elements are (1=1 to n) and a number vector q whose elements are each data output qt (i=1 to n)
This is done by constructing a circuit whose relationship is expressed by d = AP q, and taking out in parallel the outputs of any p consecutive flip-flop circuits among the n flip-flop circuits that constitute this circuit. .

However, in the past, there was no technology that could easily change the degree of parallelism in the same circuit.

Furthermore, depending on the first and second methods described above, in the case of p'=2 and the case of p≦n, a series PN pattern that generates a series PN pattern (pseudorandom pattern) in parallel, respectively. A parallel generation circuit can be constructed, but a series PN for any other p
There is a problem in that it is not possible to construct a series PN pattern parallel generation circuit that generates patterns (pseudo-random patterns) in parallel.

The present invention has been made in view of the above-mentioned problems, and it is possible to output serial PN patterns of any order in parallel with any width, and to set this width to be larger than the order of the PN pattern. Alternatively, it is an object of the present invention to provide a series PN pattern parallel generation circuit that can be configured to be variable within the following specified range, and to provide a method for configuring the series PN pattern parallel generation circuit. It is something.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic procedure of a method for configuring a series PN pattern parallel generation circuit according to a first embodiment of the present invention. In the first form of the invention, p.

Let n, m, I, and J be natural numbers satisfying n≧J≧p≧I and n>m.

In FIG. 1, (1) is n consisting of n registers.
an n-th stage shift register, and an EOR circuit that applies an exclusive OR of the final stage register output and the m-th stage register output in the shift register to the first stage register. The first step (2) of configuring the feedback shift register circuit is to obtain an n-dimensional number vector consisting of the input values of each of the n registers in the n-stage feedback shift register; The second step is to obtain an n×n-dimensional square matrix that expresses the relationship with the n-dimensional number vector consisting of the value of each output of the register. (3) is to obtain a square matrix that is the square matrix raised to the first power. , a third step of calculating a square matrix obtained by raising the square matrix to the p power for each position of p that satisfies the above j≧p≧I+l; (4) is for each value of p that satisfies the above J≧p≧I+1; , the n-th row vector αp of each of the square matrices raised to the power of Ep is determined, and each of the row vectors αp in the range of J≧p≧I+1 is set to n+p −y11 components, and the n
The fourth step is to form an n+J-I row and n column matrix with xn-dimensional square matrix as 1 to n row elements, and (5) and (6) are The relationship between the n-dimensional number vector consisting of values and the n-dimensional number vector consisting of the output values of each of the n registers is the pth row to p+n-1 of the n+J-I row n column matrix. By using the n registers in common, a circuit that connects the input and output of each register to each other as represented by an n×n matrix composed of row components, and the J≧p≧I
a fifth step of configuring for each value of p in the range J≧p≧I+1, and connecting the input and output of each of the n registers to each other for each value of p in the range J≧p≧I+1; The sixth step is to provide a selector that selects and connects only the circuit corresponding to the specified p.

FIG. 2 is a diagram showing the basic procedure of a method for configuring a series PN pattern parallel generation circuit according to a second embodiment of the present invention. In a second form of the invention, N.

p, n, m, I and J as N≧J≧p≧I>n
>M is a natural number that satisfies.

In FIG. 2, (1) is n consisting of n registers.
an n-th stage shift register, and an EOR circuit that applies an exclusive OR of the final stage register output and the m-th stage register output in the shift register to the first stage register. A feedback shift register circuit, and an N-n circuit connected in series to the output of the last stage register of the n-stage shift registers, and consisting of N-n registers.
The first step [2] of configuring the N-stage feedback shift register composed of the N-stage shift registers includes the N-stage shift register.
Expresses the relationship between an N-dimensional number vector consisting of the input values of each of the N registers in a stage feedback shift register and an N-dimensional number vector consisting of the output values of each of the N registers. The second step to calculate an N×N-dimensional square matrix
Step (3) is a third step of obtaining a square matrix that is the square matrix raised to the 1st power, and for each position of p that satisfies the above J≧p≧I+1, a square matrix that is the square matrix raised to the p power. (4) calculates the row vector αp of the nth row of each square matrix raised to the p power for each position of p that satisfies J≧p≧I+1, and calculates the row vector αp in the range of J≧p≧I+1. Let αp be N+p−1 row components, respectively, and the N×N
The fourth step is to form a matrix of N0J-I rows and N columns with 1 to N row elements as a dimensional square matrix, and (5) and (6) are the inputs of each of the N registers. The relationship between the N-dimensional number vector consisting of the values and the N-dimensional number vector consisting of the output values of each of the N registers is the pth row to p+N-1 of the N+J-4 rows and N columns matrix. A circuit that connects the input and output of each register to each other as expressed by an N×N matrix composed of row components is formed using the N registers in common, and the J≧p≧I
a fifth step configured for each position of p in the range of +1, and a circuit that connects the input and output of each register of the N registers to each other for each position of p in the range of J≧p≧I+1, This shows the sixth step of providing a selector that selects and connects only the circuit corresponding to the specified p.

In addition, in the first and second embodiments of the present invention, in the above-mentioned operation between the matrix and the number vector, addition is performed using exclusive OR.

[For production]

Figure 3 shows the n-th order generator polynomial X"+XI"-' +
1 (1<m<n), an M-sequence generation circuit with a period of 2''-1 (feedback In Fig. 3, 1□, 12. . . In-2+1, ., 1□ are latch circuits (registers), and 2 is an EOR.
circuit, and in each latch circuit, di (i=l
~n) is a data input terminal, and Qi (i=1~n)
indicates an output terminal.

Generator polynomial X" + X' + 11: Base, EOR
By the circuit 2, the output q of the n-1st stage latch circuit 12
The exclusive OR of the outputs q1 of the second and nth stage latch circuits 11 is calculated and applied to the data input dn of the first stage latch circuit 1°.

FIG. 4 shows that pn latch circuits (registers) are connected in series to the output of the final stage register of the n-stage feedback shift register circuit of FIG. 2 by the second step 2 of the present invention.
This figure shows the configuration of a p-stage feedback shift register circuit, which is equivalent to a circuit in which pn-stage shift registers are connected. In Figure 4, IZ+1'2+...1'
, - are pn latch circuits constituting the above pn stage shift register, respectively.

FIG. 5 shows a number vector whose elements are the input values of each of p registers constituting an n-stage feedback shift register circuit, an example of which is shown in FIG. A square matrix showing the relationship with a number vector whose elements are the output values of FIG. 7 is a diagram showing a square matrix showing the relationship between a number vector having elements and a number vector having eight values of each of the p registers as elements; In FIG. 5, N is the above n
or p. FIG. 5 shows N registers, . 12.・・・１□
The input values of 2+lN-1+IN are d1, d2 .
...dN, and the p registers 11+ 12+.
... I W-2+ I N-1+ l )' are expressed as q1, q2 . ...qN, these input values di, d2 . This shows a method of expressing a square matrix showing the relationship between a number vector d whose elements are dN and a number vector q whose elements are these output values q, q2°...qN.

In the representation method shown in FIG. 5, the above square matrix has a period of 2 based on the n-th order generator polynomial
″-1 M-sequence generation circuit (feedback shift register circuit)
In, 1≦i≦N (N is n or p),
The output ql of the first stage register is applied as the input d1-1 of the i-1th stage register, so they are equal to each other, and the output of the mth register and the output of the nth stage register are exclusive. Since the logical sum is applied as an input to the first stage register, (c1, C2, . . . cN) = (cl.

C2,---cp) = (0,...0,1,0゜・
・0. , 0...0), or (cl.

C2, ---CN) = (C1, C2, ...cn)
= (1, O, . . . 0., 0. . . O). Here, in the case of FIG. 3, "1" is n row m+
An element in one column and an element in n rows and one column. For example, in the case of an M-sequence generation circuit (feedback shift register circuit) with a period of 2''-1 based on the generator polynomial X''+x'+1, (CI
, C2,...CN) = (c1, C2,...cp
) = (1, 1, 0...0). Here, "1
'' are the elements in row n and column 1 and the element in row n and column 2. Moreover, in the case of FIG. 4, these are the elements in p rows and p-n+m+1 columns and the elements in p rows and p-n+1 columns. For example, M of period 2h−1 based on the generator polynomial
In the case of a sequence generation circuit (feedback type shift register circuit), (
C1, C2゜...cN) = (C1, C2,...=c
n)=(0,...0.1,,0...0). Here, "1" is the element in p row and p-n+2 column and the element in p row and pn+1 column.

In addition, in the case of FIG. 4, between the number vector d (t) in the t-th cycle of the clock and the number vector Q (t+1) in the t-1th cycle of the clock, there is q (t
+1) = d (t), and the number vector q(1) at the tth cycle of the clock and the t-1th cycle of the clock
Between the number vector q(t-1) in the cycle,
Since there is a relationship of q (t) = Aq (t-1), q
The relationship (t)=Atq(0) holds true. here,
If we set B=A' and r (t)=q (p*t), then r(t)=Btr (0)=A''tQ (0)
=Q (p*t), so not only Q (t) but also r (t) is on the generation sequence of the circuit of FIG. Then, r(t+1)=q(p*(t+1)) is also on the generation sequence of the circuit in FIG. 4, and r(t+1)=
q(p*(t+1))=Br(t)=(A')q
(p*t), so r (t+1)=Q (p*(
Each element of t+1)) undergoes p time slot transitions on its generation sequence for each element of r (t)=q (p*t). Here, in the representation method shown in FIG. 5, the first element rl(t) of the number vector r (t) has undergone p time slot transitions from the p-th element rp (t), so the number vector r The first element rl(t) in (1) is continuous on the generation sequence to the pth element rp(t+1) of the next cycle number vector r(t+1). Therefore, p elements of the number vector r (t) are divided into rp(1
)→rl(t) (parallel/serial conversion), the original generation sequence can be obtained.

N+J-I row N shown in Figure 1 or (4) in Figure 2
The N×N matrix composed of the p-th to p+N-1 row elements of the column matrix X is equal to A' for each position of p in the range of J≧p≧E. Furthermore, (5) in Figure 1 or Figure 2
The components of the pth row to the p+N-1th row of the formula y=xq shown in the formula d= represent the relationship between the input and output of p registers for each position of p in the range of J≧p≧I. It is equal to A'q.

Therefore, for each position of p in the range J≧p≧I, as shown by the p-th row to p+N-1 row components of the equation y=xq shown in (5) of FIG. 1 or FIG. ni p
By configuring a circuit that connects the inputs and outputs of these registers, a circuit that outputs serial PN patterns with a degree of parallelism p can be realized. Furthermore, here, the N registers are made common for each position of p in the range of J≧p≧T, and the input and output of each register are set for each of the points of p in the range of J≧p≧I+1.
Of the circuits connected to each other for the value of p
By providing a selector that selects and connects only the circuit corresponding to J≧p≧
A circuit whose output parallelism can be varied within the range of I+1 can be realized.

FIG. 6 shows the general configuration of the series PN pattern parallel generation circuit constructed in this manner. In FIG. 6, FF11 to FFN are the above n registers, 1
00 is according to equation (5) in FIG. 1 or 2,
Outputs q1, q2 . of registers FF11 to FFN.・・・
・Values y, y2 . which are input values to each register for all p values in the range from qN to J≧p≧1 ...
A circuit that generates yN+J-■, and 5EL11 to 5
ELN is the selector mentioned above, and selects the value input to each register according to the value of the specified degree of parallelism p.
1, y2. ...yN+J-I is selected and applied to the corresponding register.

〔Example〕

[First embodiment of the present invention] In the first embodiment of the present invention, the requirement for the order of the PN pattern is n=5, and the degree of parallelism p is 1≦p≦5.
An example of a procedure for configuring a series PN pattern generation circuit that is variable within the range of 1 and the constructed series PN pattern generation circuit are shown below.

FIG. 7 shows the configuration of a feedback shift register circuit used to construct a serial PN pattern parallel generation circuit in the first embodiment of the present invention. The configuration of FIG. 7 shows an M-sequence generation circuit (feedback type shift register circuit) with a period of 25-1 based on the generating polynomial X5+X2+1, and FF1 to FF5 are flip-flop circuits, respectively, and input di and output qi (i=
1 to 5).

In the configuration shown in FIG. 7, as shown in FIG. 5, a matrix A expressing the relationship between a number vector d whose elements are input values of a register (flip-flop circuit) and a number vector q whose elements are output values is , shown in FIG. Next, the first aspect of the present invention
The matrix X is obtained according to the procedure of the form (FIG. 1). As described above, since ■=1≦p≦5=J, the first to fifth rows of matrix X are equal to matrix A. And the 6th row of matrix X is equal to the 5th row of matrix A2, and the 7th row of matrix X is equal to matrix A3
The 8th row of the matrix X is equal to the 5th row of the matrix A4, and the 9th row of the matrix X is equal to the 5th row of the matrix A5. A matrix X is obtained. Also in the matrix X in FIG. 8, the 2nd to 6th rows are matrix A
2, its third to seventh rows are equal to matrix A3, its fourth to eighth rows are equal to matrix A4, and its fifth to ninth rows are equal to matrix A5.゛Furthermore, the procedure of the first form of the present invention (
By calculating y=xq according to (5) in FIG. 1, the relationship shown on the right side of FIG. 8 is obtained. According to the present invention, the eighth
The first to fifth lines of the relational expression in the figure are equal to the expression d=Aq. The 2nd to 6th lines of the relational expression in FIG. 8 are equal to the equation d=A' q, and the 3rd to 7th lines of the relational expression in FIG. The 4th to 8th lines of the equation are equal to the equation d=A', q, and the 5th to 9th lines of the relational equation in FIG. 8 are the equation d=A5 q
be equivalent to.

That is, here, when making five registers common,
If the inputs and outputs of the five registers are connected so that the relationship of the formula d = Aq (rows 1 to 5 of the relational formula in Figure 8) is established, the parallel series PN pattern obtained from the configuration in Figure 7 An output of degree 1 (that is, this is equivalent to the serial output of the configuration shown in FIG. 7, so it has no practical meaning in itself) is obtained, and the equation d=A2q (2nd to 6th of the relational expressions in FIG. 8) is obtained. line)
If the inputs and outputs of the five registers are connected so that the following relationship holds true, the output of the serial PN pattern obtained from the configuration shown in Fig. 7 with a degree of parallelism of 2 can be obtained from any two consecutive registers. , formula d=A3q (the third to the relational formulas in Figure 8)
If the input and output of the five registers are connected so that the relationship (7 rows) is established, the output of the serial PN pattern obtained from the configuration shown in Figure 7 with a degree of parallelism of 3 will be output from any three consecutive registers. By connecting the 8 inputs of the 5 registers so that the relationship of the equation d=A' q (lines 4 to 8 of the relational equation in Fig. 8) is established, we obtain the result from the configuration shown in Fig. 7. The parallelism degree 4 output of the serial PN pattern obtained by When the inputs and outputs of the five registers are connected, outputs of the serial PN pattern with a degree of parallelism of 5 obtained from the configuration shown in FIG. 7 can be obtained from the five registers. Here, the order in which the pits of the M-sequence serial PN pattern are lined up in the output from the above-mentioned consecutive registers is determined by the order of the data flowing through the register (flip-flop circuit) with the configuration shown in FIG. 7 corresponding to the elements of the number vector q. Corresponding in order, Q5. Q4. ...The order is ql.

Further, according to the present invention, a selector is provided for switching any one of the five types of connections between the input and output of the five registers in accordance with the designation of the degree of parallelism. The results are shown in FIG.

In FIG. 9, the configuration within the dashed line 101 consists of the outputs q, q2, . . . . 8 forces corresponding to the 9 elements on the right side of the relational expression in FIG. 8 are obtained from q5. Here, as described above, since addition is performed using exclusive OR in the calculation of a matrix and a number vector, each addition is realized by an EOR circuit. The selector 5EL12 in FIG. 9 selects y1, .
1, and the selector 5EL22 in FIG.
Among the outputs of the circuit 101, depending on which of 1 to 5,
respectively, y2. ...y6 is selected and applied to the data input d2 of the flip-flop circuit FF22, and the selector 5EL32 in FIG. ,y3. ...
y1 is selected and applied to the data input d3 of the flip-flop circuit FF32, and the selector 5EL42 in FIG. 9 selects y4. ... Select y8 and apply it to the data input d4 of the flip-flop circuit FF42, and
The selector 5EL52 in the figure selects y5.
...y9 is selected and applied to the data input d5 of the flip-flop circuit FF52. In this way, in the configuration of FIG. 9, depending on the specification of the degree of parallelism p, the above equation d=Aq
, formula d=A2q, formula d=A3q.

The inputs and outputs of the five registers are connected so that either of the following relationships: d=A'C1 and d=A5q hold true. In the configuration of FIG. 9, as shown in the multiplexing order, the order in which each bit of the M series of serial PN patterns is arranged in the output from the consecutive registers is the order in which each bit corresponds to the element of the number vector q. Registers with the configuration shown in Figure 7 (
q5° | q4 . ...The order is ql. Note that this order may be changed cyclically. Thus, by multiplexing these parallel outputs in the above order, a 5th order series PN pattern having a period of 25-1 is obtained.

[Second Embodiment of the Present Invention] In the second embodiment of the present invention, the requirement for the order of the PN pattern is n=7, and the degree of parallelism p is 4≦p≦6.
An example of a procedure for configuring a series PN pattern generation circuit that is variable within the range of 1 and the constructed series PN pattern generation circuit are shown below.

FIG. 10 shows the configuration of a feedback shift register circuit used for constructing a serial PN pattern parallel generation circuit in a second embodiment of the present invention. The configuration in FIG. 10 is based on the generator polynomial x'+x'+1, with period 27
-1 M sequence generation circuit (feedback type shift register circuit), FFI to FF7 are flip-flop circuits, respectively, and input di and output qi
(i=1 to 7).

In the configuration of FIG. 10, as shown in FIG.
A matrix A expressing the relationship between a number vector d whose elements are the input values of the (flip-flop circuit) and a number vector q whose elements are the output values is shown in FIG. Next, the matrix X is determined according to the procedure of the first embodiment of the present invention (FIG. 1). As mentioned above, since I=4≦p≦6=J, the first to seventh rows of matrix X are equal to matrix A4. Then, the 8th row of matrix X is equal to the 7th row of matrix A5, and the 9th row of matrix . Also in the matrix X in FIG. 11, the 2nd to 8th rows are equal to matrix A5, and
9 rows is equal to matrix A6. Furthermore, when y=xq is calculated according to the procedure of the first embodiment of the present invention (FIG. 1 (5)), the relationship shown on the right side of FIG. 11 is obtained. According to the present invention, the first to seventh lines of the relational expression in FIG. 11 are the expression d=A' q
be equivalent to. The 2nd to 8th lines of the relational expression in FIG. 11 are equal to the equation d-A5 q, and the 3rd to 9th lines of the relational equation in FIG. 11 are equal to the equation d=A6 q.

That is, here, when making seven registers common,
If the inputs and outputs of the seven registers are connected so that the relationship of the formula d=A' q (lines 1 to 7 of the relational formula in Figure 11) is established, the series PN pattern obtained from the configuration in Figure 10 is obtained. An output with a degree of parallelism of 4 is obtained from any four consecutive registers, and the equation d=A5q (2nd to 8th of the relational equations in FIG. 11)
If the inputs and outputs of the seven registers are connected so that the relationship (row) is established, the output of the serial PN pattern obtained from the configuration shown in FIG. By connecting the inputs and outputs of the seven registers so that the relationship of formula d = A6q (lines 3 to 9 of the relational formula in Figure 11) is established, the series PN obtained from the configuration in Figure 10 is obtained. Outputs with a pattern parallelism of 6 are obtained from any six consecutive registers. Here, the order in which each bit of the M-sequence serial PN pattern is arranged in the output from the above-mentioned consecutive registers is determined by the order of the data flowing through the register (flip-flop circuit) having the configuration shown in FIG. 10 corresponding to the element of the number vector q. Corresponding in order, Q? .

q6. ...The order is ql.

Further, according to the present invention, a selector is provided for switching any one of the three types of connections between the input and output of the seven registers according to the designation of the degree of parallelism. The results are shown in FIG.

In FIG. 12, the configuration within the broken line 102 is the first configuration described above.
In order to obtain the three types of connections obtained from the relational expression in Figure 1,
The first output from the seven registers q1, q2゜...ql
Outputs corresponding to the nine elements on the right side of the relational expression in FIG. 1 are obtained. Here, as described above, since addition is performed using exclusive OR in the calculation of a matrix and a number vector, each addition is realized by an EOR circuit. The selector 5EL13 in FIG. 12 selects the outputs of the circuit 102, y1, .
y3 is selected and applied to the data input d1 of the flip-flop circuit FF13, and the selector 5EL23 in FIG.
Depending on whether the degree of parallelism p is 4 to 6, the outputs of the circuit 102 are y2. . . . y4 is selected and applied to the data input d2 of the flip-flop circuit FF23, and the selector 5EL33 in FIG.
y3 . ...Select y5 and flip-flop circuit F
F33 is applied to the data input d3, and the selector 5EL43 in FIG. 12 selects y4. ...Select y6 and input data d of flip-flop circuit FF43
4, and the selector 5EL53 in FIG. 12 selects y5. ...yl is selected and applied to the data input d5 of the flip-flop circuit FF53. In this way, in the configuration shown in FIG. 12, depending on the specification of the degree of parallelism p, any of the relationships among the above equations d=A' C1, d=AS q, and d=A'' q hold true. The inputs and outputs of the seven registers are connected as shown in FIG. The order in which the bits are arranged is ql, which corresponds to the order of data flowing through the register (flip-flop circuit) having the configuration shown in FIG. 10, which corresponds to the elements of the number vector q.

Q6. ...The order is ql. Note that this order may be changed cyclically. Thus, by multiplexing these parallel outputs in the above order, a 7th order series PN pattern having a period of 27-1 is obtained.

[Third Embodiment of the Present Invention] In the third embodiment of the present invention, the requirement for the order of the PN pattern is n=7, and the degree of parallelism p is 8≦p≦9.
An example of a procedure for configuring a series PN pattern generation circuit that is variable within the range of 1 and the constructed series PN pattern generation circuit are shown below.

FIG. 13 shows the configuration of a feedback shift register circuit used for constructing a serial PN pattern parallel generation circuit in a third embodiment of the present invention. The configuration in FIG. 13 is based on the generator polynomial x7+x'+1, with a period of 27−
A 2-bit shift register is connected in series to the output side of the M-sequence generation circuit (feedback type shift register circuit) No. 1, and FF15 to FF95 are flip-flop circuits, respectively, and inputs di and output qi
(i=1 to 9).

In the configuration of FIG. 13, as shown in FIG.
A matrix A expressing the relationship between a number vector d whose elements are input values of a flip-flop circuit and a number vector q whose elements are output values is shown in FIG. Next, the matrix X is determined according to the procedure of the second embodiment of the present invention (FIG. 2).

As mentioned above, since ■=8≦p≦9=J, the matrix
The first to ninth rows of are equal to matrix A8. Then, since the 10th row of matrix X is equal to the 9th row of matrix A9, the 14th row
A matrix X is obtained as shown in the figure. The second to tenth rows of matrix X in FIG. 14 are also equal to matrix A9.

Furthermore, when y=xq is calculated according to the procedure of the second embodiment of the present invention ((5) in FIG. 1), the relationship shown on the right side of FIG. 14 is obtained.

According to the present invention, the first to ninth lines of the relational expression in FIG. 14 are replaced by the expression d=
Equal to A8q. Then, 2nd to 1st of the relational expressions in FIG.
Row 0 is the formula d=A9 (equal to l.

That is, here, when making nine registers common,
If the inputs and outputs of the nine registers are connected so that the relationship of the formula d=A''q (lines 1 to 9 of the relational formula in Figure 14) is established, the series PN pattern obtained from the configuration in Figure 13 is obtained. An output with a parallelism of 8 is obtained from any eight consecutive registers, and the equation d=A' q (the second relational expression in FIG.
By connecting the inputs and outputs of the nine registers so that the relationship (from rows 10 to 10) holds, the output of the serial PN pattern with a degree of parallelism of 9 obtained from the configuration shown in Fig. 13 is obtained from the nine consecutive registers. It will be done. Here, the order in which each bit of the M-series serial PN pattern is arranged in the output from the above-mentioned consecutive registers is determined by the order in which the bits of the M-sequence serial PN pattern are arranged according to the data flowing through the register (flip-flop circuit) having the configuration shown in FIG. 13 corresponding to the element of the number vector q. Corresponding in order, q9. q8. ...The order is ql.

Further, according to the present invention, a selector is provided for switching between the two types of connections between the input and output of the nine registers according to the designation of the degree of parallelism. The results are shown in FIG.

In FIG. 15, the configuration within the broken line 103 is the first configuration described above.
In order to obtain the two types of connections obtained from the relational expression in Figure 4,
Outputs of nine registers Q1, Q2゜...q9 to the first
Outputs corresponding to the 10 elements on the right side of the relational expression in FIG. 4 are obtained. Here, as described above, since addition is performed using exclusive OR in the calculation of a matrix and a number vector, each addition is realized by an EOR circuit. The selector 5EL14 in FIG. 15 selects yl and y2 from the outputs of the circuit 103 depending on whether the degree of parallelism p is 8 or 9 and applies them to the data input d1 of the flip-flop circuit FF14, Selector 5EL24 in Figure 15
is the circuit 10 depending on whether the degree of parallelism p is 8 or 9.
Out of the outputs of 3, y2 and y3 are selected and applied to the data input d2 of the flip-flop circuit FF24, and the selector 5EL34 in FIG. Out of the outputs of 103, y3 and y4 are respectively selected and applied to the data input d3 of the flip-flop circuit FF34, and the selector 5EL44 in FIG. Out of the outputs of 103, y4 and y5 are selected and applied to the data input d4 of the flip-flop circuit FF44, and the selector 5EL54 in FIG.
Depending on whether the degree of parallelism p is 8 or 9, y5 and y6 are selected from among the outputs of the circuit 103 and applied to the data input d5 of the flip-flop circuit FF54,
The selector 5EL64 in FIG. 15 selects y6 and yl from the outputs of the circuit 103 depending on whether the degree of parallelism p is 8 or 9, respectively, and selects the flip-flop circuit F.
F64 data input d6, selector 5EL74 in FIG.
is selected and applied to the data input d7 of the flip-flop circuit FF74, and the selector 5EL84 in FIG. is selected and applied to the flip-flop circuit FF84 (Df-1 input d8), and the 15th rl! y9 and ylO are selected and applied to the data input d9 of the flip-flop circuit FF94, respectively.

In this way, in the configuration shown in FIG. 15, depending on the specification of the degree of parallelism p, the above equations d=A''q and d=A9
The inputs and outputs of the nine registers are connected so that any one of the relationships q holds true. In the configuration of FIG. 15, as shown in the multiplexing order, the order in which each bit of the M series of serial PN patterns is arranged in the output from the consecutive registers is the order in which each bit corresponds to the element of the number vector q. Corresponding to the order of data flowing through the register (flip-flop circuit) having the configuration shown in FIG. 13, q9. q8. ...The order is ql. Note that this order may be changed cyclically.

Thus, by multiplexing these parallel outputs in the above order, a 7th order series PN pattern having a period of 27-1 is obtained.

[Application example]

FIG. 16 shows an example of application of the series PN pattern parallel generation circuit according to the present invention. FIG. 16 shows parallel input data d1, d2 . When multiplexing and serially transmitting d8, instead of scrambling the serial data with a serial PN pattern, the parallel input data di, d2 .
. . d8 are scrambled (exclusive ORed) using the parallel outputs r1 to r8 of the serial PN pattern parallel generation circuit 113 shown in FIG. 16, respectively. As described above, the parallel outputs r1 to r8 of the serial PN pattern parallel generation circuit 113 according to the present invention are parallel patterns that become equal to a predetermined length portion of the serial PN pattern by performing parallel/serial conversion, Furthermore, parallel input data dl in FIG.

d2. . . d8 is multiplexed in the multiplexing circuit after the above scrambling, so that the same serial data as serial data scrambled with a serial PN pattern can be obtained with the configuration shown in FIG.

〔Effect of the invention〕

According to the series PN pattern parallel generation circuit of the present invention, it is possible to output serial PN patterns of any order in parallel with any width, and this width is greater than the order of the PN pattern, or It can be configured to be variable within the specified range below.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic procedure for configuring a series PN pattern parallel generation circuit according to a first embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a series PN pattern parallel generation circuit according to a second embodiment of the present invention. Figure 3 is a diagram showing the configuration of an n-stage feedback shift register circuit; Figure 4 is a diagram showing the basic steps of the method; Figure 4 is a diagram showing the configuration of an n-stage feedback shift register circuit; p consisting of p−n registers
-A diagram showing the configuration of a p-stage feedback shift register circuit formed by connecting n-stage shift registers; FIG. 5 shows the configuration of an n-stage feedback shift register circuit, an example of which is shown in FIG. 3. A square matrix showing the relationship between a number vector whose elements are the input values of each of the p registers and a number vector whose elements are the output values of each of the p registers, or an example shown in Fig. 4. A number vector whose elements are the input values of each of the p registers constituting a p-stage feedback shift register circuit such as shown in FIG. FIG. 6 is a diagram showing a general configuration of a series PN pattern parallel generation circuit constructed according to the present invention, and FIG. FIG. 8 is a diagram showing the configuration of a feedback shift register circuit used in a parallel generator circuit, FIG. 8 is a diagram showing matrices X and A in the first embodiment of the present invention, and FIG. 9 is a diagram showing the matrix X and A in the first embodiment of the invention. FIG. 10 is a diagram showing the configuration of the serial PN pattern parallel generation circuit in the first embodiment of the present invention, and FIG. 10 is a feedback shift register circuit used to configure the series PN pattern parallel generation circuit in the second embodiment of the present invention. 11 is a diagram showing the matrix X and A in the second embodiment of the present invention. FIG. 12 is a diagram showing the configuration of the series PN pattern parallel generation circuit in the second embodiment of the present invention. FIG. 13 is a diagram showing the configuration of a feedback shift register circuit used to configure a series PN pattern parallel generation circuit in the third embodiment of the present invention, and FIG. 15 is a diagram showing the configuration of the series PN pattern parallel generation circuit in the third embodiment of the present invention, and FIG. FIG. 3 is a diagram showing an example of an application of a PN pattern parallel generation circuit. [Explanation of symbols] FFI to FF9. FF11~FFN, FF12~FF5
2. FF13~FF73. FF14-FF94. FF1
5~FF95 register (flip-flop circuit)
, 5EL11 ~ 5ELN, 5EL12 ~ 5EL52.5
EL13~5EL73, 5EL14~5EL94 Selector, 2.21, 22.31~35.41~46°1~59-
- EOR circuit, 113 series PN pattern parallel generation circuit, 110 multiplexing circuit.

Claims (1)

[Claims] 1, p, n, m, I and J, n≧J≧p≧I, n>m
is a natural number that satisfies, then the exclusive OR of an n-stage shift register consisting of n registers, the register output of the final stage and the register output of the m-th stage in the shift register is calculated as the first-stage register output. an n-dimensional number vector consisting of the input values of each of the n registers in an n-dimensional feedback shift register circuit comprising an EOR circuit that applies an signal to the register; A square matrix that is the Ith power of an n×n-dimensional square matrix that expresses the relationship with an n-dimensional number vector consisting of values,
And, for each value of p that satisfies J≧p≧I+1, based on the square matrix that is the square matrix raised to the pth power, for each value of p that satisfies the above J≧p≧I+1, the square matrix is raised to the pth power. The n-th row vector α_p of each square matrix has n+p-1 row elements, and the n×n-dimensional square matrix has 1 to n row elements to form an n+J-I row and n-column matrix. Then, the relationship between the n-dimensional number vector consisting of the input values of each of the n registers (FF11 to FFN) and the n-dimensional number vector consisting of the output value of each of the n registers is the above n+J. - A circuit (1
00) for each value of p in the range of J≧p≧I+1 using the n registers (FF11 to FFN) in common, and each register of the n registers (FF11 to FFN) Selectors (SEL11 to SELN) that select and connect only the circuit corresponding to a specified p from the circuits (100) that connect the input and output of to each other for each value of p in the range of J≧p≧I+1. 1. A series PN pattern parallel generation circuit comprising: 2. When calculating the square matrix and the number vector, addition is performed by exclusive OR, and the connection corresponding to the addition is EO
2. The series PN pattern parallel generation circuit according to claim 1, which is implemented by an R circuit. 3. The number vector consisting of the input values is configured with the input values of each of the n registers as elements corresponding to the order or reverse order of data flow in the n-stage feedback shift register, A number vector consisting of the output values is set in the n-stages corresponding to the order or reverse order of the data flow in the n-stage feedback shift register.
2. The serial PN pattern parallel generation circuit according to claim 1, wherein the serial PN pattern parallel generation circuit is constructed by using the output values of each of the registers as elements. 4, p, n, m, I and J, n≧J≧p≧I, n>m
is a natural number that satisfies, then the exclusive OR of an n-stage shift register consisting of n registers, the register output of the final stage and the register output of the m-th stage in the shift register is calculated as the first-stage register output. a first step (1) of configuring an n-th feedback shift register circuit comprising an EOR circuit that applies an voltage to the register; Second step (2) of finding an n×n dimensional square matrix expressing the relationship between the n-dimensional number vector consisting of the values and the n-dimensional number vector consisting of the output values of each of the n registers. Then, obtain a square matrix by raising the square matrix to the I power, and satisfy the above J≧p≧
For each value of p that satisfies I+1, let the square matrix be p
The third step (3) is to obtain a square matrix raised to the power of Each of the row vectors α_p in the range of J≧p≧I+1 has n+p−1 row elements, and the n×n-dimensional square matrix has 1 to n row elements to form an n+J−I row and n column matrix. The fourth step (4) is the relationship between the n-dimensional number vector consisting of the input value of each of the n registers and the n-dimensional number vector consisting of the output value of each of the n registers. n× composed of the pth row to p+n−1 row elements of the n+J−I row n column matrix;
A fifth circuit that connects the inputs and outputs of each register to each other as represented by an n matrix is configured for each value of p in the range of J≧p≧I+1 by using the n registers in common. step (5), and among the circuits that connect the inputs and outputs of each of the n registers to each other for each value of p in the range of J≧p≧I+1, only the circuit that corresponds to the specified p. The sixth step (6) is to provide a selector to select and connect
A method of configuring a series PN pattern parallel generation circuit, comprising: 5. When calculating the square matrix and the number vector, addition is performed by exclusive OR, and the connection corresponding to the addition is EO
5. The method of configuring a series PN pattern parallel generation circuit according to claim 4, wherein the method is performed using an R circuit. 6. The number vector consisting of the input values is configured with the input values of each of the n registers as elements corresponding to the order or reverse order of data flow in the n-stage feedback shift register, The number vector consisting of the output values is configured with the output values of each of the n registers as elements corresponding to the order or reverse order of the data flow in the n-stage feedback shift register. A method of configuring a series PN pattern parallel generation circuit according to item 1. 7, N, p, n, m, I and J, N≧J≧p≧I>n
> When m is a natural number satisfying, the first stage is an exclusive OR of an n-stage shift register consisting of n registers, the register output of the final stage in the shift register, and the register output of the m-th stage. EOR applied to eye register
an n-order feedback shift register circuit comprising a circuit;
and an N-stage feedback shift register that is connected in series to the output of the final stage register of the n-stage shift register, and that is composed of an N-n stage shift register including N-n registers. Let I be an N×N square matrix that expresses the relationship between an N-dimensional number vector consisting of the input values of each of the registers and an N-dimensional number vector consisting of the output values of each of the N registers. For each value of p that satisfies J≧p≧I+1, the J
For each value of p that satisfies ≧p≧I+1, the p-th row vector α_p of each of the p-th power square matrices is set as the N+p-1 row element, and the N×N-dimensional square matrix is A matrix of N+J-I rows and N columns with ~N row components is formed, and an N-dimensional number vector consisting of the input values of each of the N registers (FF11 to FFN) and the N registers (FF11 to FFN) are formed.
The relationship with the N-dimensional number vector consisting of the output values of each of F11 to FFN) is the p-th
The N registers (FF11 to
FFN) is used in common for each value of p in the range of J≧p≧I+1, and the input and output of each of the N registers (FF11 to FFN) is set to the value of J≧p≧I+1. A selector (SEL) that selects and connects only the circuit corresponding to the specified p among the circuits connected to each other for each value of p in the range.
11 to SELN)
N pattern parallel generation circuit. 8. When calculating the square matrix and the number vector, addition is performed by exclusive OR, and the connection corresponding to the addition is EO
8. The series PN pattern parallel generation circuit according to claim 7, which is implemented by an R circuit. 9. The number vector consisting of the input values is configured with input values of each of the p registers as elements corresponding to the order or reverse order of data flow in the p-stage feedback shift register, A number vector consisting of the output values is set in the p-stage corresponding to the order or reverse order of the data flow in the p-stage feedback shift register.
8. The serial PN pattern parallel generation circuit according to claim 7, wherein the serial PN pattern parallel generation circuit is constructed using the output values of each of the registers as elements. 10, N, p, n, m, I and J, N≧J≧p≧I>
When n is a natural number satisfying n>m, the exclusive OR of an n-stage shift register consisting of n registers, the register output of the final stage in the shift register, and the register output of the m-th stage is expressed as the first EO applied to the register in the first row
an n-th order feedback shift register circuit comprising an R circuit; and an N-n stage consisting of N-n registers connected in series to the output of the final stage register of the n-stage shift register. a first step (1) of configuring an N-stage feedback shift register consisting of shift registers; a second step (2) of obtaining an N×N-dimensional square matrix expressing the relationship between the number vector and the N-dimensional number vector consisting of the output values of each of the N registers; Find a square matrix raised to the I power, and satisfy the above J≧p≧
For each value of p that satisfies I+1, let the square matrix be p
The third step (3) is to obtain a square matrix raised to the power of Each of the row vectors α_p in the range of J≧p≧I+1 has N+p−1 row components, and the N×N-dimensional square matrix has 1 to N row components to form an N+J−I row and N matrix. The fourth step (4) is the relationship between the N-dimensional number vector consisting of the input values of each of the N registers and the N-dimensional number vector consisting of the output values of each of the N registers. N× composed of the pth row to p+N−1 row elements of the N+J−I row N column matrix
A fifth circuit configured for each value of p in the range of J≧p≧I+1, using the N registers in common, and forming a circuit that connects the inputs and outputs of each register to each other as represented by an N matrix. step (5), and among the circuits that connect the inputs and outputs of each of the N registers to each other for each value of p in the range of J≧p≧I+1, only the circuit that corresponds to the specified p. The sixth step (6) is to provide a selector to select and connect
A method of configuring a series PN pattern parallel generation circuit, comprising: 11. When calculating the square matrix and the number vector, addition is performed by exclusive OR, and the connection corresponding to the addition is E.
11. The method of configuring a series PN pattern parallel generation circuit according to claim 10, wherein the method is performed using an OR circuit. 12. The number vector consisting of the input values is configured with the input values of each of the p registers as elements corresponding to the order or reverse order of data flow in the p-stage feedback shift register, The number vector consisting of the output values is configured with the output values of each of the p registers as elements corresponding to the order or reverse order of the data flow in the p-stage feedback shift register. Item 1
A method of configuring a series PN pattern parallel generation circuit as described in 0.