JPH0456798B2 - - Google Patents

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Publication number
JPH0456798B2
JPH0456798B2 JP506786A JP506786A JPH0456798B2 JP H0456798 B2 JPH0456798 B2 JP H0456798B2 JP 506786 A JP506786 A JP 506786A JP 506786 A JP506786 A JP 506786A JP H0456798 B2 JPH0456798 B2 JP H0456798B2
Authority
JP
Japan
Prior art keywords
sio
film
substrate
silicon substrate
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP506786A
Other languages
Japanese (ja)
Other versions
JPS62167289A (en
Inventor
Atsushi Ogura
Tooru Tatsumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP506786A priority Critical patent/JPS62167289A/en
Publication of JPS62167289A publication Critical patent/JPS62167289A/en
Publication of JPH0456798B2 publication Critical patent/JPH0456798B2/ja
Granted legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、シリコン基板の加工方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of processing a silicon substrate.

〔従来の技術〕[Conventional technology]

従来、シリコン(Si)基板の加工方法として
は、例えば超LSIプロセスデータハンドブツク
(サイエンスフオーラム社、昭和57年)380ページ
〜492ページにあるようにホトリソグラフイとプ
ラズマ、反応性イオン等を用いたドライエツチン
グが一般的であつた。
Traditionally, silicon (Si) substrate processing methods have used photolithography, plasma, reactive ions, etc., as described in VLSI Process Data Handbook (Science Forum, 1981), pages 380 to 492. Dry etching was common.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし従来の方法ではエツチングガスによる基
板表面の汚染、ダメージ等の問題があつた。
However, the conventional method has had problems such as contamination and damage to the substrate surface due to etching gas.

本発明の目的は、従来のエツチングによる基板
加工技術に代わり、Si分子線エピタキシヤル成長
(MBE)法を利用して基板表面の汚染、ダメージ
等のないシリコン基板の加工方法を提供する事に
ある。
An object of the present invention is to provide a method for processing a silicon substrate that does not cause contamination or damage to the substrate surface by using Si molecular beam epitaxial growth (MBE) instead of the conventional substrate processing technology using etching. .

〔問題点を解決するための手段〕[Means for solving problems]

本発明のシリコン基板の加工方法は、シリコン
基板表面にSiO2膜を形成し、このSiO2膜に溝を
形成し、SiO2膜がエツチングされると共にシリ
コン基板表面にエピタキシヤル成長が起こる基板
温度および照射条件で、Si分子線を少なくとも
SiO2膜が完全に無くなるまで照射することを特
徴としている。
The silicon substrate processing method of the present invention involves forming a SiO 2 film on the surface of the silicon substrate, forming grooves in the SiO 2 film, and increasing the substrate temperature at which the SiO 2 film is etched and epitaxial growth occurs on the silicon substrate surface. and irradiation conditions, the Si molecular beam is at least
It is characterized by irradiation until the SiO 2 film is completely removed.

〔作用〕[Effect]

以下に、本発明によつて従来技術に比べ基板表
面の汚染、ダメージ等のないシリコン基板の加工
方法が得られる原理を説明する。
The principle by which the present invention provides a method for processing a silicon substrate that causes less contamination and damage to the substrate surface than in the prior art will be explained below.

Si基板上に形成されたSiO2膜にSi分子線を照射
すると、通常は、SiO2膜上に非晶質あるいは多
晶質シリコンが堆積される。しかし、この際に基
板の温度をある温度以上に保てばSiO2膜がエツ
チングされる。例えば、ジヤパニーズ・ジヤーナ
ル・オブ・アプライド・フイジクス(Jpn.J.
Appl.Phys.)21巻、1982年、534ページに記載さ
れている様に、基板表面へのSi分子の到達密度が
1.1×1016cm-2sec-1の場合、基板温度1000℃以上
でSiO2膜のエツチング現象が起こる。この際
(基板温度1000℃)のエツチング速度は約35Å/
secであり、この条件でSi清浄表面上では速度20
Å/secのMBE成長が起こる。
When a SiO 2 film formed on a Si substrate is irradiated with a Si molecular beam, amorphous or polycrystalline silicon is usually deposited on the SiO 2 film. However, if the temperature of the substrate is kept above a certain temperature at this time, the SiO 2 film will be etched. For example, Japanese Journal of Applied Physics (Jpn.J.
Appl.Phys.) Volume 21, 1982, page 534, the density of Si molecules reaching the substrate surface is
In the case of 1.1×10 16 cm -2 sec -1 , the etching phenomenon of the SiO 2 film occurs when the substrate temperature is 1000°C or higher. At this time (substrate temperature 1000℃) the etching rate is approximately 35Å/
sec, and under these conditions the speed is 20 on the Si clean surface.
MBE growth of Å/sec occurs.

そこでSi基板上にSiO2部とSi露出部を設け前記
の条件でMBE成長を行なえばSiO2はエツチング
されSi露出部ではエピタキシヤル成長し、SiO2
が完全に除去された後に最初のSiO2と逆のパタ
ーンに加工されたSi基板が得られる。また、最初
にSiO2の厚い部分と薄い部分を設けておくと、
初め一様にSiO2のエツチングが起こつた後に、
前述と同様なエツチングとエピタキシヤル成長の
同時進行が起こり、やはりSi基板を加工すること
ができる。
Therefore, if a SiO 2 part and an exposed Si part are provided on the Si substrate and MBE growth is performed under the above conditions, the SiO 2 will be etched and the exposed Si part will grow epitaxially, and the SiO 2
After completely removing SiO 2 , a Si substrate is obtained which is processed into a pattern opposite to that of the original SiO 2 . Also, if you first prepare thick and thin parts of SiO 2 ,
After uniform etching of SiO 2 occurs at first,
Etching and epitaxial growth occur simultaneously as described above, and the Si substrate can still be processed.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して説
明する。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例の加工工程を示
した断面図である。まずシリコン(100)基板
10の表面に熱酸化によつてSiO2膜20を膜厚
2μm形成した後、このSiO2膜20に通常のホト
リソグラフイ技術と反応性イオンエツチング技術
で幅、深さとも2μmのストライプ状の溝30を
掘り、Si基板10を露出させると第1図aの状態
が得られる。
FIG. 1 is a sectional view showing the processing steps of the first embodiment of the present invention. First, a thick SiO 2 film 20 is deposited on the surface of a silicon (100) substrate 10 by thermal oxidation.
After forming the SiO 2 film 20 with a thickness of 2 μm, stripe-shaped grooves 30 with a width and depth of 2 μm are dug in the SiO 2 film 20 using conventional photolithography and reactive ion etching techniques to expose the Si substrate 10, as shown in FIG. 1a. The following state is obtained.

次にこの基板をMBE装置に導入し、アルゴン
スパツタ法でSi露出部に清浄表面を得た後、基板
温度1000℃でSi分子線を基板への到達密度1.1×
1016cm-2sec-1で照射した。するとSiO2膜20の
エツチングとSi露出部でのMBE成長が同時に起
こり、第2図bに示すようにSiO2膜20の膜厚
は減少し、Si露出部にシリコンエピタキシヤル成
長層40が形成されてくる。この状態を経て、約
10分後にSiO2膜20がエツチングにより完全に
除去され、第1図cに示す様な形状に加工された
Si基板が得られる。
Next, this substrate was introduced into an MBE device, and after obtaining a clean surface on the Si exposed part using the argon sputtering method, Si molecular beams were applied to the substrate at a density of 1.1× at a substrate temperature of 1000°C.
Irradiation was performed at 10 16 cm -2 sec -1 . Then, etching of the SiO 2 film 20 and MBE growth on the exposed Si portion occur simultaneously, and as shown in FIG. 2b, the thickness of the SiO 2 film 20 decreases, and a silicon epitaxial growth layer 40 is formed on the exposed Si portion. It will be done. After this state, approximately
After 10 minutes, the SiO 2 film 20 was completely removed by etching and processed into the shape shown in Figure 1c.
A Si substrate is obtained.

さらに第1図cの状態からMBE成長を続ける
と、基板表面がシリコンエピタキシヤル成長層4
0のみで覆われた同様な形状に加工されたSi基板
が得られる。
Further, when MBE growth is continued from the state shown in Figure 1c, the substrate surface becomes a silicon epitaxial growth layer 4.
A Si substrate processed into a similar shape covered only with zero is obtained.

第2図は本発明の第2の実施例の加工工程を示
した断面図である。まずシリコン(100)基板
50の表面に熱酸化によつてSiO2膜60を膜厚
2.2μm形成した後、通常のホトリソグラフイ技術
と反応性イオンエツチング技術でSi基板50を露
出させることなく幅、深さとも2μmのストライ
プ状の溝70を掘ると第2図aの状態が得られ
る。
FIG. 2 is a sectional view showing the processing steps of a second embodiment of the present invention. First, a thick SiO 2 film 60 is deposited on the surface of a silicon (100) substrate 50 by thermal oxidation.
After forming 2.2 μm, a striped groove 70 with a width and depth of 2 μm is dug using ordinary photolithography and reactive ion etching without exposing the Si substrate 50, resulting in the state shown in Figure 2a. It will be done.

次にこの基板をMBE装置に導入し、第1の実
施例と同様に基板温度1000℃でSi分子線を基板へ
の到達密度1.1×1016cm-2sec-1で照射した。する
とSiO2膜60がエツチングされ、約2.5分後に第
2図bに示す様にSiO2膜60に覆われた部分と
Siが露出した部分が得られ、第1の実施例で述べ
た第1aと同じ状態が得られる。
Next, this substrate was introduced into an MBE apparatus, and the substrate was irradiated with a Si molecular beam at a substrate temperature of 1000° C. at a density of 1.1×10 16 cm −2 sec −1 as in the first example. Then, the SiO 2 film 60 is etched, and after about 2.5 minutes, the part covered with the SiO 2 film 60 and the part covered with the SiO 2 film 60 are etched as shown in FIG. 2b.
A portion where Si is exposed is obtained, and the same state as 1a described in the first embodiment is obtained.

その後に第1の実施例で述べたのと同じ条件
で、残つたSiO2膜60のエツチングとSi露出部
でのMBE成長を同時に行なうと、SiO2膜60が
エツチングにより除去され、かつシリコンエピタ
キシヤル成長層80が形成されて第2図cの形状
に加工されたSi基板が得られる。
Thereafter, under the same conditions as described in the first embodiment, etching of the remaining SiO 2 film 60 and MBE growth on the exposed Si portion are performed simultaneously, the SiO 2 film 60 is removed by etching, and the silicon epitaxy is A silicon substrate is obtained which is formed with a hollow growth layer 80 and processed into the shape shown in FIG. 2c.

さらに第1の実施例と同様に第2図cの状態か
らMBE成長を続けると、基板表面がシリコンエ
ピタキシヤル成長層80のみで覆われた同様な形
状に加工されたSi基板が得られる。
Furthermore, if MBE growth is continued from the state shown in FIG. 2c in the same manner as in the first embodiment, a Si substrate processed into the same shape with the substrate surface covered only with the silicon epitaxial growth layer 80 is obtained.

以上の2つの実施例ではシリコン(100)基
板を用いた例を示したが、他の方位の基板を用い
ても同様な加工を行なうことができる。また、基
板温度、Si分子の基板への到達密度等も以上の実
施例に限定されるものではない。また、SiO2
への加工形状はストライプ状に限られるものでは
なく、他の形状に加工することによつて様々な形
状に加工されたSi基板を得ることができる。
In the above two embodiments, examples using silicon (100) substrates were shown, but similar processing can be performed using substrates with other orientations. Further, the substrate temperature, the density of Si molecules reaching the substrate, etc. are not limited to the above embodiments. Further, the shape of the SiO 2 film processed is not limited to a stripe shape, and Si substrates processed into various shapes can be obtained by processing the SiO 2 film into other shapes.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によればMBE成
長を利用するため、従来のエツチングによるシリ
コン基板の加工技術に比べ、基板表面の汚染やダ
メージ等のないシリコン基板の加工方法が得られ
る。また、MBE成長中に不純物のドーピングを
行なうことも可能であり、形状、不純物濃度の制
御されたSi凸部を有するシリコン基板を得ること
ができる。
As explained above, according to the present invention, since MBE growth is utilized, a method for processing a silicon substrate can be obtained that does not cause contamination or damage to the substrate surface, compared to the conventional silicon substrate processing technology using etching. It is also possible to dope impurities during MBE growth, and it is possible to obtain a silicon substrate having Si convex portions with controlled shapes and impurity concentrations.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の加工工程を示
す断面図、第2図は本発明の第2の実施例の加工
工程を示す断面図である。 10,50……シリコン基板、20,60……
SiO2膜、30,70……溝、40,80……シ
リコンエピタキシヤル成長層。
FIG. 1 is a sectional view showing the processing steps of a first embodiment of the present invention, and FIG. 2 is a sectional view showing the processing steps of the second embodiment of the invention. 10,50...Silicon substrate, 20,60...
SiO 2 film, 30, 70... groove, 40, 80... silicon epitaxial growth layer.

Claims (1)

【特許請求の範囲】 1 シリコン基板表面にSiO2膜を形成し、この
SiO2膜に溝を形成し、SiO2膜がエツチングされ
ると共にシリコン基板表面にエピタキシヤル成長
が起こる基板温度および照射条件で、Si分子線を
少なくともSiO2膜が完全に無くなるまで照射す
ることを特徴とするシリコン基板の加工方法。 2 特許請求の範囲第1項に記載のシリコン基板
の加工方法において、前記溝をシリコン基板表面
が露出するように形成し、前記Si分子線照射によ
りSiO2膜のエツチングおよびエピタキシヤル成
長を同時進行させることを特徴とするシリコン基
板の加工方法。 3 特許請求の範囲第1項に記載のシリコン基板
の加工方法において、前記溝をシリコン基板表面
が露出することなく形成し、前記Si分子線照射に
より、前記溝の底部にシリコン基板表面が露出す
るまでSiO2膜をエツチングした後、SiO2膜のエ
ツチングおよびエピタキシヤル成長を同時進行さ
せることを特徴とするシリコン基板の加工方法。
[Claims] 1. A SiO 2 film is formed on the surface of a silicon substrate, and this
A groove is formed in the SiO 2 film, and the Si molecular beam is irradiated at least until the SiO 2 film is completely removed at a substrate temperature and irradiation conditions that will cause the SiO 2 film to be etched and epitaxial growth to occur on the silicon substrate surface. Characteristic silicon substrate processing method. 2. In the method of processing a silicon substrate according to claim 1, the groove is formed so that the surface of the silicon substrate is exposed, and etching and epitaxial growth of the SiO 2 film are simultaneously progressed by the Si molecular beam irradiation. A method for processing a silicon substrate, characterized by: 3. In the method of processing a silicon substrate according to claim 1, the groove is formed without exposing the silicon substrate surface, and the silicon substrate surface is exposed at the bottom of the groove by the Si molecular beam irradiation. 1. A method of processing a silicon substrate, characterized in that after etching the SiO 2 film up to a maximum of 100 nm, etching and epitaxial growth of the SiO 2 film proceed simultaneously.
JP506786A 1986-01-16 1986-01-16 Processing method for silicon base plate Granted JPS62167289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP506786A JPS62167289A (en) 1986-01-16 1986-01-16 Processing method for silicon base plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP506786A JPS62167289A (en) 1986-01-16 1986-01-16 Processing method for silicon base plate

Publications (2)

Publication Number Publication Date
JPS62167289A JPS62167289A (en) 1987-07-23
JPH0456798B2 true JPH0456798B2 (en) 1992-09-09

Family

ID=11601042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP506786A Granted JPS62167289A (en) 1986-01-16 1986-01-16 Processing method for silicon base plate

Country Status (1)

Country Link
JP (1) JPS62167289A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02214184A (en) * 1989-02-15 1990-08-27 Mitsubishi Electric Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS62167289A (en) 1987-07-23

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