JPH0456342A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize reductions in IC development time and cost by establishing switching circuits which selectively connect a first and a second circuit with input or output circuits and placing this switching circuit nearby the input or output circuits. CONSTITUTION:Switching circuits 501 and input/output circuits 502 are connected to each other. In each of the input/ output circuits 502, the transistors P1, P2, N1, and N2 compose an input buffer and the transistors P3, P4, N3, and N4 compose an output buffer. When signal (e) is at a level H, the transistors P3 and P4 turn on and the output buffer becomes active. As a result, signals transmitted by the switching circuit 501 are output into a pad Pa. When signal (e) is at a level L, the transistors P1 and N2 turn on and the input buffer becomes active. As a result, the signals (g) given to the pad Pa are transmitted as input signals (f) to a microcomputer core 2 and a random logic circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a semiconductor integrated circuit device, and more particularly to a large-scale control integrated circuit using a microcomputer as a core.

[Prior Art] In recent years, as electronic devices have become more sophisticated, smaller, and cheaper, there has been a growing demand for developing LSIs including microcomputers for each application product. Furthermore, it is required to develop such LSIs quickly and reliably.

As a method for developing an integrated circuit (hereinafter referred to as an IC) having a microcomputer as its core, there is an example of a technique shown in FIG. 15. This technology includes a CPU (Central Processing Unit) core 201, a ROM (Read Only Memory) 202, and a RAM (Random Access Memory) 20.
3. 1-chip microcomputer 208 including I/F circuit (interface circuit) 204, timer 205, I10 port (input/output capo) 206, and bus 207
A logic circuit 209 specific to the user's system is incorporated therein, and these are integrated on one chip. 15th
As shown in the figure, logic circuit 209 is connected to bus 207 within microcomputer 208.

Further, as another method for developing an IC using a microcomputer as its core, there is an example of a technique as shown in FIG.

In this technique, a microcomputer chip 301 and a logic circuit chip 302 are placed on a chip 303, and new pads 304 necessary to integrate them into one chip are provided. Wiring is then provided between the pad 305 on the microcomputer chip 301, the pad 306 on the logic circuit 302, and the newly provided pad 304 to integrate them into one chip.

According to these techniques, a general-purpose microcomputer and a user-specific logic circuit are integrated into one chip, making it easy to downsize the system and reduce costs.

[Problems to be Solved by the Invention] However, in the technique shown in FIG. 15, in order to incorporate the logic circuit 209 into the one-chip microcomputer 208, changes and additions to the layout are required, and the microcomputer chip 208 is The entire structure will be remodeled. Therefore, chip development, comprehensive timing verification, test program development, and debugging take time. Additionally, chip development requires engineers who are familiar with everything about microcomputers, including their patterns, circuit configurations, timing, and testing methods.

Furthermore, test programs, software development/debugging tools, etc. that have already been developed for microcomputer chips cannot be used. Therefore, new test programs, software development/debugging tools, etc. must be developed.

On the other hand, in the technique shown in FIG. 16, multiple chips are integrated into one chip by wiring between them, so pads 30 are placed on each chip 301 and 302.
There are 5,306 and 6 circuits 307 and 308. Therefore, pads, driver circuits, etc. are duplicated, resulting in waste and increasing chip size. In addition, it cannot be ignored that the layout pattern of an integrated circuit is becoming less integrated due to an increase in the wiring area. In particular, recently, the number of terminals in integrated circuits has increased, and computers have been used to design layout patterns of integrated circuits, which further increases the wiring area and causes an increase in chip size.

Furthermore, since the microcomputer chip 301 and logic circuit chip 302 cannot be electrically separated, test programs, software development/debugging tools, etc. that have already been developed for microcomputer chips or logic circuit chips are used. Can not do it. Therefore, new test programs, software development/debugging tools, etc. must be developed.

The purpose of this invention is to provide an IC using a microcomputer.
It is an object of the present invention to provide a semiconductor integrated circuit device that can realize the following in a short time with low development effort and cost.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device formed on one chip, comprising first and second circuit means, input or output circuit means, and A switching circuit means is provided. The input or output circuit means includes an external signal pad and inputs or outputs signals to or from the first and second circuit means. Switching circuit means selectively couples the first and second circuit means to the input or output circuit means. The switching circuit means is arranged adjacent to the input or output circuit means.

[Operation] During normal operation, the input or output circuit means is commonly used by the first and second circuit means, and the input or output circuit means is connected to both the first circuit means and/or the second circuit means. or one is combined.

When testing the first circuit means, only the first circuit means is coupled to the input or output circuit means, and a signal for testing is input/output via this input or output circuit means. On the other hand, when testing the second circuit means, only the second circuit means is coupled to the input or output circuit means, and a signal for testing is input/output via this input or output circuit means.

In this way, the first circuit means and the second circuit means can be tested individually, so that test programs and software development/debugging tools that have already been developed for general-purpose microcomputers and logic circuits can be tested. can be used.

Further, since the pad is not included in the first circuit means and the second circuit means, but is included in the input or output circuit means, the chip size is reduced compared to the conventional example. Furthermore, without changing or adding to the layout of one of the first and second circuit means, the other can be designed according to specifications.

Moreover, input or output circuit means for inputting or outputting signals to or from the first and second circuit means;
Since the switching circuit means and the switching circuit means for selectively coupling the second circuit means to the input or output circuit means are arranged adjacent to each other, the degree of integration of the semiconductor integrated circuit device is improved.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a plan view showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. A microcomputer core (or microcontrol unit core; hereinafter referred to as microcomputer core) 2 and a random logic circuit 3 are provided on a semiconductor chip 1 . A common shared terminal circuit 4, a selective shared terminal circuit 5, a dedicated terminal circuit 6 for a microcomputer core, and a dedicated terminal circuit 7 for a random logic circuit are provided on the peripheral portion of the semiconductor chip 1. Further, a mode setting signal generation circuit 8 and a mode signal input circuit 9 are provided on the semiconductor chip 1.

Here, each of the common shared terminal circuit 4, the selected shared terminal circuit 5, and the dedicated terminal circuits 6 and 7 is referred to as a peripheral circuit. The length H of each peripheral circuit in the direction perpendicular to each side of the semiconductor chip 1 is formed to be the same.

Referring to FIG. 1, the peripheral circuit 500a corresponds to the common terminal circuit 4 or the selective common terminal circuit 5, and the peripheral circuit 500a corresponds to the common terminal circuit 4 or the selective common terminal circuit 5.
00b corresponds to the dedicated terminal circuits 6 and 7. Peripheral circuit 50
0a includes a switching circuit 501 and an input/output circuit 502.

The switching circuit 501 and the input/output circuit 502 are arranged adjacent to each other.

Further, peripheral circuit 500b includes a gate circuit 503 and an input/output circuit 502. Gate circuit 503 and input/output circuit 5
It is arranged adjacent to 02.

As shown in FIG. 1, the length H of each peripheral circuit 500a, 500b in the direction perpendicular to each side of the semiconductor chip.
are all formed identically.

FIG. 2A is a diagram showing an example of a layout pattern on a semiconductor chip of the peripheral circuit 500a, and FIG.
FIG. 2 is an equivalent circuit diagram of FIG.

As shown in FIG. 2A, the power supply voltage V. One area corresponds to the switching circuit 501, and the other area corresponds to the input/output circuit 502, sandwiching the power line L1 that supplies power D and the power line L2 that supplies power voltages VS and l. be.

The switching circuit 501 includes an N-channel MOS transistor N5.
．． N6. NIO, N20. N30 and P channel MO
8) Transistor P5. P6. PLO, P20. Contains P2O. Each transistor includes a source S1 gate G and a drain D.

The input/output circuit 502 includes an N-channel MO3) transistor N
l, N2. N3. N4, P channel MOS transistor PL, P2. P3. Includes P4 and pad Pa. Each transistor includes a source S1 gate G and a drain D.

In FIG. 2B, inverter 11 is composed of an N-channel MOS transistor N10 and a P-channel MOS transistor PLO shown in FIG. 2A. In addition, the inverter I2 is an N-channel MO3 shown in FIG. 2A).
It consists of a transistor N20 and a P channel MOS transistor P20, and the inverter 3 is an N channel MOS transistor P20.
It consists of a transistor N30 and a P-channel MO8) transistor P30. Transistor P5. N5 constitutes a first transfer gate, and transistor P6°N6 constitutes a second transfer gate. Signal a is “H”
When the level is high, transistor P5°N5 turns on,
The signal is transmitted to input/output circuit 502. Also, signal C
When transistor P6. is at "H" level, transistor P6. N6 is turned on and signal d is transmitted to input/output circuit 502.

In the input/output circuit 502, transistors P1, P2.
Nl and N2 constitute an input buffer, and transistor P3
．． P4. N3. N4 constitutes the output buffer. signal e
When transistor P3. is at "H" level, transistor P3. N4 is turned on and the output buffer is enabled. Thereby, the signal transmitted from switching circuit 501 is output to pad Pa. When the signal e is at "L" level, the transistor P1
, N2 are turned on and the input buffer is enabled.

As a result, the signal g applied to the pad Pa is input to the microcomputer core 2 or the random logic circuit 3 as the input signal f.
transmitted to.

FIG. 3A is a diagram showing an example of a layout pattern on a semiconductor chip of the peripheral circuit 500b, and FIG.
FIG. 2 is an equivalent circuit diagram of FIG.

As shown in FIG. 3A, one region across the power lines LL and L2 corresponds to the input/output circuit 502,
The other region is a portion corresponding to gate circuit 503.

The layout pattern of input/output circuit 502 is similar to the layout pattern of input/output circuit 502 shown in FIG. 2A. Gate circuit 503 includes N-channel MO3) transistors NIQ and N40 and P-channel MOS transistors PLO and P2O. Each transistor has a source S
1 gate G and drain D.

As shown in FIG. 3B, gate circuit 503 includes inverter 11 and I4. Inverter 11 consists of an N-channel MOS transistor NIO and a P-channel MOS transistor PIO shown in FIG. 3A. Inverter I4 consists of an N-channel MOS transistor N40 and a P-channel MO3) transistor P40.

The signal is transmitted to the transistor P4 of the input/output circuit 502 via the inverter 4. Given to the gate of N3. When signal e is at "H" level, transistor P3. N4 is turned on and the output buffer is enabled. Therefore, a signal is output to pad Pa. When the signal e is at ``L'' level, transistors PL and N2 are turned on. Therefore, the signal g applied to the pad Pa is input to the microcomputer core 2 or the random logic circuit 3 as the input signal f.

In the above embodiment, since the switching circuit 501 and the input/output circuit 502 are arranged adjacent to each other on the layout pattern of the semiconductor chip, the wiring area between the switching circuit 501 and the input/output circuit 502 covers the entire semiconductor integrated circuit. It is almost negligible for the area.

Furthermore, the switching circuit 501 and the input/output circuit 502 are separated by power lines LL and L2. Similarly, the gate circuit 503 and the input/output circuit 502 are separated by power lines Ll and L2. Therefore, external noise that has entered pad Pa via the input/output terminal is prevented from entering switching circuit 501 and gate circuit 503. Note that the power supply line Ll is formed of aluminum wiring.

If a contact is provided between the lower part of L2 and the semiconductor substrate, or if a diode with a reverse breakdown voltage is placed between them, external noise will be more effectively removed.

According to the layout pattern design using a computer, the wiring area between the microcomputer core 2 or the random logic circuit 3 and the peripheral circuits 500a and 500b is
00a and 500b. Therefore,
Each peripheral circuit 500a in a direction perpendicular to each side of the semiconductor chip.

When the lengths of the wires 500b are different from each other, each wire is formed to be bent. In the above embodiment, each peripheral circuit 5 in the direction perpendicular to one side of the semiconductor chip
Since the lengths H of 00a and 500b are unified, the layout pattern of each wiring is simplified and the area of the wiring region is reduced.

Next, the configuration and operation of each part of the semiconductor integrated circuit device of the above embodiment will be explained in detail.

As shown in FIG. 5, the microcomputer core 2 is a CPU core 2
1, ROM 22, RAM 23, I/F circuit 24, timer 25, I10 port 26, and bus 27, but does not include input/output circuits such as input/output drivers and pads.

The random logic circuit 3 includes various gates, counters,
A logic circuit consisting of flip-flops, etc.
Designed according to specific application specifications.

Next, referring to FIG. 6, the common terminal circuit 4 is normally coupled to the microcomputer core 2 and the random logic circuit 3, and is selectively coupled to the microcomputer core 2 or the random logic circuit 3 during testing. The selective common terminal circuit 5 is normally fixedly coupled to either the microcomputer core 2 or the random logic circuit 3, and is selectively coupled to the microcomputer core 2 or the random logic circuit 3 during testing. The dedicated terminal circuit 6 is fixedly coupled only to the microcomputer core 2, and the dedicated terminal circuit 7 is fixedly coupled only to the random logic circuit 3.

The mode signal input circuit 9 is configured to operate the semiconductor integrated circuit device in a normal mode and a test mode of the microcomputer core 2 (hereinafter referred to as M
A mode signal for setting the random logic circuit 3 to a test mode (hereinafter referred to as an R/L test mode) is provided. In response to the output of the mode signal input circuit 9, the mode setting signal generation circuit 8 outputs the common terminal circuit 4 and the selected common terminal circuit 5.
Give a mode setting signal to.

FIG. 7 is a block diagram showing the configurations of the common shared terminal circuit 4 and the selected shared terminal circuit 5. As shown in FIG. Common shared terminal circuit 4
consists of a switching circuit 41 and an input/output circuit 42, and the selection common terminal circuit 5 similarly consists of a switching circuit 51 and an input/output circuit 52. The switching circuit 41 is connected to the microcomputer core 2 by a signal line LM and to the random logic circuit 3 by a signal line LR. Similarly, the switching circuit 51 is connected to the microcomputer core 2 by a signal line LM and to the random logic circuit 3 by a signal line LR. Furthermore, a mode setting signal is applied to the switching circuit 41 and the switching circuit 51 from the mode setting signal generation circuit 8 via the signal line LC.

FIGS. 8A, 8B, and 8C are schematic diagrams for explaining the functions of the common terminal circuit 4. FIG.

In the normal mode, the input/output circuit 42 is coupled to the microcomputer core 2 and the random logic circuit 3 by the switching circuit 41, as shown in FIG. 8A.

In the MCU test mode, as shown in FIG. 8B, the input/output circuit 42 is switched to the microcomputer core 2 by the switching circuit 41.
is combined with In R/L test mode, the 8th C
As shown in the figure, an input/output circuit 42 is coupled to the random logic circuit 3 by a switching circuit 41.

FIG. 9 is a schematic diagram for explaining the function of the selection common terminal circuit 5. In the normal mode, as shown in FIG. 9, the input/output circuit 52 is fixedly coupled to either the microcomputer core 2 or the random logic circuit 3 by the changeover switch 51.

Which of the microcomputer core 2 and the random logic circuit 3 it is coupled to is determined by the specifications of the semiconductor integrated circuit device.

In the MCU test mode, as in the case of the common terminal circuit 4, the input/output circuit 52 is coupled to the microcomputer core 2 by the switching circuit 51. Also in the R/L test mode, the input/output circuit 52 is coupled to the random logic circuit 3 by the switching circuit 51, as in the case of the common terminal circuit 4.

FIG. 10 is a diagram showing the configuration of mode setting signal generation circuit 8 and mode signal input circuit 9. The mode signal input circuit 9 includes pads 91.92 and input buffers 93.94.
including. Mode setting signal generating circuit 8 is supplied with mode signal φ0 via pad 91 and input buffer 93, and is supplied with mode signal φ1 via pad 92 and input buffer 94. The mode setting signal generation circuit 8 generates a mode signal φ0. Mode setting signal TN based on φ1
, TM, and TR are generated. The mode setting signal TN is active in the normal mode, the mode setting signal TM is active in the MCU test mode, and the mode setting signal TR is active in the R/L test mode.

FIG. 11 is a diagram showing the configuration of the signal lines in detail.

The signal line LM consists of a data line for transmitting output data DOM, a data line for transmitting input data DIM, and a control line for transmitting control signal CM. This signal line LM is connected to the I10 port 26 (fifth
(see figure).

The signal line LR includes a data line for transmitting output data DOR, a data line for transmitting input data DIR, and a control line for transmitting control signal CR. Further, the signal line LC includes three signal lines for transmitting mode setting signals TN, TM, and TR.

FIG. 12 is a diagram showing the configuration of the common shared terminal circuit 4.

Output circuit 42 includes a pad 43 and an output driver 44.

In the normal mode, the mode setting signal TN becomes active. Thereby, the switching circuit 41 controls the control signals CM, C
A signal resulting from the logical sum of one or both of R and one of the output data DOM and DOR is provided to the output driver 44. Output driver 44 outputs output data to pad 43 in response to the control signal.

In the MCUC test mode, the mode setting signal TM becomes active. Thereby, the switching circuit 41 receives the control signal C.
M and output data DOM are provided to the output driver 44. Output driver 44 outputs output data DOM to pad 43 in response to control signal CM.

In the R/L test mode, the mode setting signal TR becomes active. Thereby, the switching circuit 41 provides the control signal CR and output data DOR to the output driver 44. Output driver 44 outputs output data DOR to pad 43 in response to control signal CR.

Furthermore, input data DIM is input from the pad 43 to the microcomputer core 2, and input data DIR is input from the pad 43 to the random logic circuit 3.

The configuration of the selection common terminal circuit 5 is also similar to the configuration shown in FIG. However, in the selection common terminal circuit 5,
Output data D in normal mode.

Predetermined output data of M and DOR is always output.

FIG. 13 is a diagram showing the configuration of the dedicated terminal circuit 6. Dedicated terminal circuit 6 includes a pad 61 and an output driver 62. The output driver 62 is provided with a control signal CM and output data DOM. Input data DIM is also input from the pad 61 .

The configuration of the dedicated terminal circuit 7 is also similar to the configuration of the dedicated terminal circuit 6.

Next, the operation of the semiconductor integrated circuit device of this embodiment will be explained.

In the normal mode, the common terminal circuit 4 is commonly used by the microcomputer core 2 and the random logic circuit 3, and the output of the microcomputer core 2 (or random logic circuit 3) is connected to the random logic circuit 3 (or the microcomputer core 2).
), or the signal is input to the microcomputer core 2 and the random logic circuit 3 via the common terminal circuit 4. Further, signals are input/output to/from the microcomputer core 2 via the dedicated terminal circuit 6, and signals are input/output to/from the random logic circuit 3 via the dedicated terminal circuit 7. When the selective common terminal circuit 5 is coupled to the microcomputer core 2, signals are input to and output from the microcomputer core 2 via the selective common terminal circuit 5. Conversely, when the selective common terminal circuit 5 is coupled to the random logic circuit 3, signals are inputted to and output from the random logic circuit 3 via the selective common terminal circuit 5.

In the MCUC test mode, the common shared terminal circuit 4 and the selected shared terminal circuit 5 are coupled only to the microcomputer core 2. In this case, the common shared terminal circuit 4, the selected shared terminal circuit 5
Alternatively, a test signal is input/output to/from the microcomputer core 2 via the dedicated terminal circuit 6.

In the R/L test mode, the common shared terminal circuit 4 and the selected shared terminal circuit 5 are coupled only to the random logic circuit 3. In this case, a test signal is input/output to/from the random logic circuit 3 via the common terminal circuit 4, the selective common terminal circuit 5, or the dedicated terminal circuit 7.

As mentioned above, each of the microcomputer core 2 and random logic circuit 3 can be tested individually, so test programs and software development/debugging tools that have already been developed for general-purpose microcomputers and logic circuits can be used. can be used.

Further, since the pads and drivers are not included in the microcomputer core 2 and the random logic circuit 8, but are included in the common shared terminal circuit 4 and the selected shared terminal circuit 5, the chip size is reduced.

Furthermore, the configuration of the random logic circuit 3 can be designed according to specifications without changing or adding to the layout of the microcomputer core 2.

Next, an example of use of the semiconductor integrated circuit device of this embodiment will be explained with reference to FIG.

Normally, arithmetic processing is performed in the microcomputer core 2,
The random logic circuit 3 performs high-speed processing that cannot be processed by the microcomputer core 2.

For example, if the random logic circuit 3 is designed to be a general-purpose controller, the dedicated terminal circuit 7
A plurality of nocusonal computers 101, disk devices 106, etc. are connected to the computer via a bus 100.

Furthermore, the random logic circuit 3 is configured to control a specific control target 102.
If it is designed to be a dedicated controller for
A controlled object 102 is connected to the dedicated terminal circuit 7 .

For example, an external memory 103 is connected to the common terminal circuit 4. For example, the selection common terminal circuit 5 includes a CPU 10.
4 is connected to the dedicated terminal circuit 6, and a disk controller 105, for example, is connected to the dedicated terminal circuit 6. The selective common terminal circuit 5 can also be coupled to the random logic circuit 3 according to the user's order.

As described above, according to this embodiment, an IC using a microcomputer core can be realized at low cost and in a short period of time with little development effort.

[Effects of the Invention] As described above, according to the present invention, test programs and software development/debugging tools that have already been developed for the first circuit means or the second circuit means can be used. At the same time, the chip size is reduced. Furthermore, even if one is not familiar with the pattern, circuit configuration, timing, testing method, etc. of one of the first and second circuit means, the other can be easily designed in accordance with the user's requirements.

In turn, it becomes possible to realize an IC using a microcomputer core in a short period of time and with less development effort and cost.

Furthermore, since the input or output circuit means and the switching circuit means are arranged adjacent to each other, the degree of integration is further improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the main parts of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2A is a diagram showing an example of the layout pattern of the peripheral circuit of the same embodiment. 2nd B
The figure is an equivalent circuit diagram of FIG. 2A. FIG. 3A is a diagram showing an example of a layout pattern of another peripheral circuit of the same embodiment. FIG. 3B is an equivalent circuit diagram of FIG. 3A. 4th floor
! ! J is a plan view of the entire semiconductor integrated circuit device according to the same embodiment. FIG. 5 is a functional block diagram showing the configuration of the same embodiment. FIG. 6 is a schematic diagram for explaining the features of the main parts of the embodiment. FIG. 7 is a block diagram showing the configuration of the common shared terminal circuit and the selected shared terminal circuit. 8A, 5, 8B and 8C are schematic diagrams for explaining the functions of the common shared terminal circuit, FIG. 8A is a diagram showing the normal mode, FIG. 8B is a diagram showing the MCU test mode, FIG. 8C is a diagram showing the R/L test mode. FIG. 9 is a schematic diagram for explaining the function of the selective common terminal circuit. FIG. 10 is a diagram showing the configuration of a mode setting signal generation circuit and a mode signal input circuit. FIG. 11 is a diagram showing a specific configuration of signal lines. FIG. 12 is a diagram showing the configuration of the common shared terminal circuit. FIG. 13 is a diagram showing the configuration of the dedicated terminal circuit. FIG. 14 is a diagram for explaining an example of use of the embodiment. 15th
The figure is a plan view showing an example of an IC using a conventional microcomputer core. Figure 16 shows an I
FIG. 3 is a functional block diagram showing another example of C. In the figure, 1 is a semiconductor chip, 2 is a microcomputer core, 3 is a random logic circuit, 4 is a common shared terminal circuit, 5 is a selection shared terminal circuit, 6.7 is a dedicated terminal circuit, 8 is a mode setting signal generation circuit, 9 is a mode signal input circuit, 500a and 500b are peripheral circuits, 501 is a switching circuit, 502 is an input/output circuit, and Pa is a pad. Note that the same reference numerals in each figure indicate the same or corresponding parts. (Other 2 people) 1'''' Pa 0 Figure 2B Figure 3B 5 o 2: Input/output circuit Figure 5 辅 4 Figure 8: Mo, -do S Moxibustion Hiro A 2-to-5 man power station Figure 6 Figure 7 Figure 10 Figure 8 Δ Figure 8B Figure 8C Figure 14

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device formed on a chip, comprising: first and second circuit means; and an external signal pad; input or output circuit means for inputting or outputting the input or output, and switching circuit means for selectively coupling the first and second circuit means to the input or output circuit means, A semiconductor integrated circuit device disposed adjacent to output circuit means.