JPH07142583A - Semiconductor integrated circuit and layout method thereof - Google Patents

Semiconductor integrated circuit and layout method thereof

Info

Publication number
JPH07142583A
JPH07142583A JP28718293A JP28718293A JPH07142583A JP H07142583 A JPH07142583 A JP H07142583A JP 28718293 A JP28718293 A JP 28718293A JP 28718293 A JP28718293 A JP 28718293A JP H07142583 A JPH07142583 A JP H07142583A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
line
power supply
region
circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP28718293A
Other languages
Japanese (ja)
Inventor
Mitsuru Onodera
充 小野寺
Original Assignee
Fujitsu Ltd
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To improve the stability of operation, to improve circuit density, to enhance the flexibility of design and to make it possible to perform the free design of a power supply suitable for respective circuit parts by laying power supply lines exclusive for a region along the peripheral line or a line in parallel with the peripheral line in the region, wherein a logic part or a macro-part is formed.
CONSTITUTION: Four regions are secured in the element-forming-type cell array part (SOG part) at the entire surface of a semiconductor chip 11. First - fourth circuit parts 15-18 are formed in these regions. A pair of power supply lines 15b and 15c are laid in parallel with a peripheral line 15a of the first circuit part 15. Furthermore, a pair of power supply lines 16b and 16c are laid in parallel with a peripheral line 16a of the second circuit part 16. A pair of power supply lines 17b and 17c are laid in parallel with a peripheral line 17a of the third circuit part 17. Furthermore, a pair of power supply lines 18b and 18c are laid in parallel with a peripheral line 18a of the fourth circuit part 18. Therefore, the unnecessary power supply lines do not cross each circuit part, the effect of power supply noises is hard to receive and the using efficiency of the SOG part can be improved.
COPYRIGHT: (C)1995,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、全面素子形成型セルアレイ(SOG:Sea Of Gate)を利用して作られるセミカスタムの半導体集積回路及びそのレイアウト方法に関し、特に、多電源で動作する半導体集積回路及びそのレイアウト方法に関する。 BACKGROUND OF THE INVENTION This invention is entirely element forming cell array: relates to a semiconductor integrated circuit and a layout method of the semi-custom made by using (SOG Sea Of Gate), in particular, a semiconductor integrated operating at multiple power supply circuit and its layout method. 全面素子形成型セルアレイは、 Entire element formation type cell array,
半導体基板に配線を含まない基本構造のみのトランジスタを多数作り込んだもの(通称「ベーシックセル」) Those yelling to make a large number of transistors of only the basic structure that does not include the wiring in a semiconductor substrate (called "basic cell")
で、自在な配線設計によって、任意のロジック部やマクロ部を作ることができ、少量多品種の半導体集積回路に多用されている。 In, the universal wiring design, can make any logic section and the macro section, it is widely used in the semiconductor integrated circuit of the high-mix low-volume.

【0002】 [0002]

【従来の技術】図7はベーシックセルの概略平面図である。 BACKGROUND ART FIG. 7 is a schematic plan view of a basic cell. この図において、1は半導体チップ、2は全面素子形成型セルアレイ部(以下「SOG部」)であり、SO In this figure, 1 is a semiconductor chip, 2 is the entire element formation cell array section (hereinafter "SOG unit"), SO
G部2を含むチップ全面には、数種類(ここでは2種類)のメッシュ状の電源線3、4がレイアウトされている。 The entire surface of the chip containing the G unit 2, meshed power lines 3 and 4 of the several (two in this case) has been laid. なお、一点鎖線で示す電源線3は例えば+5V系、 The power supply line 3 shown by a dashed line, for example + 5V system,
破線で示す電源線4は例えば+3V系である。 Power line 4 indicated by a broken line, for example + 3V system.

【0003】図8は図7のベーシックセルを利用して、 [0003] FIG. 8 by using the basic cell of FIG. 7,
異なる電源で動作する複数個(ここでは2個)の回路部(第1及び第2の回路部5、6)をレイアウトした例である。 It is an example of layout circuit section (first and second circuit portions 5, 6) of the plurality of operating at different supply (two here). これらの回路部5、6は、フルカスタム設計されたロジックであってもよいし、ライブライリ資産であるマクロであってもよい。 These circuits 5 and 6 may be a full custom designed logic, may be macro is Raiburairi assets. ここで、第1の回路部5の動作電圧を+5V、第2の回路部6の動作電圧を+3Vとすると、これらの回路部5、6には、同一系統の電源線3、4を介して電源電圧(+5V又は+3V)が供給される。 Here, the operation voltage of the first circuit portion 5 + 5V, when the operating voltage of + 3V to the second circuit portion 6, these circuits 5 and 6, through the power lines 3 and 4 of the same system supply voltage (+ 5V or + 3V) is supplied.

【0004】すなわち、第1の回路部5には、一点鎖線で示す電源線3を介して+5Vが供給され、また、第2 [0004] That is, the first circuit part 5, through the power supply line 3 shown by a dashed line + 5V is supplied, and the second
の回路部6には、破線で示す電源線4を介して+3Vが供給される。 The circuit portion 6, via a power supply line 4 shown by broken lines + 3V is supplied.

【0005】 [0005]

【発明が解決しようとする課題】しかしながら、かかる従来の半導体集積回路及びそのレイアウト方法にあっては、メッシュ状の電源線3、4をレイアウトした後に、 [SUMMARY OF THE INVENTION However, in the such a conventional semiconductor integrated circuit and a layout method, after laying out meshed power lines 3 and 4,
第1及び第2の回路部5、6の領域を確保する構成となっていたため、+5V系の第1の回路部5の領域内を+ Because it is configured to secure an area of ​​the first and second circuit portions 5 and 6, the first circuit portion 5 of the + 5V system the region +
3V系の電源線4が横切り、また、+3V系の第2の回路部6の領域内を+5V系の電源線3が横切ることとなり、異系の電源線からの誘導雑音によって、それぞれの回路部が誤動作しやすくなるという問題点があった。 3V system power supply line 4 crosses the, also, + 3V type second circuit portion will be 6 region of + 5V system power supply line 3 of the crossing of the induction noise from the power supply line of allogeneic, each circuit portion but there is a problem that is likely to malfunction.

【0006】また、第1及び第2の回路部5、6の領域の一部が不要な電源線に占有されるから、領域の使用効率が悪く、集積度の向上を阻害するという問題点もある。 Further, since part of the area of ​​the first and second circuit portions 5 and 6 are occupied by unnecessary power supply line, poor utilization of space, the problem that inhibits the increased density is there. さらに、メッシュ状の電源線3、4の電流容量があらかじめ決まっているため、それぞれの回路部5、6に適合した柔軟な電源設計を行えないという問題点もある。 Furthermore, there is a current capacity of the mesh-like power supply lines 3 and 4 is determined in advance, a problem that can not be performed, power, flexible design adapted to the respective circuits 5 and 6. [目的]そこで、本発明は、電源雑音の影響を受け難くして動作安定性の向上を図ること、SOG部の使用効率を改善して集積度の向上を図ること、及び、設計の柔軟性を高めてそれぞれの回路部に適合した自在な電源設計を可能にすることを目的とする。 [Object] The present invention is possible to improve the operational stability and difficult to receive an influence of power supply noise, possible to improve the degree of integration by improving the use efficiency of the SOG portions, and design flexibility and an object thereof is to enable a universal power supply design adapted to the respective circuit portions to enhance.

【0007】 [0007]

【課題を解決するための手段】本発明の半導体集積回路は、全面素子形成型セルアレイ上に確保した任意の大きさの領域内に任意のロジック部又はマクロ部を形成する半導体集積回路において、前記領域の外縁線又は外縁線と平行する線に沿って、その領域専用の電源線を敷設したことを特徴とする。 The semiconductor integrated circuit of the present invention According to an aspect of the semiconductor integrated circuit to form an arbitrary logic unit or macro section in the region of an arbitrary size which is secured on the entire surface element forming cell array on the along a line parallel to the outer line or edge line region, characterized in that laying the power line of the region only.

【0008】本発明の半導体集積回路のレイアウト方法は、外周電源線を含むI/O領域及び該I/O領域に囲まれた全面素子形成型セルアレイを有するベーシックセルを用意し、該全面素子形成型セルアレイ上に任意の大きさの領域を確保し、該領域の外縁線又は外縁線と平行する線に沿って電源線を敷設し、該電源線と前記外周電源線との間を接続するとともに、該電源線と前記領域の内部電源線との間を接続することを特徴とする。 [0008] The layout method of a semiconductor integrated circuit of the present invention is to provide a basic cell having the entire element formation type cell array enclosed in the I / O region and the I / O region including the outer peripheral power line, 該全 surface elements formed together to secure the area of ​​arbitrary size on the mold array, laying power line along a line parallel to the outer line or edge line of the region, which connects the outer peripheral power supply line and said power line characterized by connecting the internal power supply line of the with the power line region.

【0009】又は、前記半導体集積回路若しくは前記半導体集積回路のレイアウト方法において、前記領域の外縁線又は外縁線と平行する線に沿って敷設される電源線は、有端線であることを特徴とする。 [0009] or, in the layout method of the semiconductor integrated circuit or the semiconductor integrated circuit, a power supply line that is laid along a line parallel to the outer line or edge line of the region, and characterized by a closed end line to. 又は、前記半導体集積回路若しくは前記半導体集積回路のレイアウト方法において、前記領域は、少なくともその領域の外縁線の一部と外周電源線との間に他の領域が介在しないようにレイアウトされていることを特徴とする。 Or, in the layout method of the semiconductor integrated circuit or the semiconductor integrated circuit, the region, at least the other areas between the part and the peripheral power supply line of the outer edge line of the region is laid out so as not intervene the features.

【0010】 [0010]

【作用】本発明では、全面素子形成型セルアレイ(SO According to the present invention, the entire surface element forming cell array (SO
G部)上の任意のロジック部又はマクロ部の周囲に電源線が敷設され、その電源線を介してロジック部又はマクロ部に所要の電源電圧が供給される。 G section) on any logic unit or power supply line is laid around the macro section, the required supply voltage to the logic unit or the macro section through the power line is supplied. したがって、ロジック部又はマクロ部を異系の電源線が横切らないので、 Therefore, since no cross power line allogeneic logic unit or macro section,
電源雑音の影響を受け難くして動作安定性の向上を図ることができ、また、SOG部の使用効率を改善して集積度の向上を図ることができ、さらに、設計の柔軟性を高めてそれぞれの回路部に適合した自在な電源設計を可能にすることができる。 Was hardly affected by power supply noise to be able to improve the operational stability, also to improve the use efficiency of the SOG portions can be improved degree of integration, further increasing the flexibility of design it can allow a universal power supply design adapted to the respective circuit portion.

【0011】 [0011]

【実施例】以下、本発明の実施例を図面に基づいて説明する。 BRIEF DESCRIPTION OF THE PREFERRED embodiment of the present invention with reference to the drawings. 図1〜図6は本発明に係る半導体集積回路の一実施例を示す図である。 1 to 6 are views showing an embodiment of a semiconductor integrated circuit according to the present invention. 図1において、11は半導体チップであり、半導体チップ11の周縁部のI/O領域には、図示を略したI/Oバッファや電源端子及び信号端子とともに、+5V用の外周電源線12、+3V用の外周電源線13、及び、グランド用の外周電源線14が敷設されている。 1, 11 is a semiconductor chip, the I / O region at the peripheral edge of the semiconductor chip 11, along with the I / O buffer and the power supply terminal short for illustration and signal terminals, the outer peripheral power supply line 12 for + 5V, + 3V outer peripheral power supply line 13 of the use, and the outer peripheral power supply line 14 is laid in the ground.

【0012】半導体チップ11の内部領域…I/O領域に囲まれた領域で全面素子形成型セルアレイ部(SOG [0012] entire element formation cell array section within a region ... surrounded by the I / O area region of the semiconductor chip 11 (SOG
部)の領域…には4つの領域が確保されており、それぞれの領域には第1〜第4の回路部15〜18が形成されている。 Area parts) ... in are secured four regions, and each region is the first to fourth circuit portion 15 to 18 is formed. これらの回路部15〜18は、あらかじめ設計されたRAM又はMPU等のライブラリ資産(マクロ) These circuit portions 15 to 18, pre-designed RAM or library assets such as an MPU (macro)
やフルカスタム設計されたロジック部であり、動作電源電圧は、例えば、第1の回路部15と第3の回路部17 And a full custom designed logic unit, operating supply voltage, for example, a first circuit portion 15 the third circuit section 17
が+5V、第2の回路部16と第4の回路部18が+3 There + 5V, and the second circuit portion 16 fourth circuit portion 18 is +3
Vである。 A V.

【0013】それぞれの回路部15〜18は、全面素子形成型セルアレイ上に確保された任意形状(ここでは矩形状)の領域内に形成されており、各領域の外縁線15 [0013] Each of the circuit portions 15 to 18, (in this case rectangular) arbitrary shape secured to the entire element formation cell array on which is formed in the region of the outer edge lines of each region 15
a〜18aと平行する線(仮想の線)に沿って、その領域専用の電源線15b、15c、16b、16c、17 Along a line (imaginary line) in parallel with A~18a, power line 15b in the region only, 15c, 16b, 16c, 17
b、17c、18b及び18cが敷設されている。 b, 17c, 18b and 18c are laid. すなわち、第1の回路部15の外縁線15aと平行して一対の電源線15b、15cが敷設され、第2の回路部16 That is, the first circuit portion 15 in parallel with the outer edge line 15a a pair of power supply lines 15b of, 15c are laid, the second circuit portion 16
の外縁線16aと平行して一対の電源線16b、16c A pair of power supply line 16b in parallel to the outer edge lines 16a, 16c
が敷設され、第3の回路部17の外縁線17aと平行して一対の電源線17b、17cが敷設され、第4の回路部18の外縁線18aと平行して一対の電源線18b、 There is laid, the third edge line 17a parallel to the pair of power supply line 17b of the circuit portion 17, 17c is laid, the fourth in parallel with the outer edge line 18a a pair of power supply line 18b of the circuit portion 18,
18cが敷設されている。 18c is laid.

【0014】そして、図では省略しているが、各一対の電源線の一方が+5V又は+3Vの外周電源線12、1 [0014] Then, although not shown in the figure, the outer peripheral power supply line of one is + 5V or + 3V of each pair of power line 12,1
3の何れかに接続され、且つ、各一対の電源線の他方がグランド用の外周電源線14に接続されている。 It is connected to one of 3, and the other of each pair of power lines are connected to the outer peripheral power supply line 14 for grounding. 例えば、第1の回路部15と第3の回路部17の各一方の電源線15b、17bが+5V用の外周電源線12に接続され、第2の回路部16と第4の回路部18の各一方の電源線16b、18bが+3V用の外周電源線13に接続され、さらに、全部の回路部15〜18の各他方の電源線15c、16c、17c及び18cがグランド用の外周電源線14に接続されている。 For example, each one of the power supply line 15b of the first circuit portion 15 the third circuit portion 17, 17b is connected to the outer peripheral power supply line 12 for + 5V, and the second circuit portion 16 of the fourth circuit portion 18 each one of the power supply line 16b, 18b are connected to the outer peripheral power supply line 13 for + 3V, further each other power line 15c of all the circuit portions 15 to 18, 16c, 17c and 18c outer peripheral power supply line for ground 14 It is connected to the.

【0015】以上の構成によれば、それぞれの回路部1 According to the above configuration, each of the circuit portions 1
5〜18を取り囲んで、各回路部に専用の電源線(例えば第1の回路部にあっては電源線15b、15c)が敷設される。 Surrounds 5 to 18, dedicated power line to each circuit unit (for example, the first power supply line 15b In the circuit portion, 15c) is laid. したがって、各回路部を不要な電源線(異系の電源線)が横切らないから、電源雑音の影響を受け難くして動作安定性の向上を図ることができる。 Accordingly, since each circuit portion unnecessary power line (allogeneic power line) does not cross, it is possible to improve the operational stability and difficult to receive an influence of power supply noise. また、各回路部に不要な電源線を敷設しないから、SOG部の使用効率を改善して集積度の向上を図ることができる。 Also, since not route an unnecessary power supply line to each circuit section, it is possible to increase the degree of integration by improving the use efficiency of the SOG portions. さらに、各電源線の線幅等を自在に設計できるから、設計の柔軟性を高めてそれぞれの回路部に適合した自在な電源設計を可能にすることができる。 Further, since the line width of each power supply line can be freely designed, it is possible to allow a universal power supply design adapted to the respective circuit portions to enhance the design flexibility.

【0016】図2〜図5は本実施例の概略レイアウト工程図である。 [0016] Figure 2-5 is a schematic layout process diagram of the present embodiment. (1)まず、SOGのベーシックセルを用意する。 (1) First, a basic cell of the SOG. 図2 Figure 2
はベーシックセルの概略平面図であり、21は半導体基板、22はI/O領域に形成された+5V用の外周電源線、23は同じくI/O領域に形成された+3V用の外周電源線である。 Is a schematic plan view of a basic cell, 21 denotes a semiconductor substrate, 22 an outer peripheral power supply line for + 5V formed in the I / O region, 23 also at the outer peripheral supply line for + 3V formed in the I / O region is there. なお、グランド用の外周電源線は省略してある。 Incidentally, the outer peripheral power supply line for ground is omitted. 24はSOG部である。 24 is a SOG part. (2)次いで、ベーシックセルのSOG部24内に任意のロジック部又はマクロ部の領域を確保する。 (2) Then, to secure the area of ​​any logic unit or macro portion SOG portion 24 of the basic cell. 図3は便宜的に3つの領域26〜27を確保した例を示している。 Figure 3 shows an example of securing a conveniently three regions 26-27. ここで、第1の領域25は+3V動作のロジック部の形成領域、第2の領域26は+3V動作のマクロ部の形成領域、第3の領域27は+5V動作のロジック部の形成領域である。 Here, formation region of the first region 25 is the logic portion of the + 3V operation, the second region 26 is + 3V operation of macro portion forming region, the third region 27 is forming region of the logic portion of the + 5V operation. (3)次に、図4に示すように、各領域25〜27の周囲に電源線25a〜27aを敷設する。 (3) Next, as shown in FIG. 4, laying the power line 25a~27a around each region 25-27. なお、グランド用の電源線は省略してある。 In addition, the power supply line for the ground is omitted. (4)最後に、同一系の電源線25a〜27aと外周電源線22、23との間を接続する。 (4) Finally, a connection between the power supply line 25a~27a and the outer power supply line 22 and 23 of the same system. 例えば、図5に示すように、第1及び第2の領域25、26の各電源線25 For example, as shown in FIG. 5, each power line of the first and second regions 25, 26 25
a、26aと+3V用の外周電源線23との間を接続(符号A、B参照)するとともに、第3の領域27の電源線27aと+5V用の外周電源線22との間を接続(符号C参照)する。 a, connects the outer peripheral power supply line 23 for 26a and + 3V (code A, B refer) as well as the connection between the outer power supply line 22 of the power supply line 27a and the + 5V of the third region 27 (code C reference) to.

【0017】このようなレイアウト方法によれば、第1 [0017] According to such a layout method, the first
〜第3の領域25〜27に形成されるロジック部やマクロ部に対して、専用の電源線25a〜27aを敷設することができ、それぞれの領域を横切る異系の電源線をなくすことができる。 It can be relative to the logic section and the macro section to be formed through the third region 25 to 27, a dedicated power line 25a~27a can laying, eliminating the power supply line of allogeneic across the respective region . したがって、動作安定性や集積度の向上を図ることができるとともに、それぞれの回路部に適合した自在な電源設計を可能にすることができる。 Therefore, it is possible to allow the operation it is possible to improve the stability and degree of integration, the universal power supply design adapted to the respective circuit portion.

【0018】なお、上記実施例では、ロジック部やマクロ部の周囲に閉鎖ループ状の無端の信号線を敷設しているが、これに限るものではなく、ループの一部が開放した有端の信号線であっても構わない。 [0018] In the above embodiment, although laying a signal line of the closed loop-shaped endless around the logic section and the macro section, not limited to this, chromatic end of the part of the loop is open it may be a signal line. また、ロジック部やマクロ部の領域は、少なくともその領域の外縁線の一部と外周電源線との間に他の領域が介在しないようにレイアウトすることが好ましい。 The area of ​​the logic portion and the macro section preferably other areas between the part and the peripheral power supply line of at least the outer edge line of the region is laid out so as not intervene. 例えば、図6に示すように、4つの領域31〜34をレイアウトする場合には、 For example, as shown in FIG. 6, when laying out the four regions 31 to 34,
すべての領域31〜34について少なくともその外縁線の一部(矩形領域であれば少なくとも1辺)が外周電源線35〜37と直に対向するようにレイアウトする。 For all the regions 31 to 34 at least a portion of the outer edge line (if the rectangular area at least one side) is laid out to directly face the outer peripheral power supply line 35-37. これは、各領域の少なくとも1辺と外周電源線との間には、他の領域が介在しないことを意味する。 This is between the at least one side and the outer power supply line of each region, which means that other regions is not interposed. このようにすれば、各領域31〜34の周囲に敷設した電源線31 In this way, the power supply line laid around each region 31 to 34 31
a、31b、32a、32b、33a、33b、34a a, 31b, 32a, 32b, 33a, 33b, 34a
及び34bと外周電源線35〜37との間の接続を最短経路で行うことができるから好ましい。 And preferred because the connection between 34b and the outer power supply line 35 to 37 can be carried out in the shortest route.

【0019】なお、上記実施例では、+5Vと+3Vの2電源を例としているが、これに限るものではなく、別の電源電圧であってもよいし、又は、3種類以上の多電源であってもよい。 [0019] In the above embodiment, + 5V and + 3V for although the two power supply embodiment, the present invention is not limited thereto, may be a separate supply voltage, or a three or more multi-power it may be.

【0020】 [0020]

【発明の効果】本発明によれば、全面素子形成型セルアレイ(SOG)上に確保した任意の大きさの領域の外縁線又は外縁線と平行する線に沿って、その領域専用の電源線を敷設したので、電源雑音の影響を受け難くして動作安定性の向上を図ることができるとともに、SOG部の使用効率を改善して集積度の向上を図ることができ、 According to the present invention, along a line parallel to the outer line or edge line of the desired size of the area secured on the entire surface element forming cell array (SOG), a power supply line of the area dedicated since laying the, it is possible to improve the operational stability and difficult to receive an influence of power supply noise, and improve use efficiency of the SOG portions can be improved degree of integration,
さらに、設計の柔軟性を高めてそれぞれの回路部に適合した自在な電源設計を可能にすることができる。 Furthermore, it is possible to allow a universal power supply design adapted to the respective circuit portions to enhance the design flexibility.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】一実施例の半導体集積回路の概略平面図である。 1 is a schematic plan view of a semiconductor integrated circuit according to one embodiment.

【図2】一実施例のレイアウト方法に用いるベーシックセルの概略平面図である。 2 is a schematic plan view of a basic cell used in the layout method of one embodiment.

【図3】一実施例のレイアウト方法における領域確保の概念図である。 3 is a conceptual diagram of area allocation in the layout method of the embodiment.

【図4】一実施例のレイアウト方法における領域毎の電源線敷設の概念図である。 4 is a conceptual diagram of a power supply line laid for each area in the layout method of the embodiment.

【図5】一実施例のレイアウト方法における領域毎の電源線と外周電源線との間の接続概念図である。 5 is a connection schematic diagram between the power supply line and the outer power supply line for each area in the layout method of the embodiment.

【図6】一実施例の半導体集積回路の他の概略平面図である。 6 is another schematic plan view of a semiconductor integrated circuit according to one embodiment.

【図7】従来例のメッシュ状の電源線を含むベーシックセルの概略平面図である。 7 is a schematic plan view of a basic cell including a conventional mesh-like power supply line.

【図8】従来例の領域確保の概念図である。 8 is a conceptual view of the region securing the conventional example.

【符号の説明】 DESCRIPTION OF SYMBOLS

12〜14:外周電源線 15〜18:第1〜第4の回路部(ロジック部又はマクロ部) 15a、16a、17a、18a:外縁線 15b、15c、16b、16c、17b、17c、1 12-14: outer peripheral power supply line 15 to 18: first to fourth circuit portion (logic unit or the macro section) 15a, 16a, 17a, 18a: outer edge lines 15b, 15c, 16b, 16c, 17b, 17c, 1
8b、18c:電源線 8b, 18c: power line

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】全面素子形成型セルアレイ上に確保した任意の大きさの領域内に任意のロジック部又はマクロ部を形成する半導体集積回路において、 前記領域の外縁線又は外縁線と平行する線に沿って、その領域専用の電源線を敷設したことを特徴とする半導体集積回路。 1. A semiconductor integrated circuit to form an arbitrary logic unit or macro section in the region of any secured in the entire element formation cell array on size, a line parallel to the outer line or edge line of the region along, a semiconductor integrated circuit, characterized in that laid the power line of the region only.
  2. 【請求項2】外周電源線を含むI/O領域及び該I/O 2. A comprises an outer power supply line I / O region and the I / O
    領域に囲まれた全面素子形成型セルアレイを有するベーシックセルを用意し、 該全面素子形成型セルアレイ上に任意の大きさの領域を確保し、 該領域の外縁線又は外縁線と平行する線に沿って電源線を敷設し、 該電源線と前記外周電源線との間を接続するとともに、 該電源線と前記領域の内部電源線との間を接続することを特徴とする半導体集積回路のレイアウト方法。 Providing a basic cell having the entire element formation type cell array surrounded by regions, ensuring the desired size of the area to 該全 surface elements forming cell array on, along a line parallel to the outer line or edge line of the region laying the power line Te, along with connecting the said outer peripheral power supply line and said power supply line, a layout method of a semiconductor integrated circuit, characterized in that the connection between the internal power supply line of the with the power line region .
  3. 【請求項3】前記領域の外縁線又は外縁線と平行する線に沿って敷設される電源線は、有端線であることを特徴とする請求項1記載の半導体集積回路又は請求項2記載の半導体集積回路のレイアウト方法。 3. A power supply line is laid along a line parallel to the outer line or edge line of the region, according to claim 1 semiconductor integrated circuit or claim 2 wherein the wherein the a chromatic end line layout method of the semiconductor integrated circuit.
  4. 【請求項4】前記領域は、少なくともその領域の外縁線の一部と外周電源線との間に他の領域が介在しないようにレイアウトされていることを特徴とする請求項1記載の半導体集積回路又は請求項2記載の半導体集積回路のレイアウト方法。 Wherein said region is at least a semiconductor integrated according to claim 1, wherein the other region is laid out so as not interposed between a portion of the outer edge line and the outer power supply line of the region layout method of a semiconductor integrated circuit of the circuit or claim 2, wherein.
JP28718293A 1993-11-17 1993-11-17 Semiconductor integrated circuit and layout method thereof Withdrawn JPH07142583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28718293A JPH07142583A (en) 1993-11-17 1993-11-17 Semiconductor integrated circuit and layout method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28718293A JPH07142583A (en) 1993-11-17 1993-11-17 Semiconductor integrated circuit and layout method thereof

Publications (1)

Publication Number Publication Date
JPH07142583A true true JPH07142583A (en) 1995-06-02

Family

ID=17714145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28718293A Withdrawn JPH07142583A (en) 1993-11-17 1993-11-17 Semiconductor integrated circuit and layout method thereof

Country Status (1)

Country Link
JP (1) JPH07142583A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005229650A (en) * 2001-05-06 2005-08-25 Altera Corp Pld architecture for flexible arrangement of ip functional block
JP2007027314A (en) * 2005-07-14 2007-02-01 Nec Electronics Corp Semiconductor integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005229650A (en) * 2001-05-06 2005-08-25 Altera Corp Pld architecture for flexible arrangement of ip functional block
JP4729333B2 (en) * 2001-05-06 2011-07-20 アルテラ コーポレイションAltera Corporation pld architecture for flexible placement of Ip functional blocks
US9094014B2 (en) 2001-05-06 2015-07-28 Altera Corporation PLD architecture for flexible placement of IP function blocks
JP2007027314A (en) * 2005-07-14 2007-02-01 Nec Electronics Corp Semiconductor integrated circuit device

Similar Documents

Publication Publication Date Title
US6130484A (en) Semiconductor device
US6521960B2 (en) Column transistor for semiconductor devices
US5095352A (en) Semiconductor integrated circuit device of standard cell system
US4855803A (en) Selectively definable semiconductor device
US5309015A (en) Clock wiring and semiconductor integrated circuit device having the same
US5408428A (en) Programmable bit cell
US4688072A (en) Hierarchical configurable gate array
US5148263A (en) Semiconductor device having a multi-layer interconnect structure
US4884115A (en) Basic cell for a gate array arrangement in CMOS Technology
US5007025A (en) Power and signal line bussing method for memory devices
US5917230A (en) Filter capacitor construction
US6858928B1 (en) Multi-directional wiring on a single metal layer
US4746966A (en) Logic-circuit layout for large-scale integrated circuits
US5008728A (en) Semiconductor integrated circuit device having an improved arrangement of power source lines
US5140556A (en) Semiconductor memory circuit having dummy cells connected to twisted bit lines
US5283753A (en) Firm function block for a programmable block architected heterogeneous integrated circuit
US5401989A (en) Semiconductor device having a basic cell region and an I/O cell region defined on a surface thereof
JPH10178110A (en) Semiconductor storage device
US5155390A (en) Programmable block architected heterogeneous integrated circuit
US5416431A (en) Integrated circuit clock driver having improved layout
US5668389A (en) Optimized power bus structure
US20020113319A1 (en) Flip chip semiconductor device having signal pads arranged outside of power supply pads
US20050169042A1 (en) Multi-threshold MIS integrated circuit device and circuit design method thereof
JP2009267094A (en) Layout structure of standard cell, standard cell library and layout structure of semiconductor integrated circuit
JP2002057270A (en) Stacked chip semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20010130