JPH0454388B2 - - Google Patents

Info

Publication number
JPH0454388B2
JPH0454388B2 JP56503472A JP50347281A JPH0454388B2 JP H0454388 B2 JPH0454388 B2 JP H0454388B2 JP 56503472 A JP56503472 A JP 56503472A JP 50347281 A JP50347281 A JP 50347281A JP H0454388 B2 JPH0454388 B2 JP H0454388B2
Authority
JP
Japan
Prior art keywords
polysilicon
layer
gate
type
active region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56503472A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57501706A (enExample
Inventor
Ronarudo Uein Burauwaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of JPS57501706A publication Critical patent/JPS57501706A/ja
Publication of JPH0454388B2 publication Critical patent/JPH0454388B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP56503472A 1980-10-20 1981-10-19 Expired JPH0454388B2 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/198,428 US4345366A (en) 1980-10-20 1980-10-20 Self-aligned all-n+ polysilicon CMOS process

Publications (2)

Publication Number Publication Date
JPS57501706A JPS57501706A (enExample) 1982-09-16
JPH0454388B2 true JPH0454388B2 (enExample) 1992-08-31

Family

ID=22733341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56503472A Expired JPH0454388B2 (enExample) 1980-10-20 1981-10-19

Country Status (4)

Country Link
US (1) US4345366A (enExample)
EP (1) EP0063578B1 (enExample)
JP (1) JPH0454388B2 (enExample)
WO (1) WO1982001380A1 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4422885A (en) * 1981-12-18 1983-12-27 Ncr Corporation Polysilicon-doped-first CMOS process
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
US4516313A (en) * 1983-05-27 1985-05-14 Ncr Corporation Unified CMOS/SNOS semiconductor fabrication process
US4633571A (en) * 1984-04-16 1987-01-06 At&T Bell Laboratories Method of manufacturing a CMOS cell array with transistor isolation
US4603472A (en) * 1984-04-19 1986-08-05 Siemens Aktiengesellschaft Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation
US4749662A (en) * 1984-12-14 1988-06-07 Rockwell International Corporation Diffused field CMOS-bulk process
US4701423A (en) * 1985-12-20 1987-10-20 Ncr Corporation Totally self-aligned CMOS process
JPS6446979A (en) * 1987-08-14 1989-02-21 Oki Electric Ind Co Ltd Analogue switch and sample-and-hold circuit with analogue switch
US5272367A (en) * 1988-05-02 1993-12-21 Micron Technology, Inc. Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams)
AU5977190A (en) * 1989-07-27 1991-01-31 Nishizawa, Junichi Impurity doping method with adsorbed diffusion source
EP0417456A3 (en) * 1989-08-11 1991-07-03 Seiko Instruments Inc. Method of producing semiconductor device
EP0430275A3 (en) * 1989-12-01 1993-10-27 Seiko Instr Inc Doping method of barrier region in semiconductor device
CA2031253A1 (en) * 1989-12-01 1991-06-02 Kenji Aoki Method of producing bipolar transistor
US5366922A (en) * 1989-12-06 1994-11-22 Seiko Instruments Inc. Method for producing CMOS transistor
JP2920546B2 (ja) * 1989-12-06 1999-07-19 セイコーインスツルメンツ株式会社 同極ゲートｍｉｓトランジスタの製造方法
CA2031636A1 (en) * 1989-12-06 1991-06-07 Kenji Aoki Method of producing cmos transistor
EP0505877A2 (en) * 1991-03-27 1992-09-30 Seiko Instruments Inc. Impurity doping method with adsorbed diffusion source
WO1993016494A1 (en) * 1992-01-31 1993-08-19 Analog Devices, Inc. Complementary bipolar polysilicon emitter devices
US5605861A (en) * 1995-05-05 1997-02-25 Texas Instruments Incorporated Thin polysilicon doping by diffusion from a doped silicon dioxide film
US6245604B1 (en) * 1996-01-16 2001-06-12 Micron Technology Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
US5585299A (en) * 1996-03-19 1996-12-17 United Microelectronics Corporation Process for fabricating a semiconductor electrostatic discharge (ESD) protective device
FR2757683B1 (fr) * 1996-12-20 1999-03-05 Sgs Thomson Microelectronics Transistor bipolaire et capacite
US6030752A (en) * 1997-02-25 2000-02-29 Advanced Micro Devices, Inc. Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device
US5956591A (en) * 1997-02-25 1999-09-21 Advanced Micro Devices, Inc. Method of making NMOS and PMOS devices having LDD structures using separate drive-in steps
US5789300A (en) * 1997-02-25 1998-08-04 Advanced Micro Devices, Inc. Method of making IGFETs in densely and sparsely populated areas of a substrate
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
KR20250105477A (ko) 2017-07-27 2025-07-08 바이오메리욱스, 인코포레이티드. 격리 튜브

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3700507A (en) * 1969-10-21 1972-10-24 Rca Corp Method of making complementary insulated gate field effect transistors
US3608189A (en) * 1970-01-07 1971-09-28 Gen Electric Method of making complementary field-effect transistors by single step diffusion
US3646665A (en) * 1970-05-22 1972-03-07 Gen Electric Complementary mis-fet devices and method of fabrication
US3986896A (en) * 1974-02-28 1976-10-19 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing semiconductor devices
CA1017073A (en) * 1974-06-03 1977-09-06 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
JPS5214958A (en) * 1975-07-25 1977-02-04 Hitachi Ltd Cooling system for super cold temperature
NL7604986A (nl) * 1976-05-11 1977-11-15 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting, en inrichting vervaardigd door toe- passing van de werkwijze.
JPS5324281A (en) * 1976-08-19 1978-03-06 Sony Corp Production of insulated gate type field effect transistors
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate

Also Published As

Publication number Publication date
EP0063578A1 (en) 1982-11-03
US4345366A (en) 1982-08-24
EP0063578B1 (en) 1987-03-11
JPS57501706A (enExample) 1982-09-16
WO1982001380A1 (en) 1982-04-29
EP0063578A4 (en) 1984-07-06

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