JPH0454082A - Reception, processing and selection output unit for high definition television signal - Google Patents

Abstract

PURPOSE:To simplify the entire circuit constitution and to make the circuit scale small by applying in-field signal processing to a signal subject to still picture processing at an encoder of a sender side and a signal subject to moving picture processing so as to reproduce a video signal. CONSTITUTION:A MUSE signal received from an input terminal 101 is demodulated into an analog signal whose band width is nearly 8MHz by a demodulation circuit 102, converted into a digital signal by an A/D converter 103. The MUSE signal subject to processing is inputted to an in-field signal processing section 1, from which a 1125/30 scanning line signal, a 525/60 scanning signal and a 525/30 scanning signal are obtained. The 1125/30 scanning line signal is inputted to an input terminal (a) and the 525/60 scanning signal is inputted to an input terminal (b) of a selector 1401 by the said in-field signal processing circuit 1 respectively. Thus, an output signal of the television system corresponding to the display device in use and an output signal corresponding to a package for a VTR or the like are simultaneously obtained from the side (b) of a selector 1402.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides high-definition television system (hereinafter referred to as HDTV) by receiving and processing high-definition television signals.
video signals that use the double-speed television system (hereinafter referred to as the EDTV system), and video signals that use the standard-speed scan television system (hereinafter referred to as the NTSC system).
Receiving and processing of high-definition television signals that take video signals, and select and output any of them.
This invention relates to a dual selection output device.

[Prior Art] In recent years, as television screens have become larger, there has been a demand for higher quality display images. In response to these demands, various high-definition television systems are being studied. In Japan, MUSE is a high-definition television signal transmission system developed by NHK (Japan Broadcasting Corporation).
(Multiple Sub-NyquistSam
The pling encoding method is typical, and will be explained below using this as an example.

The MUSE method is in the material rNHK Technical Research Journal 1986.
Volume 39, Issue 2, Volume 172, p18-p53”
The feature is that the number of scanning lines is 112.
5, Increment signal with a frame frequency of 30Hz,
The screen aspect ratio is 16:9, which is wider than the current screen.

In addition, this MUSE method uses 1
The still image transmission band is 24 MHz by using a multiple subsample band compression method that thins out pixels every other pixel, and in the case of still images, thins out every other pixel so that one cycle takes two frames.
, a signal with a video transmission band of 16 MHz is band-compressed to 8 MHz and then transmitted.

Therefore, the MUSE decoder on the receiving side that receives this has two signal processing systems, one for still image/video processing, and a motion detection circuit for determining still images/videos, and one for still image/video processing. The scale of the signal processing circuit has become extremely large, including a MIX circuit for mixing signals, a frequency conversion circuit, and the like.

Therefore, instead of using such complex, large-scale, and expensive signal processing circuits, the current NT
A television system (EDT) that uses a television receiver based on the SC system or displays images using double-speed scanning
Progress is also being made in the development of a signal processing circuit that can receive and inexpensively reproduce images transmitted by a high-definition television system using a V) receiver.

For such purposes, high-definition television signals may be converted into standard television signals or double-speed television signals (ED).
Regarding the method of converting to TV signals), "Kasezawa et al."
“DTV Compatible MUSE/NTSC Converter” Television Society Technical Report.

VOL, 14, No, 8 pp 13-18 (
1990) reported in J.

EDTV compatible MUSE/NT mentioned in this report
The major features of the SC converter are as follows.

One is the output compatible with HDTV, that is, the scanning m number is 11.
525 high-definition television signals of 25 lines/frame
It is possible to obtain an output converted to a double-speed scanning signal of the book/field. Second, we are trying to use frame memory to eliminate aliasing interference.

This converter will be explained below using FIG. 2.

In FIG. 2, 201 is a MUSE signal input terminal;
2 is an amplifier circuit, 203 is an A/D conversion circuit that converts an analog signal into a digital signal, 204 is an ALC (automatic level control circuit) circuit that controls the signal level, and 205 is a MUSE that is non-linearly processed on the transmitting encoder side. A de-emphasis circuit that returns the signal to a linear state, 206 a frame memory, 207
is a horizontal low-pass filter (hereinafter referred to as LPF), 20
209 is a vertical LPF.
, 210 is an edge enhancement circuit, 211 is a time axis conversion circuit that reads out a signal written with a 32.4 MHz clock using a 20.16 M7 clock or a 30.24 MHz clock, and 212, 213, and 214 are respectively A time axis conversion circuit, 215, 216, a D/A conversion circuit that converts a digital signal into an analog signal, 217,
218.219 is the output terminal for luminance signal and color difference signal compatible with EDTV, 220, 221.222 is NTSC
This is an output terminal for luminance signals and color difference signals compatible with ink-lace scanning displays.

Next, the operation of the circuit shown in FIG. 2 will be explained.

The analog MUSE signal inputted from the input terminal 201 is converted into a digital signal by the A/D converter 203 while accurately maintaining the signal level according to the control signal from the ALC circuit 204.

The de-emphasis processing unit 205 performs processing to return the MUSE signal, which has been non-linearly processed on the transmitting side encoder side, to a linear state, and then processes the MUSE signal which has been non-linearly processed on the transmitting side encoder side to a linear state.
It is supplied to the frame memory section 206.

The horizontal LPF section 207 performs horizontal LPF processing on both the incoming signal and the signal delayed by one frame by the frame memory section 206.

The aliasing removal circuit 208 has a built-in frame memory, and performs motion detection based on a two-frame difference and mixing processing. The mixing processing section obtains a signal of the current frame in the case of a moving image, and an average value signal of the current frame and the previous frame in the case of a still image, and mixes and outputs them according to the motion detection signal.

The aliasing removal circuit 208 attempts to obtain a signal from which aliasing interference due to frame offset subsampling processing during still image reception has been removed.

In the vertical LPF section 209, the number of scanning lines of the MUSE signal is 11.
From 25 lines, processing is performed to create 525 scanning lines with the center of gravity of the scanning lines aligned in accordance with EDTV.

The edge enhancement processing unit 210 performs edge enhancement processing only on the luminance signal. In the time axis conversion processing section 211, a signal is written using a write clock synchronized with the MUSE signal, and the signal is read out using a read clock corresponding to the EDTV synchronization signal. The above HDTV signal is D/A
The signal is input to the converter 215 and converted into an analog signal.

Further, the EDTV signal is converted to the time axis conversion unit 212.21.
3, 214, and here, the read frequency for time axis expansion is input to 172 of the time axis conversion processing section 211.
NTSC by reading out interlace.
Creates standard television signals. The signal corresponding to the standard television is input to the D/A converter 216 and converted into an analog signal.

[Problem to be solved by the invention]

The MUSE decoder in the conventional example described above has a configuration in which the luminance and color difference signals are switched between moving image processing and still image processing depending on the presence or absence of image movement. For this reason, the scale of the processing circuit has become extremely large.

Furthermore, the display for displaying high-definition television signals had to be a special horizontally long display with an aspect ratio of 16=9 in view of the NTSC system. Therefore, there was a problem that the television receiving system became very expensive.

In addition, in the method of converting the high-definition television signal in the conventional example above to a standard television signal or to a double-speed television signal (sequential scanning signal) compatible with EDTV, all NTSC system receivers are compatible. Although it is possible to do so, vertical LPF processing converts the center of gravity of the scanning line to a standard (NTSC) display that performs interlaced scanning or for EDTV, so it cannot be used for high-definition televisions with an aspect ratio of 16:9. Even if you want to display it on a horizontal display for John,
There was a problem that it could not be dealt with.

Furthermore, since the aliasing removal circuit with the above configuration performs inter-frame processing after performing horizontal LPF processing, the flicker generated in the frame direction (time direction) does not flicker, but the aliasing interference With a border on the screen (
There was a problem that it would stop and remain.

An object of the present invention is to solve the above-mentioned problems, and when receiving high-definition television signals, it can be applied not only to high-definition television receivers but also to television system receivers such as the NTSC system and EDTV system that currently exist in the world. Another object of the present invention is to provide an inexpensive high-definition television signal reception, processing, and selection output device that makes it possible to display images.

In other words, according to the high-definition television signal reception, processing, and selection output device provided by the present invention,
When a high-definition television signal is received, a video signal that follows the high-definition television system (HDTV system), a video signal that follows the double-speed television system (EDTV system), and a video signal that follows the standard-speed scanning television system (NTSC system) correspond to the received high-definition television signal. video signals of three formats are created, and the video signals are output as a combination of HDTV and NTSC, a combination of EDTV and NTSC, or each format alone, depending on the user's wishes. Therefore, by connecting a corresponding display to each output terminal, it is possible to enjoy a television screen according to the user's preference (or economy).

[Means for Solving the Problem] In order to achieve the above object, the present invention receives and processes a high-definition television signal to create a video signal that adopts a high-definition television system (hereinafter referred to as an HDTV system). , double speed television system (hereinafter referred to as EDTV system)
and a video signal that follows the standard speed scan television system (hereinafter referred to as the NTSC system),
As a high-definition television signal reception, processing, and selection output device that selects and outputs any of the high-definition television signals, it includes a demodulation means for demodulating the received analog high-definition television signal, and a demodulation output from the demodulation means. an A/D conversion means for converting from an analog signal to a digital signal; and a synchronization signal reproducing device that receives the digital signal from the A/D conversion means and extracts and reproduces control signals such as clock signals and synchronization signals for signal processing. and a control signal from the synchronization signal reproducing means to perform in-field signal processing on the digital high-definition television signal that is the demodulated output from the demodulating means, thereby converting the HDTV system into a system digital video signal. , EDTV format digital video signals, and NTSC
an in-field signal processing means for outputting in parallel a digital video signal employing the HDTV system;
Digital video signals in three formats, TV format and NTSC format, are input, and from among these, a combination of a digital video signal that uses the HDTV format and a digital video signal that uses the NTSC format, or a combination of a digital video signal that uses the EDTV format and a digital video signal that uses the NTSC format. A selection means for selecting and outputting a combination with a digital video signal to be adopted, and a D/A conversion means for converting the digital video signal of the combination selected by the selection means into an analog signal and outputting it. Configured the device.

[Effect]

After receiving, the high-definition television signal is demodulated by the demodulation means and converted into a digital signal by the A/D conversion means, and is supplied to the synchronization signal reproduction means and the in-field signal processing means. The intra-field signal processing means performs intra-field signal processing on both still image processed signals and moving image processed signals on the transmitting encoder side to reproduce video signals.

For this reason, large circuits such as frame memory for interframe interpolation processing, motion detection, field memory for interfield interpolation, frequency conversion circuit, mixer, etc. required for each of the luminance signal processing section and color difference signal processing section are required. There is no need for a signal processing section that requires a 100% signal processing section, and the overall circuit configuration can be simplified and the circuit scale can be reduced.

Further, the intra-field signal processing means simultaneously creates an NTSC scan line, an HDTV (7) scan line, and an HDTV (D scan line) in parallel.

Furthermore, N created by the above-mentioned in-field signal processing means
The Tsc, EDTV, and HDTV signals are manually input to the selection means, and the output signals are HDTV, NTSCl, or E.
At least two combinations of output signals, DTV and NTSC, can be obtained.

By converting this signal into an analog signal using a D/A conversion means and outputting it, video signals compatible with two combinations of television systems can be obtained.

In other words, as an image display means, it is possible to support a 4:3 display currently used for fishing boats and a 16:9 display, and to create a system that receives high-quality television signals at a low cost. Can be configured.

Furthermore, when the in-field signal processing means is implemented as an integrated circuit, it can be realized with a smaller number of terminals than when outputting all three types of television systems, making it a practical integrated circuit.

〔Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 1 shows an embodiment in which two types of television signals can be output.

In Fig. 1, 101 is an input section for the MUSE signal being broadcast, and 102 is the input section for the received MUSE signal with a band of approximately 8M.
103 is an A/D converter that converts the analog signal into a digital signal; 104 is a digitized MUSE signal outputted from the A/D converter 103; a synchronization signal and a control signal; a control signal generation section that extracts signals and generates a system clock, etc.; 105 is a de-emphasis processing section;
It is.

1, the number of scanning lines is 1125 and the frame frequency is 30Hz by processing the transmitted MUSE signal only in the field.
scanning line signal for increment scan (hereinafter referred to as 1125/30), number of scanning lines 525, frame frequency 60H
z non-interlaced scanning (hereinafter referred to as 525/60)
scanning line signal, number of scanning lines 525, frame frequency 3
an in-field signal processing circuit that creates a scanning line signal for 0 increment scanning (hereinafter referred to as 525/30);
1401.1402 is a selector that inputs and selectively outputs the output signal of the intra-field signal processing circuit l; 1403.1
404 is a D/A converter, 1405°1406.140
7 is the output terminal of the D/A converter 1403, 1408, 14
09.1410 is the output terminal of the D/A converter 1404.

Furthermore, in the in-field signal processing circuit 1 of FIG.
401 is a field interpolation processing circuit, 107 is 1125
109 is a speed conversion processing circuit that converts the luminance signal and color difference signal into a 525/60 scanning line signal, 110 is a color difference signal processing circuit for 525/60 output, and 111 is a color difference signal processing circuit for /30 output. For the 525/60 luminance signal and color difference signal, the number of scanning lines is thinned out to 1/2 to 525/3.
Speed conversion processing circuit for converting into a scanning line signal for 0, 124
．． 125 is a blanking insertion circuit.

Next, the first circuit operation will be explained. Input terminal 10
The MUSE signal input from A 1 is demodulated into an analog signal with a band of approximately 8 MHz by a demodulation circuit 102, and then
The signal is converted into a digital signal by the /D converter 103.

The MUSE signal converted into a digital signal is sent to a de-emphasis processing section 105 and a control signal generation section 104.
supplied to

The control signal generating section 104 extracts a synchronization signal and a control signal from the MUSE signal, and also generates a system clock and the like to operate the entire system. In the de-emphasis processing unit 105, the M
The USE signal is subjected to inverse non-linearity and filtered with de-emphasis characteristics to reduce triangular noise in the transmission path, and also to reduce noise components that are noticeable in areas where the amplitude of the video signal is small.

The MUSE signal subjected to the above processing is input to the in-field signal processing unit 1, and is converted into the 1125/30 scanning line signal and the 52
A 5/60 scanning line signal and a 525/30 scanning line signal are obtained. The selector 1401 receives the 1125/30 scanning line signal from the intra-field signal processing circuit 1 at the input terminal a.
525/60 scanning line signals are respectively input to the input terminals. In addition, the selector 1402 receives the 525/60 scanning line signal from the in-field signal processing circuit 1 at the input terminal a, and the 525/30 scanning line signal from the input terminal a.
Enter each.

The selectors 1401 and 1402 switch the selection input to a or b depending on the display used. If the display to be used has an aspect ratio of 4=3 and is capable of double speed scanning, the selector 1401.14
Let the output signal of 02 be the b side. This allows the selector 140
1 selects the 525/60 scanning line signal, converts it to an analog signal in the D/A converter 1403, and outputs it to the output terminal 14.
At 05.1406.1407, a 525/60 luminance signal and a (R-YL (B-Y) color difference signal) are obtained.

Further, the selector 1402 selects the 525/30 scanning line signal, converts it into an analog signal in the D/A converter 1404, and outputs the 525/30 scanning line signal to the output terminals 1408, 1409, and 1410.
25/30 luminance signal and (RY), (B-Y)
color difference signals are obtained.

Next, if the display to be used is a high-definition television display with a horizontal aspect ratio of 16:9, the output signals of selectors 1401 and 1402 are
side.

As a result, the selector 1401 selects the 1125/30 scanning line signal, converts it into an analog signal in the D/A converter 1403, and outputs the 1125/30 luminance signal and ( R-Y), (B
-Y) color difference signals are obtained. Further, the selector 1402 selects the 525/60 scanning line signal, and the D/A converter 1
404 converts it into an analog signal and outputs it to an output terminal 1408.
At 1409.1410, a 525/60 luminance signal and (RY) and (B-Y) color difference signals are obtained.

According to the configuration shown in FIG. 1, an output signal corresponding to a package such as a VTR (i.e., a system signal for the NTSC system) is output from the b side of the selector 1402 at the same time as a television system output signal corresponding to the display to be used. Obtainable.

Next, the operation of the intra-field signal processing circuit 1 shown in FIG. 1 will be explained.

In the intra-field signal processing circuit 1, the intra-field interpolation processing circuit 401 inputs the signal from the de-emphasis processing section 105, and performs processing on the received MUSE signal.
Performs two-dimensional filter processing within the field to create still images and
Regardless of the video signal, both luminance and color difference signals undergo intra-field interpolation processing, and the band is 1125/30 with a bandwidth of 16M7 or higher.
and create an output signal of M which is 1125/30.
The scanning line gravity center position of the USE signal is set to the scanning line number 1125/2.
, a scanning line is created that is converted to a barycentric position for non-interlaced scanning with a frame frequency of 607, that is, a scanning line barycentric position compatible with HDTV. Here, the brightness signal of 1125/30 has a blanking period inserted in the blanking insertion circuit 124 and is supplied to the selector 1401.

Regarding the 1125/30 color difference signal, when it is output from the field interpolation circuit 104, it has still been band-compressed in the horizontal/vertical directions and the time axis direction, so it is input to the color difference signal processing unit 107 and is compressed on the time axis. After decompression and aligning the luminance signal with the horizontal time axis, line-sequential processing (vertical line interpolation) is performed to calculate (R-Y) for each line.
(B-Y) Create a signal. Furthermore, we perform interpolation processing,
After performing pixel interpolation in the horizontal direction and inserting a blanking period in the blanking insertion circuit 124, the selector 14
Supply to 01.

In addition, the EDT in the field interpolation processing circuit 401
To create a scanning line with a scanning line center of gravity position corresponding to V, select 4.
A scanning line that can display a 16:9 horizontally elongated image on a :3 display is created, allowing two display formats: zoom mode and wide mode.

However, the zoom mode refers to a mode in which the left and right sides of a 16:9 horizontally long image are cut out and the image is displayed on a 4:3 display at the same time (hereinafter referred to as ZOOM), and the wide mode refers to a mode in which the left and right sides of a 16:9 horizontally long image are displayed. This shows a mode (hereinafter referred to as WIDE) in which a 16:9 image is displayed on a 4:3 display with blanking periods provided above and below the image.

The speed conversion processing circuit 109 converts the speed of both the luminance and color difference signals subjected to the above signal processing into 525/60 EDT compatible outputs, and after inserting a blanking period in the blanking insertion circuit 125 for the luminance signal. , speed conversion circuit 111, and selectors 1401 and 1404. Here, the color difference signal is subjected to speed conversion processing in a path independent from the luminance signal, and processing that also serves as time axis expansion is performed.
Align the luminance signal and the horizontal time axis.

The color difference signal processing circuit 110 performs vertical line interpolation (
Line sequential processing) is performed, and for each line (R-Y), (
A B-Y) signal is created, and then subjected to interpolation processing to perform pixel interpolation in the horizontal direction, and then supplied to the blanking insertion circuit 125. The color difference signal into which the blanking period has been inserted by the blanking insertion circuit 125 is processed by the speed conversion processing circuit 11.
1 and is output to selectors 1401 and 1402.

The speed conversion processing circuit 111 thins out the number of scanning lines to 1/2 for the 525/60 luminance signal and color difference signal converted to the EDTV compatible output, and generates 525/30 increment scanning lines, that is, It is converted into an output signal compatible with a standard speed NTSC display and supplied to the selector 1402.

According to the configuration shown in the in-field signal processing circuit 1 of FIG. 1, it is possible to generate digital video signal output compatible with all types of displays and packages such as VTRs that currently exist in the world. Furthermore, in the television receiving device having such a configuration, the blanking insertion circuit 124125 may be deleted and a blanking insertion circuit may be placed in front of the D/A converter or within the D/A converter instead. For example, the memory capacity of the speed conversion processing circuit 111 can be reduced by the blanking period.

Furthermore, in FIG. 1, even when the selector 1402 selects a number of pieces, the readout of the speed conversion processing circuit 109 is
By setting the horizontal synchronization to 1/2 increment synchronization and setting the readout clock to 1/2, it is possible to create a signal compatible with NTSC (a signal compatible with packages such as VTRs), so the speed conversion processing circuit Without 111,
Output terminal 140B, 525/30 to 1409.1410
It is also possible to obtain an output signal of

Therefore, based on this embodiment, consider the case where the above circuit is integrated into an LSI and the memory (speed conversion circuit) is externally attached.
When using a high-definition television display with an aspect ratio of 16:9, the line memory (capacity of 3 lines) used in the speed conversion processing circuit 111 for creating 525/30 output is reduced. be able to.

Furthermore, when using a display with a 4:3 aspect ratio and capable of double-speed scanning, the color difference signal processing section for 1125/'30 is not used, so the color difference signal processing section for 1125/30 should be used. It is also possible to reduce the line memory (capacity of 3 lines).

Next, an example of the internal configuration and operation of the field interpolation processing circuit 401 shown in FIG. 1 will be described using FIGS. 3 and 4.

FIG. 3 shows the field interpolation processing circuit 4 in FIG.
FIG. 2 is a block diagram showing an example of the configuration of 01.

In FIG. 3, the same reference numerals as in FIG. 1 perform the same operations.

In FIG. 3, 501 is a MUSE signal input terminal input from the de-emphasis processing unit 105 in FIG.
2 is a TRF (transversal filter) processing circuit;
503 and 504 are the storage capacity for one line of the MUSE signal (here, the capacity is for the signal after TRF processing, that is, the capacity for one line after horizontal interpolation processing. 480 * 2
505 has a storage capacity of 2 lines of color difference signals (94*2*8 bits)
508 is a Y/C control signal input terminal with different signal levels for the luminance signal period and color difference signal period; 506, 507, and 515 are Y/C control signal input terminals for the luminance signal period and the b side for the color difference signal period; , a selector that selects and outputs the respective selections.

509.510, 514, 516 are adders, 512.5
13 is a 2-bit control signal input terminal for switching selection input for each field; 511 is a control signal input terminal 512;
a selector 51 that switches and outputs input signals for each field according to a 2-bit control signal input from 513;
7 is a vertical delay processing section, 518 is a vertical center of gravity position conversion processing section, 519 is an output terminal that outputs the scanning line at the scanning line center of gravity position for 525/60, and 520 is an output terminal that outputs the scanning line for 1125/30. be.

FIG. 4 is a scanning line structure diagram showing the operating principle of FIG. 3. In FIG. 4, ■ is the scanning line center of gravity position of the MUSE signal, ■ is the scanning line center of gravity position for 525/60 in 200M mode, ■ is the scanning line center of gravity position for 525/60 in WIDE mode, FIG. 3 is a diagram viewed from the vertical-time axis direction, respectively.

However, in order to simplify the explanation, only the luminance signal is shown here.

As shown in (2), the MUSE signal has an interlace relationship between the scanning lines between fields. As an example, there is a method of creating a scanning line at the center of gravity position as shown in ■.
In the IDE mode, when the number of scanning lines is further thinned out to 3/4 compared to the 700M mode, a method of creating scanning lines at the center of gravity position as shown in (1) may be considered as an example.

Therefore, the scanning line of the first field of the incoming signal is shown in Figure 4.
As seen in Al, A2, A3A4,
A5..., the scanning line of the second field is BIB2. B3
．． B4. In the case of B5..., in the 200M mode (Fig. 4 ■), in the first field, α1 = (3 (AI) + 4 (A2) + (A3)) /
8α2-(3(A2) +4(A3) + (A4)
) / 8.

α3 = (3(A3)+4(A4)+(A5))/
8-・.

Then, in the second field, β1 = ((Bl)+4(B2)+3(B3))/
8゜β2 = ((B2') +4(B3) +3(B
4) ) / 8.

B3 = ((B3)+4(B4)+3(B5))/
8. It is sufficient to create a scanning line at the center of gravity position represented by...

Furthermore, in the WIDE mode that performs 3/4 compression processing in the vertical direction (Fig. 4 ■), in the first field, μm = (3 (AI) + 4 (A2) + (A3)) /
8.

β2 = (2(A2) +4(A3) +2(A4)
) / 8.

β3 = ((A3)+4(A4)+3(A5))/
8. The scanning line of the center of gravity position represented by ..., and in the second field, β1 = ((BO) + 4 (Bl) + 3 (B2)) /
8.

β2 = (3(B2)+4(B3)+(B4))/
8゜β3 = (2(B3)+4(B4)+2(B5)
) /8 . . . It is sufficient to create a scanning line at the center of gravity position.

Next, the operation of the circuit shown in FIG. 3 will be explained using FIG. 4.

The MUSE signal is input to the input terminal 501 from the de-emphasis processing section 105 shown in FIG.
2, horizontal pixel interpolation and horizontal passband limit to 16
Processing is performed to keep the frequency below MHz (in order to minimize aliasing interference during still image reproduction, the horizontal passband is up to 12M&).

The signal subjected to the above processing is input to the vertical delay processing 517. In the vertical delay processing section 517, the line memory 503,
504, one line delay output and two
A line delay output is obtained, and a 4-line delay output of the color difference signal is obtained by the line memory 505. The selector 506 receives the 1-line delay output and the 2-line delay output from the line memories 503 and 504, and the selector 507 receives the
Two line delayed outputs and four line delayed outputs of color difference signals are input from the line memories 504 and 505.

Furthermore, the selectors 506 and 507 have control signal input terminals 5
Y/C from 08! lI? An I signal is input, and when a luminance signal is input, the a side is selected, and when a color difference signal is input, the b side is selected and output. Therefore, the vertical delay processing section 517
, when the incoming signal is A3 shown in FIG. 4 above, Al, A2 . This means that A3 has been obtained.

Here, in the color difference signal period, A(-1) (although not shown in the figure, means the scanning line two lines before A1) +
This means that Al and A3 are obtained.

However, the color difference signal is subjected to vertical band compression processing, and each line is divided into (R-Y), (B-Y) (R-Y).
, (B-Y)... Therefore, once the scanning line is obtained as described above, the subsequent color difference signal processing is
The same processing as the luminance signal will be performed. Therefore,
From now on, we will explain the operation focusing on the luminance signal.

Scanning line A input to the vertical center of gravity position conversion processing unit 518
I and A3 are averaged by adder 509 to obtain (AI+A3)/2, which is input to selector 515, 511 and adder 510. Moreover, the scanning lines Al and A3 are
The scanning line A1 is input to the selector 511, and the scanning line A1 is input to the selector 511.
Enter 5. The adder 510 inputs the output signal of the adder 509 and the signal obtained by doubling the scanning cotton A2, performs addition, and obtains ((AI)+4(A2)+(A3))/2. Enter .516.

The selector 511 selects the 1st . In the field corresponding to the third field, the scanning line input to the φ side is
The second. In the field corresponding to the fourth field, the scanning line input to the π side is selected and output.

Also, when in WIDE mode, 1. Third...
In the field corresponding to the field, the φ side,
The scanning lines input to the ω side and the π side are shown in 2. in Figure 4 (■). Fourth
... In the field corresponding to the field, scanning lines input to the π side, ω side, and φ side are selected and output in the input order.

Further, an adder 514 inputs the output signal of the adder 510 and the output signal from the selector 511 and adds them to 1/1.
The output signal multiplied by 4 is input to the output terminal 519 as the scanning line at the center of gravity of the 525/60 scanning line. That is, the output terminal 519 has the first . In the third field, (3 (AI) + 4 (A2) + (
A3) ) / 8-β1゜(3(A2) +4(A3
) + (A4) ) / 8 = The scanning line at the center of gravity position represented by α2. l /8−β1+
(B2)+4(B3)+3(B4)) /8 =β2・
The scanning line of the center of gravity position represented by ... is output, and furthermore,
In WIDE mode, which performs 3/4 compression processing in the vertical direction, the first. In the third field, (3(At
) +4 (A2) + (A3) ) / s = μm
(2(A2) +4(A3) +2(A4) ) /
8 =μ2.・.

The scanning line of the center of gravity position represented by
...In the field, ((BO)+4(Bl)+3(B2))/8-ν1゜(3(B2)+4(B3)+(B4))/8 =ν2
The scanning line at the center of gravity position represented by . . . will be output. This corresponds to creating a scanning line at the center of gravity of the 525/60 scanning line based on the principle shown in FIG.

On the other hand, the selector 515 receives the Y/C control signal from the control signal input terminal 508 in the same way as the selectors 506 and 507, and when the luminance signal is input, selects the a side and outputs the scanning line A3. When inputting color difference signals, select the b side (A(
-1)+A3)/2 is output and input to the adder 516. The adder 516 always adds (3(
We get Al)+4(A2)+(A3))/8,
When inputting color difference signals, always 2 (2A (-1) + 4 (A
l)+2(A3))/8 is obtained and inputted to the output terminal 520 as a 1125/30 scanning line.

As described above, constantly creating a scanning line with one center of gravity in each field corresponds to a shift in the center of gravity of the scanning line relative to the input scanning line. Therefore, the scanning lines output to the output terminal 520 have a 1125/30 interlace relationship for each field. Therefore, the above output signal can be used as a 1125/30 scanning line.

According to the circuit configuration shown in FIG. 3, the line memory of the intra-field interpolation processing circuit 401 is shared, and a part of the vertical scanning line centroid position conversion circuit for creating the scanning line centroid position for 525/60 is used. By using the same intra-field interpolation processing circuit 401, it is possible to simultaneously obtain a scanning line output for a display compatible with high-definition television, a scanning line output of the center of gravity position of a scanning line for an EDT compatible display in 200M mode, and WIDE mode. can.

FIG. 5 shows the intra-field interpolation processing circuit 4 in FIG.
It is a professional 7th drawing showing another example of a composition of 01. In FIG. 5, the same reference numerals as in FIGS. 1 and 3 perform the same operations.

In FIG. 5, 701, 702, 703 are the TRF (1-transversal filter) processing circuit 50 of FIG.
A TRF processing circuit 704 equivalent to 2 is a vertical delay processing section having the same internal configuration as the vertical delay processing section 517 in FIG.

Next, the operation of the circuit shown in FIG. 5 will be explained.

The de-emphasis processing unit 1 obtained from the input terminal 501
The output signal of 05 is input to the vertical delay processing section 704.

The vertical delay processing section 704 has the same internal configuration as the vertical delay processing section 517 shown in FIG. However, the input signal is the signal input to the vertical delay processing section 517 in FIG.
Since the signal before being subjected to horizontal interpolation processing by the TRF processing circuit 502 is input, the memory capacity is limited to 5 in FIG.
Half the memory capacity built into the 17 vertical delay processing units is sufficient.

When the scanning line A3 shown in FIG. 4 arrives at the vertical delay processing section 704, the output signal is AI,
This means that A2 and A3 are obtained. The above scanning line A
l, A2. A3 are TRF processing circuits 703 and 7, respectively.
02 and 701, and each TRF processing circuit performs horizontal pixel interpolation and horizontal pass band limitation similarly to the TRF processing circuit 502 in FIG.

The scanning lines AI and A2A3 subjected to the above processing are input to the vertical center of gravity position conversion processing unit 518, and the scanning line at the center of gravity position of the 525/60 scanning line is input to the output terminal 519. creates and outputs 1125/30 scanning lines respectively.

According to the configuration shown in FIG. 5, compared to the configuration shown in FIG.
Although the logic part of the TRF processing circuit in the intra-field interpolation processing section increases, the memory capacity of the vertical delay processing section is halved, and the scanning line output for display compatible with high-definition television, 200M mode, and WIDE mode are improved. It is possible to simultaneously obtain the scanning line output of the scanning line gravity center position for an HDTV compatible display.

FIG. 6 shows the field interpolation processing circuit 4 in FIG.
FIG. 2 is a block diagram showing another example of the configuration of 01. In FIG. 6, the same reference numerals as those in FIGS. 1, 3, and 5 perform the same operations.

In FIG. 6, 801, 804, 805 are adders;
02, 803 is a TRF processing circuit; 806 is a selector that performs an operation equivalent to 506, 507, and 508 in FIG. 3 above;
807 is a vertical center of gravity position conversion processing unit.

Next, the operation of the circuit shown in FIG. 6 will be explained.

The de-emphasis processing unit 1 obtained from the input terminal 501
The output signal of 05 is input to the vertical delay processing section 704.

From the vertical delay processing unit 704, A3 shown in FIG.
When the scanning lines of Al, A2 . A3 is obtained.

In this processing system, TRF processing circuits 703, 702.
701 to the vertical center of gravity position conversion processing unit 807, and output from the vertical center of gravity position conversion processing unit 807 to the output terminal 519, the signal is input to the vertical center of gravity position conversion processing unit 807 via 200 as in FIG.
This is a signal output of 1125/30 corresponding to the scanning line at the center of gravity of the scanning line corresponding to EDTV in M mode and WIDE mode.

The 1125/30 output signals in FIGS. 3 and 5 above are all 1125/30 using the scanning line at the center of gravity of one of the 525/60 (compatible with HDTV) output signals.
/30 interlace output signal is obtained, but since the output signal was originally subjected to vertical filter processing (vertical center of gravity position conversion processing) for 525/60 (compatible with HDTV), the vertical passband Not getting enough, 112
It is difficult to obtain sufficient vertical resolution when reproducing a 5/30 signal. Further, in the color difference signal, when transmitting a still image, a high frequency component in the horizontal direction is folded back into a low frequency component in the horizontal direction and a high frequency component in the vertical direction.

For this reason, it is better not to widen the vertical pass band of the color difference signal. Therefore, in the configuration example of this circuit, 112
New TRF processing circuits 802 and 803 and adders 801 and 804 are provided for creating a 5/30 luminance signal.

Adder 801 adds scanning lines A1 and A3 obtained from the vertical delay processing section and inputs the sum to TRF processing circuit 803. T
The RF processing circuit 802 processes the scanning line A2 obtained from the vertical delay processing section, and the TRF processing circuit 803 processes the scanning line A2 obtained from the vertical delay processing section.
Horizontal pixel interpolation and horizontal pass band limitation are performed on the outputs obtained from 01, respectively. And adder 80
4 adds the outputs of the TRF processing circuits 802 and 803, and adds the outputs of the TRF processing circuits 802 and 803 to the adder 801 and the TRF processing circuits 802 and 803.
and adder 804 constitute a two-dimensional filter within the field. At this time, the TRF processing circuit 802.80
A Knob coefficient of 3 is selected to widen the vertical passband.

On the other hand, the adder 805 adds the output signals of the adders 509 and 510, and outputs a signal 2 (A (- 1) +4(AI)+2(A3
)) I got /8. The selector 806 selects and outputs the luminance signal obtained from the adder 804 and the color difference signal obtained from the adder 805 in accordance with the control signal obtained from the control signal input terminal 508 and inputs it to the output terminal 520.

After performing the above processing, a 1125/30 scanning line with the same vertical resolution as above is created and outputted to the output terminal 520 for the luminance signal.

According to the configuration shown in FIG. 6, compared to the configuration shown in FIG.
Although the number of logic units such as TRF processing circuits in the intra-field interpolation processing unit increases, the 200M mode and WID
It is possible to simultaneously obtain a scanning line output at the scan line gravity center position for an E-mode EDTV compatible display and a scanning line output for a high definition television compatible display with improved vertical resolution during brightness signal reproduction.

FIG. 7 shows the intra-field interpolation processing circuit 4 in FIG.
FIG. 2 is a block diagram showing yet another example of the configuration of 01. 7th
In the figures, the same reference numerals as those in FIGS. 1, 3, 5, and 6 perform the same operations.

In FIG. 7, 901 is 701°702. in FIG.
A TRF processing circuit 902 having the same configuration as 703 is a vertical center of gravity position conversion processing section.

Next, the operation of the circuit shown in FIG. 7 will be explained using FIG. FIG. 8 is an explanatory diagram of the principle of signal processing operation in the circuit of FIG. 7.

In FIG. 7, when the scanning line A3 shown in FIG. 4 arrives from the vertical delay processing unit 704 as described above,
l, A2, and A3 are obtained.

First, let's take a look at the 1125/30 output system of the output terminal 520.

The output for 1125/30 in this processing system is equivalent to that shown in Figure 6 for the luminance signal, but for the color difference signal, processing equivalent to the luminance signal processing in Figure 6 above is performed. When transmitting still images, the vertical passband is widened. Therefore, in this circuit configuration, when a still image is transmitted, the 1125/30 color difference signal reproduction output contains slightly more aliasing components than in the configuration shown in FIG. However, compared to the luminance signal, the color difference signal is
Considering that there is little effect on the human eye during image reproduction, this is not a major problem.

Next, let's take a look at the 525/60 EDTV compatible output system. This configuration has a configuration in which the order of the TRF processing circuit and the vertical center of gravity position conversion processing section is changed compared to the configuration shown in FIG. The fact that this process is possible in principle will be explained with reference to FIG.

Figure 8 shows the output signal when the vertical center of gravity position conversion process is performed after performing the TRF process and the output signal after performing the vertical center of gravity position conversion process when the tap coefficients of N TRF processing circuits are equal. FIG. 4 is a principle diagram for explaining that output signals become equal when TRF processing is performed.

In FIG. 8, (a) shows the case where vertical center of gravity position conversion processing is performed after TRF processing, and (b)
) is the TRF after performing vertical center of gravity position conversion processing.
This shows the case where processing has been performed. Here, to simplify the explanation, the tap coefficients of the TRF processing section are assumed to be five, and they are set as 1, 1, 2, and 1.1 in order from the input side, and the coefficient in the vertical direction is assumed to be 1.2. .1.

In FIG. 8, (C) shows the internal configuration of the TRF processing circuit used to explain the principle, and (d) shows the internal configuration of the vertical center of gravity position conversion processing section used to explain the principle.

In FIG. 8(a), the output signal at time t shown in the figure corresponds to finding the pixel at the position S (☆) in the figure,
When calculated according to the coefficients shown in the figure, S(☆)=((a
+c)+2 b) + (b'+c')+((a"+C
″)+2b″) ・−・・・・(1) In Fig. 8(b), the output signal at time t shown in the figure corresponds to finding the pixel at the position M(·) in the figure. , when calculated according to the coefficients shown in the figure, M(・) - (a + (2 - (a + (C + a") + (2b' + 2 (b + b ")) c' + c + c"
) +a″)+2(b+b’tenb”) +2(’+(,”) ・・・・・・(
2).

Here, if we transform (1) 2 above and combine them into a, b, and c, we get S(☆)-(a+a")+2(b+b'+b")+(
c+2 c'+('') In other words, S(☆)-M(.) It can be seen that even if the order of the TRF processing and the vertical center of gravity position conversion processing is changed, the output signals match.

This is not limited to the case of the above-mentioned tap coefficients; boat fishing has non-linear components as shown in the TRF processing circuit in Figure 8 (C) and the vertical center of gravity position conversion processing section (d). If not, if the tap coefficients of the TRF processing circuits are equal, the output signal when vertical center of gravity position conversion processing is performed after performing TRF processing, and the output signal when TRF processing is performed after performing vertical center of gravity position conversion processing. The output signals in the case are equal.

From the above explanation, it can be seen that in FIG. 7, the same output signal as that obtained in FIG. 6 can be obtained at the output terminal 519. Here, the tap coefficients of the actual TRF processing section have a large number of digits after the decimal point (this affects the filter characteristics of the two-dimensional filter, so the data bit width after TRF processing is usually the bit width of the input signal. Therefore, in an actual circuit, the circuit scale of the vertical center of gravity position conversion processing section when using the configuration shown in FIG. 7 is larger than that of the configuration shown in FIG. It is possible to make the circuit scale much smaller than the circuit scale of the vertical center of gravity position conversion processing section when using this method.

According to the configuration shown in FIG. 7, compared to the configuration shown in FIG.
The circuit size of the TRF processing circuit in the intra-field interpolation processing section has been reduced to 1/3, and in addition, the circuit size of the vertical center of gravity position conversion processing section has been significantly reduced. A scanning line output at the scanning line gravity center position and a scanning line output for a display compatible with high-definition television can be obtained simultaneously.

FIG. 9 shows the in-field signal processing circuit 1 in FIG.
It is a Pronk diagram showing another specific example of.

In FIG. 9, the same reference numerals as in FIG. 1 above perform the same operations.

1001 is an output signal input terminal of the de-emphasis processing unit 105, 1101 is a 1125/30 output color signal processing circuit, and 1102 is a 525/30 output color signal processing circuit for the luminance signal and color difference signal.
60, the speed conversion processing circuit 1103 is 525
/60 output color difference signal processing circuit, 1002, 1003
．． 1004 is a 1125/30 output terminal, 1005,1
006°1007 is the 525/60 output terminal, 1008
1009.1010 are 525/30 output terminals.

In FIG. 9, the in-field signal processing circuit 1 of FIG.
The only different components are a color difference signal processing circuit 1101, a speed conversion processing circuit 1102, and a color difference signal processing circuit 1103. These configurations will be explained below with emphasis on FIGS. 10 and 11.

In FIG. 9, the 1125/30 scanning line output created by the intra-field interpolation processing circuit 401 is input to the color difference signal processing circuit 1101. In the intra-field interpolation processing circuit 401, the color difference signal is still a signal whose band has been compressed in the horizontal/vertical directions and the time axis direction. FIG. 10 shows the internal configuration of the color difference signal processing section that returns this signal to the original signal.

In FIG. 10, 1201 is a scanning line signal input terminal for 1125/30, 1202 is a time axis expansion section, 1203 is a line sequential processing section, 1204 is a color difference interpolation processing section, 1205.
1206 is (RY), (BY) signal output terminal, 12
07.1208 is a color difference signal output terminal for 1125/30.

The color difference signal inputted from the intra-field interpolation processing circuit 401 is inputted from the input terminal 1201, and is inputted to the time axis expansion unit 1.
At 202, the time axis is expanded by reading out the color difference signal whose time axis has been compressed to 1/4 with respect to the luminance signal using a memory at a clock rate of 1/4 of the luminance signal.
Align the luminance signal and the horizontal time axis.

Next, the line sequential processing unit 1203 performs line sequential processing (vertical line interpolation), and for each line (RY),
(B-Y) Create a signal and output terminal 1205.120
6 and output to the color difference interpolation processing unit 1204. The above (RY) and (B-
Y) signal is supplied to the speed conversion processing circuit 1102. In addition, the color difference interpolation processing unit 1204 processes the above (RY), (
By performing pixel interpolation in the horizontal direction on the B-Y) signal,
Output to output terminals 1207 and 1208.

The color difference signals outputted to the output terminals 1207 and 1208 have a blanking period inserted in the blanking insertion circuit 124, and are outputted to the output terminals 1003 and 1004. 11 above
The (R-Y) and (B-Y) signals obtained from the 25/30 color difference signal processing circuit 1101 before being subjected to interpolation processing and at a data rate 1/4 times that of the luminance signal, The luminance signal obtained from the intra-field interpolation processing section 401 is input to the speed conversion processing circuit 1102. The internal configuration of this speed conversion processing circuit 1 02 will be explained using FIG. 11.

In FIG. 11, the same reference numerals as in FIGS. 9 and 10 perform the same operations.

1301 is the above luminance signal input terminal, 1302゜1305
1303 is the speed conversion memory section, and 525/1303 is the luminance signal.
60 EDTV compatible output terminal, 1304 is a multiplexing unit that multiplexes color difference signals, 1306 is a separation processing unit that separates color difference signals that have been subjected to speed conversion processing while being multiplexed, and 1307 and 1308 are 525/6
0 This is an output terminal for EDT ■ compatible output.

The luminance signal is speed-converted from 1125/30 to 525/60 EDTV compatible output by a speed conversion memory unit 1302 and is supplied to an output terminal 1303. Also,
As described above, the color difference signal supplied to the speed conversion processing circuit 1102 has a data rate 1/4 times that of the luminance signal.

Therefore, in the multiprocessing unit 1304, the input terminal 121
(RY) and ( after line sequential processing obtained from 6.1217
For the B-Y) signal, the upper bit and lower b
It selects and outputs a total of four input signals to multiplex color difference signals and quadruple the data rate. As a result, the color difference signal has the same data rate as the luminance signal, and it becomes possible to control the speed conversion memory section of the color difference signal using the same clock and control signal as the luminance signal.

Next, the color difference signal is converted from 1125/30 to 525/60 by the speed conversion memory unit 1305 while being subjected to multiple processing.
Speed conversion to EDTV compatible output. Separation processing unit 130
6, performs the inverse of the above multiprocessing and outputs the output terminal 1.
Supply to 307.1308.

After performing the above signal processing, a blanking period is inserted in the blanking insertion circuit 125 for the luminance signal, and then outputted to the output terminal 1005 and the speed conversion circuit 111. Regarding the color difference signal, the color difference signal processing circuit 1
In step 103, only interpolation processing is performed, pixel interpolation in the horizontal direction is performed, and after a blanking period is inserted in a blanking insertion circuit 125, the data is output to output terminals 1006 and 1007 and the speed conversion circuit 111.

According to the configuration shown in FIG. 9, compared to the configuration shown in the in-field signal processing circuit in FIG. 1, most of the circuitry of the color difference signal processing section is shared, so the built-in memory capacity is three lines worth. The memory capacity of the color difference signal processing section can be reduced to 1/2 for the entire system.

Next, the control signal generation circuit 104, which is the main circuit in the configuration shown in FIG. 1, will be explained.

FIG. 12 is a diagram showing the inside of the control signal generating section 104 that extracts a synchronization signal and a control signal from the incoming MUSE signal and also generates a system clock and the like.

In FIG. 12, 301 is an input terminal for the MUSE signal converted into a digital signal by the A/D converter 103;
307 has two display forms (200M) in the 525/60 and 525/30 series.

WIDE) switching control (mode switching) signal input terminal. 303 is a phase-locked loop circuit (
(hereinafter referred to as PLL) (1), 302 is the input terminal 30
The output signal from PLL (1) and the output signal from PLL (1) are input, and the control signal of the 1125/30 system and the 525
1125, system timing generation circuit, 304, 305 supplying clock to PLL of /60,525/30 system,
PLL (2), PLL (3), and 306 are PLLs that reproduce clocks corresponding to two display formats (ZOOM, WIDE) of the 525/60 and 525/30 series, respectively.
(2), according to the clock from PLL (3) and the mode switching control signal from the control signal input terminal 307, the 525/
525 series timing generation circuit that supplies control signals and clocks for 60,525/30 series systems, 308 is 11
The 25 system timing output terminal 309 is a 525 system timing output terminal. The operation of FIG. 12 will be explained below.

In FIG. 12, the MUSE signal converted into a digital signal by the A/D converter 103 in FIG.
The signal is input to the timing generation circuit 302 of the system.

First, in P L L (1), 3
A 2.4 MHz clock is generated and input to the 1125 system timing generation circuit 302. The 1125 system timing generation circuit 302 generates various synchronization signals and control signals, and in FIG.
The signal is supplied to the /D converter 103 , de-emphasis 105 , field interpolation processing circuit 401 , color difference signal processing section 107 , blanking insertion circuit 124 , D/A converter 1403 , and speed conversion circuit 109 .

Further, in FIG. 9, the signal is supplied to a color difference signal processing circuit 1101 and a speed conversion processing circuit 1102 which operate in synchronization with 1125. These signals are output to the 1125 system timing output terminal 308.

Furthermore, a 32.4 MHz clock is supplied to PLL (2) 304 and PLL (3) 305. P L L (
2) In 304, 32 obtained from the above PLL (1) 303
．． Generates a WIDE clock synchronized with a 4MHz clock. However, the WIDE clock referred to here is a clock that can display almost all of the pixels included in one line in the 1125/30 system within the video period in one line in the 525/60 system. frequency.

PLL (3) 305 generates a 700M clock synchronized with the 32.4 MHz clock obtained from PLL (1) 303. However, the clock for Z00'M referred to here is 525
This is the frequency that can be displayed within the video period of one line in the /60 system. That is, the clock generated by PLL (3) 305 has a frequency approximately 3/4 times that of the clock generated by PLL (2) 304 (or may be exactly 3/4 times as high).

The 525-system timing generation circuit 306 is connected to the PLL (2
) 304, the clock generated by PLL (3) 305, and the control signals obtained from the two display formats (ZOOM, WIDE) switching control signal input terminal 307. Output from 309.

In FIG. 1, the circuits that operate in 525 synchronization are the speed conversion circuit 109, the color difference signal processing section 110, the blanking insertion circuit 125, the speed conversion processing circuit 111, and the D/A converter 1404. are a speed conversion processing circuit 1102 and a color difference signal processing circuit 1103.

As shown in FIG. 12 above, the system of the present invention has 1125/
30 series (■) and furthermore, 525/60゜525/30
The system has two display formats, 700M (■) and WIDE (■), and in order to control a total of three systems, PLLs corresponding to each are provided.

As above, HDTV signal and NTSC signal or ED
The configuration of the receiver capable of selectively outputting a TV signal and an NTSC signal has been described. The embodiments shown in FIG. 1 have been described as outputting the output signal in the form of Y, (RY) (B - Y), but an RGB matrix circuit is added to the output section to output the RGB output. It is also possible to take the form of

Next, another embodiment of the present invention will be described with reference to FIG. 13.

Fig. 13 takes into account the case where it is possible to output two types of television signals, and in particular, the N.
This is an example in which consideration is given to obtaining the output signal of the TSC at all times.

In FIG. 13, the same reference numerals as those in FIG. 1 perform the same operations. Furthermore, in FIG. 13, 1501 is a selector that inputs and selectively outputs the HDTV output signal and EDTV output signal of the in-field signal processing circuit 1; 1502 is a D/A converter; 1502 is a D/A converter;
503.1504 1505 is D/A converter 1502
This is the output terminal of

In FIG. 13, the selector 1501 receives the 1125/30 scanning line signal from the intra-field signal processing circuit 1 on the a side, and the 525/60 scanning line signal on the b side. The selector 1501 switches the selection input to a or b depending on the display used. If the display to be used is a high-definition television display with a horizontal aspect ratio of 16:9, the output signal of the selector 1501 is set to the a side. As a result, the selector 1501 selects the 1125/30 scanning line signal,
The D/A converter 1502 converts it into an analog signal, and the output terminals 1503, 1504 and 1505 output the signal 1125/1125.
30 luminance signals and (RY) and (BY) color difference signals are obtained.

Next, if the display to be used is a double-speed scanning display with an aspect ratio of 4=3, selector 1501
Let the output signal be the b side. As a result, the selector 1501
selects the 525/60 scanning line signal, converts it to an analog signal at the D/A converter 1502, and outputs it to the output terminal 150.
A luminance signal of 525/60 and a color difference signal of (R-YL (B-Y)) are obtained at 3,1504° 1505.

Here, when using any of the above displays, NTSC output is obtained at the output terminals 121, 122, and 123, and if an NTSC S encoder is newly added to this, separate inputs can be obtained. Output signals compatible with other VTRs can also be easily obtained.

According to the configuration shown in FIG. 13, the number of selectors is halved compared to the configuration shown in FIG. 1, and while the circuit size is reduced, the output signal ( NTSC signal) can be obtained. In other words, even if you are viewing high-definition television signals using any of the above-mentioned displays, the VT
It is possible to record on R.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 14 shows an example in which a case where one type of television signal can be output is considered. In FIG. 14, the same reference numerals as those in FIG. 1 perform the same operations. Further, in FIG. 14, 1601 is a selector that inputs all the output signals of the intra-field signal processing circuit 1 and selectively outputs the signals, and 1602 is a D
/A converters 1603, 1604, and 1605 are output terminals of the D/A converter 1602.

In FIG. 14, the selector 1601 receives the 1125/30 scanning line signal from the intra-field signal processing circuit 1 on the a side, the 525/60 scanning line signal on the b side, and the 525/30 scanning line signal on the b side.
The scanning line signals for each are input to the C side. The selector 1601 switches the selection input to a, b, or C depending on the display used.

If the display you are using is a high-definition television display with a 16:9 aspect ratio,
The output signal of the selector 1601 is set to the a side. This results in
The selector 1601 selects the 1125/30 scanning line signal, converts it into an analog signal in the D/A converter 1602, and outputs the 1125/30 scanning line signal to the output terminals 1603, 1604, and 1605.
A luminance signal of 5/30 and a color difference signal of (R-YL (B-Y)) are obtained.

Next, if the display to be used is a double-speed scanning display with an aspect ratio of 423, selector 1601
Let the output signal be the b side. As a result, the selector 1601
selects the 525/60 scanning line signal, converts it to an analog signal at the D/A converter 16o2, and outputs it to the output terminal 160.
At 3,1604° and 1605, a 525/60 luminance signal and (RY) and (B-Y) color difference signals are obtained.

Additionally, if the display you are using is a standard speed display with a 4:3 aspect ratio, selector 1
601 output signal C side. As a result, the selector 16
01 selects the 525/30 scanning line signal, converts it to an analog signal in the D/A converter 1602, and outputs it to the output terminal 1.
603, 1604, and 1605, a 525/30 luminance signal and (RY), (B-Y) color difference signals are obtained.

Here, if a standard speed display with an aspect ratio of 4:3 is used as the above display, the output terminal! 603, 1604, and 1605 have an NTSC output, and by adding an NTSC S encoder to these, it is possible to easily obtain an output signal compatible with a VTR having separate inputs.

According to the configuration shown in FIG. 14, the number of selectors is halved compared to the configuration shown in FIG. 1, and an output signal compatible with HDTV, EDTV, and NTSC is obtained while reducing the circuit scale. In addition, the VTR can obtain output signals that can be recorded and reproduced if the same television system is used.

As described above, according to this embodiment, at the time of commercialization,
Effective use of memory, reduction of the number of output pins when integrated into an LSI, etc. can be realized.

〔Effect of the invention〕

According to the present invention, an inexpensive high-definition television signal reception, processing, and An advantage is that a selective output device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example of a high-definition television signal processing circuit, and FIG. 3 is the configuration of the intra-field interpolation processing section in FIG. 1. A block diagram showing an example, FIG. 4 is an explanatory diagram showing the operating principle of the vertical center of gravity position conversion processing section in the intra-field interpolation processing section in FIG. 3, and FIG. FIG. 6 is a block diagram showing still another example of the configuration of the intra-field interpolation processing section in FIG. 1, and FIG. A block diagram showing yet another example of the configuration; FIG. 8 is an explanatory diagram showing the principle of the signal processing operation in FIG. 7;
FIG. 9 is a block diagram showing another specific example of the intra-field signal processing section in FIG. 1, and FIG.
A block diagram showing an example of the configuration of a color difference signal processing unit for 125/30 output.
FIG. 12 is a block diagram showing an example of the configuration of the speed conversion processing unit for output creation, FIG. 12 is a block diagram showing an example of the configuration of the control signal generation unit in FIG. 1, and FIG. FIG. 14 is a block diagram showing yet another embodiment of the present invention. Explanation of symbols 1...In-field signal processing unit, 101...MUS
E signal input terminal, 102... demodulation circuit, 103...
A/D conversion section, 104... control signal generation section,
105... De-emphasis processing unit, 401... Intra-field interpolation processing circuit, 107... Color difference signal processing circuit, 109... Speed conversion processing circuit, 110... Color difference signal processing circuit, 111...・Speed conversion processing circuit, 124
... Blanking insertion circuit, 125 ... Blanking insertion circuit, 1401.1402 ... Selector, 140
3.1404...D/A conversion section, 1405, 1406
．． 1407.140B, 1409.1410... Output terminal agent Patent attorney Akio Namiki (C) TRF's A row! ] ] (b) 5 kings of the month! Iri Part 2 (Vertical processing-TRF) (d) Vertical 1. ! Processing Iku no υ month

Claims (1)

[Claims] 1. By receiving and processing a high-definition television signal, a video signal adopting a high-definition television system (hereinafter referred to as an HDTV system) and a double-speed television system (hereinafter referred to as an EDTV system) can be generated. ) and a video signal adopting the standard speed scanning television system (hereinafter referred to as the NTSC system), and receiving a high-definition television signal by selecting and outputting any one of them; The processing and selection output device includes demodulation means (102) for demodulating the received analog high-definition television signal, and A/D conversion means (103) for converting the demodulated output from the demodulation means from an analog signal to a digital signal. and synchronization signal reproducing means (104) which receives the digital signal from the A/D conversion means and extracts and reproduces control signals such as clock signals and synchronization signals for signal processing.
Then, using the control signal from the synchronization signal reproducing means, intra-field signal processing is performed on the digital high-definition television signal that is the demodulated output from the demodulating means, and H
an in-field signal processing means (1) for outputting in parallel a digital video signal adopting the DTV system, a digital video signal adopting the EDTV system, and a digital video signal adopting the NTSC system; Digital video signals of three NTSC formats are input, and a combination of a digital video signal of the HDTV format and a digital video signal of the NTSC format, or a combination of a digital video signal of the EDTV format and a digital video signal of the NTSC format. selection means (1401, 140) for selecting and outputting a combination with a signal;
2), and first and second D/A conversion means (1403, 1
404) A high-definition television signal reception, processing, and selection output device characterized by comprising: 2. By receiving and processing a high-definition television signal, it is possible to create a video signal that uses the high-definition television system (hereinafter referred to as the HDTV system) and a video signal that uses the double-speed television system (hereinafter referred to as the EDTV system). , a standard speed scan television system (hereinafter referred to as NTSC system), and a high-definition television signal reception, processing, and selection output device that selects and outputs any one of them. , a demodulation means (102) for demodulating the received analog high-definition television signal, an A/D conversion means (103) for converting the demodulated output from the demodulation means from an analog signal to a digital signal, and the A/D conversion means (103) for converting the demodulated output from the demodulation means from an analog signal to a digital signal. Synchronous signal reproducing means (104) which receives the digital signal from the converting means and extracts and reproduces control signals such as clock signals and synchronizing signals for signal processing.
Then, using the control signal from the synchronization signal reproducing means, intra-field signal processing is performed on the digital high-definition television signal that is the demodulated output from the demodulating means, and H
an in-field signal processing means (1) for outputting in parallel a digital video signal adopting the DTV system, a digital video signal adopting the EDTV system, and a digital video signal adopting the NTSC system; HDTV system and EDT of the three NTSC systems
a selection means (1501) which receives a V-system digital video signal and selects and outputs one of them; and a first part which converts the digital video signal selected by the selection means (1501) into an analog signal and outputs it. D/A conversion means (1502), and the in-field signal processing means (1).
a second D/A conversion means (which converts the NTSC digital video signal from the
114) A high-definition television signal reception, processing, and selection output device characterized by comprising: 3. By receiving and processing a high-definition television signal, it is possible to create a video signal that uses the high-definition television system (hereinafter referred to as the HDTV system) and a video signal that uses the double-speed television system (hereinafter referred to as the EDTV system). , a standard speed scan television system (hereinafter referred to as NTSC system), and a high-definition television signal reception, processing, and selection output device that selects and outputs any one of them. , a demodulation means (102) for demodulating the received analog high-definition television signal, an A/D conversion means (103) for converting the demodulated output from the demodulation means from an analog signal to a digital signal, and the A/D conversion means (103) for converting the demodulated output from the demodulation means from an analog signal to a digital signal. Synchronous signal reproducing means (104) which receives the digital signal from the converting means and extracts and reproduces control signals such as clock signals and synchronizing signals for signal processing.
Then, using the control signal from the synchronization signal reproducing means, intra-field signal processing is performed on the digital high-definition television signal that is the demodulated output from the demodulating means, and H
an in-field signal processing means (1) for outputting in parallel a digital video signal adopting the DTV system, a digital video signal adopting the EDTV system, and a digital video signal adopting the NTSC system; A selection means (which receives digital video signals of three NTSC formats and selects and outputs any one of them)
1601); and D/A conversion means (1602) for converting the digital video signal selected by the selection means (1601) into an analog signal and outputting the analog signal. Signal reception, processing, and selection output device. 4. The high-definition television signal reception, processing and selection output device according to claim 1, 2 or 3, wherein the intra-field signal processing means (1) is configured to generate a digital signal which is a demodulated output from the demodulation means. A high-definition television signal is input, and a line memory that delays the television signal is used to generate a digital video signal with the number of scanning lines according to the HDTV method and a digital video signal with the number of scanning lines matching the center of gravity of the scanning line according to the EDTV method. , an intra-field interpolation processing means (401) that generates and outputs by intra-field interpolation processing using the control signal from the synchronization signal reproduction means, and an HDT from the intra-field interpolation processing means (401).
A first method that performs time-axis expansion processing, line-sequential processing, and interpolation processing on the color-difference signal in the digital video signal with the number of scanning lines according to the V method, which is compressed and multiplexed in the time-axis, and outputs the resultant EDT as output from the color difference signal processing means (107) and the intra-field interpolation processing means (401)
The digital video signal of the scanning line that matches the scanning line gravity center position according to the V method is input, and the number of scanning lines and the scanning speed are
A first speed converting means (109) converts the DTV system into that according to the EDTV system and outputs the same, and the color difference signal outputted from the first speed converting means (109) is compressed and multiplexed on the time axis. a second color difference signal processing means (110) that performs line-sequential processing and interpolation processing on the color difference signal and outputs the same; a luminance signal as an output of the first speed conversion means (109); Color difference signal processing means (1
10), a second speed converting means (111) that receives the color difference signal from the NTSC system, converts the number of scanning lines and the scanning speed into the NTSC system, and outputs the converted signal. Signal reception, processing, and selection output device. 5. The high-definition television signal reception, processing, and selection output device according to claim 1, 2, or 3, wherein the in-field signal processing means (1) is configured to generate a digital signal that is a demodulated output from the demodulation means. A high-definition television signal is input, and a line memory that delays the television signal is used to generate a digital video signal with the number of scanning lines according to the HDTV method and a digital video signal with the number of scanning lines matching the center of gravity of the scanning line according to the EDTV method. , an intra-field interpolation processing means (401) which generates and outputs each by intra-field interpolation processing using a control signal from the synchronized reproduction means; and an HDTV method from the intra-field interpolation processing means (401). First color difference signal processing that performs time axis expansion processing, line sequential processing, and interpolation processing on the color difference signal compressed and multiplexed in the time axis on the color difference signal in the digital video signal of the number of scanning lines, and outputs the resultant processing. means (1101); and a luminance signal as an output from the intra-field interpolation processing means (401) and the first color difference signal processing means (110).
The color difference signals after line-sequential processing (before interpolation processing) from 1) are input, and using separate memories, the number of scanning lines and scanning speed are input to the HDTV system and then to the EDTV.
a first speed converting means (1102) that converts and outputs the converted signal according to a method, and a second speed converting means (1102) that performs an interpolation process on the color difference signal as an output of the first speed converting means (1102) and outputs it. A color difference signal processing means (1103) receives the luminance signal as an output of the first speed conversion means (1102) and the color difference signal from the second color difference signal processing means (1103), and calculates the number of scanning lines. and second speed converting means (111) for converting the scanning speed to that according to the NTSC system and outputting the same. 6. Receiving the high definition television signal according to claim 5;
In the processing and selection output device, the first speed conversion means (1102) processes the color difference signal after line-sequential processing from the first color difference signal processing means (1101) during speed conversion processing of the color difference signal. A multiplex circuit that divides the (RY) signal and (B-Y) signal into upper bits and lower bits, respectively, and selects and outputs a total of four input signals to achieve time axis multiplexing and bit compression. 1304), a speed conversion circuit (1305) that performs speed conversion on the output from the multiplex circuit (1304) and outputs it, and a speed conversion circuit (1305) that performs speed conversion on the output from the multiplex circuit (1304) and outputs the result
A separation circuit (1305) is input, and separates and reproduces the original (R-Y) signal and (B-Y) signal.
306), and a clock used for speed conversion of a luminance signal is used as it is for speed conversion of a color difference signal during speed conversion processing. 7. In the high-definition television signal reception, processing, and selection output device according to claim 4 or 5, the intra-field interpolation processing means (401) performs transversal type (hereinafter, TRF) processing on the input signal. TRF processing means (50
2), vertical delay means (517) for vertically delaying the color difference signal and luminance signal with respect to the output signal from the TRF processing means (502), and the vertical delay means (517).
), the scanning line center of gravity position conversion means ( 51
8) A high-definition television signal reception, processing, and selection output device characterized by comprising: 8. The high-definition television signal reception, processing, and selection output device according to claim 4 or 5, wherein the intra-field interpolation processing means (401) vertically converts the color difference signal and luminance signal, which are the input signals. and a transversal type (hereinafter referred to as TR) for the output signal from the vertical delay means (704).
TRF processing means (701 to 703) that perform horizontal low-pass filter processing of
1 to 703) is input, and then the HD
Digital video signal and ED with the number of scanning lines according to the TV system
Receiving and processing high-definition television signals, characterized by comprising: scanning line gravity center position converting means (518) for creating and outputting a digital video signal of a scanning line that matches the scanning line gravity center position according to the TV system; Combined selection output device. 9. In the high-definition television signal reception, processing, and selection output device according to claim 4 or 5, the intra-field interpolation processing means (401) performs TRF processing.
It has a processing means, a scanning line centroid position conversion processing means (807), and a vertical delay unit (704) that delays the color difference signal and the luminance signal in the vertical direction, and the scanning line centroid position conversion processing means (807) ) is a selector (511) that switches signal processing for each field or according to display mode.
) and an arithmetic circuit that performs arithmetic operations between the output signal and the input signal of the selector, it is possible to create scan lines for vertically compressed display of a screen compatible with EDTV, and to display left and right cuts of a screen compatible with EDTV. It is possible to create scanning lines that can be displayed on a high-definition television display by simply creating a scanning line for the computer and providing a signal processing path that does not pass through the selector (511) in the arithmetic circuit. A high-definition television signal reception, processing, and selection output device characterized by: 10. In the high-definition television signal reception, processing, and selection output device according to claim 8, the TRF processing means in the intra-field interpolation processing means (401) delays the color difference signal and the luminance signal in the vertical direction. The high-definition television signal processing means is characterized in that the output signal obtained from the vertical delay means (704) is provided with TRF processing means having different configurations (tap coefficients) for EDTV and HDTV, respectively. Receiving, processing, and selective output device. 11. In the high-definition television signal reception, processing, and selection output device according to claim 4 or 5, the intra-field interpolation processing means (401) performs vertical compression display (hereinafter referred to as When creating a scanning line for EDTV (hereinafter referred to as WIDE) and a scanning line for left and right cut display of a screen compatible with EDTV (hereinafter referred to as ZOOM), for the output signal obtained from the vertical delay means, TRF that performs scanning line centroid position conversion processing and then performs TRF processing
A high-definition television signal reception, processing, and selection output device characterized by comprising processing means.