JPH04275789A - High definition television signal processor - Google Patents

Abstract

PURPOSE:To remove foldover noise in a static image when relating output from a simple type MUSE down converter to a signal processing circuit with an EDTV system. CONSTITUTION:The processor inputs the image signals 1 (525 lines, 2:1 of an interframe Y/C separation circuit in the EDTV system signal processing circuit, obtains an interporation scanning line in the present field, using a line memory 2 and an adder 5, and further obtains an interporation scanning line in the previous field, using a field memory 3, a line memory 4 and an adder 6. The phases of the inputted image signal of the interporative scanning line in the present field and the one in the preceding field are considered with a selecter 7, and the phases of the inputted signal of the interporative scanning line in the preceding field and the one in the field just before the preceding field are considered with a selecter 8, so that they are mutually changed over with a selection signal 18 and the interporation between and within the scanning lines is performed. The static image signal whose foldover noise is removed is thus obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition television signal processing apparatus for associating MUSE system signals with IDTV system, EDTV system, etc. signals.

0002

2. Description of the Related Art Digital signal processing of video signals is becoming popular as digital ICs advance, especially as memories become faster, larger in capacity, and lower in price. Further, there is a demand for larger screens and higher definition for television receivers. The IDTV method and EDT are methods for increasing the resolution of the screen.
The V method has been developed.

FIGS. 8 and 9 show television signal processing circuits based on the EDTV system. An NTSC signal or an S-terminal input luminance signal is supplied to an input terminal 401 and introduced into an analog/digital (hereinafter referred to as A/D) converter 402 . Further, an S terminal input color difference signal is supplied to the input terminal 403. The S terminal input luminance signal Sy and the S terminal input color difference signal Sc are signals after luminance and color signals have been separated in advance.

A digital signal from the A/D converter 402 is input to a motion detection circuit 405 and an interframe luminance/color separation (hereinafter referred to as Y/C separation) circuit 406. The interframe Y/C separation circuit 406 is connected to the frame memory 40
8, an adder 409 and a subtracter 410; the adder 409 obtains a luminance signal Y, and the subtracter 410 obtains a chrominance signal C. The interframe Y/C separation circuit 406 separates luminance and color signals using interframe signals, and is therefore effective when the input signal is a still image. Further, the digital signal from the A/D converter 402 is supplied to an intra-field Y/C separation circuit 411 which is effective when the input signal is a moving image. That is, the interframe Y/C separation circuit 406 uses the fact that the color subcarrier is inverted for each frame to separate the luminance signal and the color signal in the still part of the image based on the sum and difference between frames.

The luminance signals separated by the Y/C separation circuits 406 and 411 are input to a mixing circuit 413, and the mixing ratio of both signals is controlled in accordance with a motion detection signal from a motion detection circuit 405. Further, the color signals separated by the Y/C separation circuits 406 and 411 are input to the mixing circuit 414, and in this case as well, the mixing ratio of both signals is controlled according to the motion detection signal from the motion detection circuit 405.

Each luminance signal and color signal from mixing circuits 413 and 414 are supplied to one of selectors 415 and 416, respectively. The other of the selectors 415 and 416 is supplied with an S terminal input luminance signal and an S terminal input color signal. Since the S terminal input luminance signal does not need to be subjected to Y/C separation processing, it is directly supplied from the A/D converter 402. In addition, the S terminal input color signal is also input terminal 4.
03, is supplied to the selector 416 via the A/D converter 404.

The luminance signal from the selector 415 is supplied to a motion adaptive progressive scan converter 501, and the chrominance signal from the selector 416 is supplied to a color demodulation double speed converter 502. The motion adaptive progressive scan converter 501 includes a motion detection circuit 511 to which an input luminance signal is supplied, a field memory 512, and a line memory 513. The input and output of the line memory 513 are added by an adder 514, an average value is taken, and the average value is supplied to one of the mixing circuits 515. Also, the mixing circuit 51
5 is supplied with the output of the field memory 512. The mixing ratio of the mixing circuit 515 is controlled according to the motion detection signal from the motion detection circuit 511. The motion detection circuit 511 detects a moving image portion and a still image portion using the difference between one frame or the difference between two frames, and obtains a motion detection signal.

The output of the mixing circuit 515 is stored in a double-speed memory 516.
and is read out at 1/2 the speed of the horizontal scanning period. In addition, the output from the selector 415 is also output from the double-speed memory 51.
7 and is read out at a speed 1/2 of the horizontal scanning period. That is, the signals of double speed memories 516 and 517 are as follows.
The data are read out alternately at a speed 1/2 of the horizontal scanning period. These signals are alternately selected and derived by the selector 518, resulting in 525 1:1 sequential scanning signals.

On the other hand, the color signal from the selector 416 is supplied to a color demodulation circuit 521 and demodulated into two color difference signals. (R
-Y) and (B-Y) signals are each sent to the 1H delay circuit 52.
2,524. Adder 523 adds the input and output of 1H delay circuit 522 and outputs the average value to double speed memory 526. Double speed memory 526 and color demodulation circuit 5
Double speed memory 5 to which the (RY) signal is directly supplied from 21
27 are read out alternately at a speed 1/2 times the horizontal scanning period, and their outputs are alternately selected and derived by the selector 530. Therefore, the number of scanning lines of the (RY) signal is also doubled. (B-Y) The processing system on the signal side is similarly configured, and includes a 1H delay circuit 524 and an adder 5.
25, double-speed memories 528 and 529, and a selector 531.

The luminance signal from the selector 518 and the (RY) and (B-Y) signals from the selectors 530 and 531 are respectively sent to digital/analog (hereinafter referred to as D/A) converters 541, 542, and 543. The signal is converted into an analog signal, and then converted into R, G, and B signals by a matrix circuit 544 and output.

By performing Y/C separation processing and motion adaptive progressive scanning conversion processing in this way, the current system broadcasting signal (
525 lines 2:1 interlace) can be converted into a signal (525 lines 1:1 non-interlace) to achieve high image quality.

On the other hand, a high-definition television system that is completely different from the current system has also been developed. Since this method requires about five times the signal band of the conventional method, the signal band is compressed so that it can be transmitted in the signal band for one broadcasting satellite channel (MUSE (Multiple S
ub-Nyquist Sampling Encod
ing method)). This method performs band compression by performing offset sampling between fields and frames of a high-definition television signal. Therefore, on the receiving side, a MUSE equipped with a large capacity memory such as a frame memory is used.
A decoder is required. However, the MUSE decoder is an extremely complex circuit, requires a large memory capacity, and is expensive. Furthermore, since the signals of the MUSE system are completely different from the signals of the current system, the images cannot be displayed using normal existing television signals. Therefore, MUSE, which simply converts MUSE system signals to the current standard system,
Downconverters are being developed.

FIGS. 10 and 11 show a conventional simple MUSE.
Showing a down converter. The input terminal 701 has M
A USE signal is supplied to an A/D converter 703 via an 8.1 MHz band low pass filter (hereinafter referred to as LPF) 702 . MUSE signal is A/D converter 7
At 03, the signal is converted into a digital signal at a clock rate of 16.2 MHz, and is input to the field interpolation circuit 707 and the 1125-system timing circuit 705 that constitute the simple MUSE processing circuit 704.

The signal from which intra-field interpolation has been removed is TCI (
Time Compressed Integrity
on ) is input to the decoder 708 . The TCI decoder 708 expands the two color signals multiplexed during the horizontal blanking period of the luminance signal on the time axis and outputs the expanded signals. T.C.
The luminance signal Y obtained from the I decoder 708 and the color difference (R-
Y, B-Y) signal is input to an intra-field scanning line converter 709 at the next stage. The scanning line converter 709 includes 112
5 system timing circuit 705 and 525 system timing circuit 7
A timing signal from 06 is supplied. Here, 1125 2:1 interlace signals are used as 525
Processing is performed to convert the signal into a 2:1 interlaced signal. The scan-converted luminance signals Y, (RY) and (
B-Y) are D/A converters 711, 712, 7, respectively.
13, the signal is converted into an analog signal, and then supplied to LPFs 714, 715, and 716 that constitute an NTSC encoder. The output of LPF714 is sent to the synchronous burst addition circuit 7.
18 and also to an adder 719. The outputs of the LPFs 715 and 716 are supplied to a quadrature modulator 717 and converted into a 3.58 MHz carrier color signal, and then supplied to a synchronization burst adding circuit 718 and an adder 7.
19. The adder 719 combines the chrominance signal and the luminance signal, and supplies the resultant signal to the synchronization burst addition circuit 718 . From the synchronous burst addition circuit 718, the adder 7
An NTSC composite video signal obtained by adding a synchronization signal and a burst signal to the output obtained from the LPF 714 can be obtained at the output terminal 723, and an S terminal luminance signal Sy obtained by adding a synchronization signal to the output of the LPF 714 is output to the output terminal 721. An S-terminal chrominance signal Sc obtained by adding a burst signal to the output of the quadrature modulator 717 can be obtained at the output terminal 722. In addition, the scanning line converter 709 has 525 lines 1:
It is also possible to output a signal converted into a non-interlaced signal.

[0015]

[Problem to be solved by the invention] As mentioned above, MU
Since the SE decoder circuit is very complicated and expensive, a simple MUSE down converter as shown in FIGS. 10 and 11 has been developed. Furthermore, on the other hand,
The EDTV system shown in FIGS. 8 and 9 is also being developed to improve the image quality of current television signals. Therefore, simple type M
Output of USE down converter (525 lines 2:1
A conceivable method is to further connect a signal processing circuit (interlace) to an EDTV signal processing circuit. However, simple M
Since the USE down converter performs intra-field interpolation processing for both still images and moving images, there is a problem in the case of still images that aliasing noise occurs between fields and the image quality is significantly degraded.

The present invention has been made to solve the above problems, and an object thereof is to provide a high-detail television signal processing device that can remove aliasing noise in still images.

[0017]

[Means for Solving the Problems] The present invention provides a first interlace-scanned signal from a high-definition television signal, which is band-compressed by offset subsampling that goes around in n fields and has a greater number of scanning lines than the current television signal. A high-definition television signal processing device comprising: a first conversion means for obtaining a television signal; and a second conversion means for obtaining a second television signal sequentially scanned from the first television signal. , a first delay means for delaying the first television signal by one horizontal period; a second delay means for delaying the first television signal by one field; a first addition means for adding the output of the second delay means and the output of the first addition means, and a select signal containing information of the first television signal, which a first signal switching means for selectively outputting the output using the second delay means; a third delay means for delaying the output of the second delay means by one horizontal period; a second addition means for adding the outputs; and a second addition means for adding the outputs of the second addition means and the output of the first delay means, and selectively outputs the output of the second addition means and the output of the first delay means using a selection signal containing phase information of the first television signal. a second signal switching means for detecting the amount of movement of the first television signal;
a first mixing means for mixing and controlling the output of the first signal switching means and the output of the first adding means according to the output of the motion detecting means; a second mixing means for mixing and controlling the output of the first delaying means in accordance with the output of the motion detecting means; a first double-speed memory means for converting the output of the first mixing means into a double-speed converter; a second double-speed memory means for double-speed converting the output of the second mixing means; and a third signal switching means for alternately selecting and outputting the output of the first double-speed memory means and the output of the second double-speed memory means. It is equipped with the following.

[0018]

[Operation] According to the above means, when the output of the simple MUSE down converter is further connected to an EDTV signal processing circuit and used, aliasing between fields included in the still image output of the simple MUSE down converter is removed. be able to.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a high-detail television signal processing apparatus according to the present invention. Simple MUS
In the method of using the output of the E down converter (525 lines 2:1 interlaced) by further connecting it to an EDTV signal processing circuit, A video signal is input to input terminal 1. The video signal includes a luminance signal and a color difference signal, and both signals can be processed in the same way. The input video signal is transmitted through a line memory 2 having a delay time of 1H (H is a horizontal scanning period), a field memory 3 having a delay time of 1 field, and a motion detection circuit 15.
is input. The output of the line memory 2 is added to the input video signal by an adder 5, and the average value output is input to the B terminal of the selector 7. The output of the field memory 3 is input to the A terminal of the selector 7. Further, the output of the field memory 3 is input to the adder 16, and is also input to the adder 16 via the line memory 4 having a delay time of 1H. The adder 16 inputs the average value of the two input signals to the A terminal of the selector 8. The output of the line memory 2 is input to the B terminal of the selector 8. A video signal interpolation method will be described below with reference to FIGS. 2 to 6.

FIG. 2 shows an input video signal, which is obtained by the interframe Y/C separation circuit 406 in the EDTV signal processing circuit, and is an interlaced signal having a sampling rate of, for example, 4 fsc (fsc is the color subcarrier frequency). . In the figure, scanning lines 1 to 3 indicated by solid lines indicate scanning lines of odd fields, and scanning lines 4 to 6 indicated by dotted lines indicate scanning lines of even fields. Hereinafter, the data of the current field is shown as a white circle, and the data of the previous field is shown as a black circle.

[0022] The MUSE method uses M
A USE signal is transmitted, and this signal is received and decoded by a simple MUSE down converter.

Further explanation will be given with reference to FIG. The field offset subsampling phase signal is a signal for determining whether the phase of the first video data of the currently sent field is to the right or to the left of the phase of the video data one field before. , extracted from the control signals allocated within the frame. For example, if data at point A on the solid line in Figure 2 is currently being sent, is the phase of this data to the left of the phase of the video data one field before, as shown in Figure 3(a)? Or it is determined whether it is on the right as shown in FIG. 3(b).

In FIG. 1, the decoded field offset subsampling phase signal 16 and the sampling clock 4fsc are input to an exclusive OR 17,
A select signal 18 is input to the control terminals of selectors 7 and 8. The selectors 7 and 8 switch each input signal using a select signal 18.

FIG. 4 shows the transmitted data shown in FIG. 2 divided into fields. FIG. 4(a) shows the data of the odd field, and FIG. 4(b) shows the data of the even field. In the figure, circles indicate the video data being sent (
The triangular mark indicates the interpolated video data (basic data).
interpolated data). Now, if the video data input to input terminal 1 is at point A (current field, on current line) in Figure 4(a) of an even field, the output of line memory 2 is point B 1H ago, The output of adder 5 is C
It is a point. In addition, the output of the field memory 3 is shown in the same figure (b
), the output of line memory 4 is point E,
The output of adder 6 is point F. Point C and point F are interpolated data and become data on line 6 and line 2, respectively.

FIG. 5 is a diagram for explaining the operation of the selectors 7 and 8. For example, when the select signal 18 is at the "L" level, the selectors 7 and 8 select the A terminal side, and
When the level is "H", the B terminal side is selected. FIG. In (b) of the same figure, (1) is the sampling clock 4fsc, (2) and (4) are the field offset subsampling phase signals 16, and (3) and (5) are the respective (1) (2) and the select signal 18 obtained by exclusive ORing (1) and (4).

Now, the field offset subsampling phase signal 16 of the current field (odd field) is “
In the case of "L" level, this means that the sample point of the current field is to the left of the sample point of the previous field, and the video signal of FIG.
b) Using the select signal 18 of (3), the selector 7,
The video signal is switched at 8 and becomes the video signal shown in FIG. 8(c).

Further, when the field offset subsampling phase signal 16 is at the "H" level, this means that the sample point of the current field is to the right of the sample point of the previous field, as shown in FIG. (a
) is the select signal 18 in (b)-(5) of the same figure.
is switched by the selectors 7 and 8, resulting in the video signal shown in FIG. 3(d).

Since the input video signal is an interlaced signal, the output of the selector 7 is a video signal interpolated on the untransmitted scanning line between the upper and lower scanning lines subjected to interlaced scanning. The output of the selector 8 is a video signal interpolated on non-sample points on the scanning line of the current field.

If the video signal input to the input terminal 1 is a complete still image, it can be used as information on the location where the video data of one field before is to be interpolated. However, in the case of a moving image, since the image moves between the first field and the next field, if video data from one field before is used, it overlaps with the image of the current field, resulting in a double image and blurring. Therefore, in the case of a moving image, only the processing within the current field is performed.

For the reasons mentioned above, in the case of still images, selector 7
, 8 are used as interpolated values. For videos,
The output of the adder 5 is used when interpolating data on scanning lines that are not transmitted due to interlaced scanning. In other words, in FIG. 4, when data at point A on the solid line is sent, the output of the adder 5 becomes point C, and the data at point C is used as the interpolated value, and the interpolated value at point H is also Point data is used as is. Furthermore, when interpolating video data to non-sample points on the scanning line of the current field, the output of the line memory 2 is used. That is, in the same way, the output of the line memory 2 becomes point B, and the data at point B is used as an interpolated value, and the data at point B is used as is for the interpolated value at point G.

The still image output of the selector 7 and the moving image output of the adder 5 are input to the mixing circuit 9, and the still image output of the selector 8 and the moving image output of the line memory 2 are input to the mixing circuit 10, and each control A motion detection signal from a motion detection circuit 15 is input to the end. The motion detection circuit 15 detects a moving image portion and a still image portion using the difference between frames or the difference between two frames, and the mixing circuits 9 and 10 perform mixing control according to the motion detection signal.

The outputs of the mixing circuits 9 and 10 are input to double-speed memories 11 and 12, respectively, into which video data is written at a clock rate of 8 fsc and read out at twice the clock rate of 16 fsc. That is, the output data of the double-speed memories 11 and 12 is read out at a speed 1/2 of 1H (twice the writing speed).

The double-speed memories 11 and 12 alternately select two signals and output them to the selector 13. Here, when the current field is an odd field (on the solid line in FIG. 5(a)), the output of the double-speed memory 11 is the data on the line that is not sent due to interlace scanning (as shown in FIG. 5(c) and (d)). (on the dotted line). The output of the double-speed memory 12 is data on a line obtained by interpolating non-sample points of the current field (Fig. 5(c),
(on the solid line in (d)).

FIG. 6 shows the mixing circuits 9 and 10 and the selector 13.
This shows the state of the data. For example, line 2 in FIGS. 5(c) and 5(d) where the current field is an odd field,
3 is located as shown in FIG. 6(b), and this is the output of the mixing circuit 10. Further, lines 5 and 6 in FIG. 2 are located as shown in FIG. 6(a), and these are the outputs of the mixing circuit 9. Selector 1
3 switches the two input signals using the select signal 19, selects them alternately, and outputs them in the relationship shown in FIG. 6(c). This select signal 19 is generated so that the lines of the image are not upside down. The output of the selector 13 is converted into an analog signal by the D/A converter 14, resulting in a 525-line 1:1 non-interlaced signal.

FIG. 7 shows another embodiment of the high-detail television signal processing apparatus according to the present invention. In FIG. 7, the processing up to selectors 7 and 8 is the same as in FIG. 1, and the same parts are given the same reference numerals and their explanations will be omitted.

5 from the simple MUSE down converter
At the same time that 25 2:1 interlaced signals are input to input terminal 1, 525 1:1 non-interlaced signals are input to input terminal 101.

The 525 2:1 interlaced signals are processed as explained in FIG. 1, and input from selectors 7 and 8 to double-speed memories 102 and 103, respectively. The double-speed memories 102 and 103 write video data at an interval of 8 fsc and read it out at twice the clock rate of 16 fsc. That is, the video data written in the double-speed memories 102 and 103 is read out at a speed 1/2 of 1H in the same way as in the case of FIG. Each of the read video data is input to the selector 105, and the selector 105 uses the select signal 19 to alternately select two data signals.
25 lines Convert to 1:1 non-interlaced signal.

The output of the selector 105 is input to one end of the mixing circuit 106, and the 525 1:1 non-interlaced signals from the input terminal 101 are input to the other end of the mixing circuit 106. Here, the output of the selector 105 is a still image signal, and the signal of the input terminal 101 is a moving image signal. Since the signal at the input terminal 101 has a higher vertical resolution than the interpolated value of the moving image interpolated in the embodiment shown in FIG. 1, this signal is used as the moving image signal.

The motion detection signal inputted to the control terminal of the mixing circuit 106 is obtained by passing the 525 2:1 interlaced signals of the input terminal 1 through the motion detection circuit 15 and the rate converter 104 in series. The rate converter 104 converts the motion detection signal of the motion detection circuit 15 to a sample rate corresponding to the video signal. For example, the two signals input to the mixing circuit 106 are 525 signals 1:1 16f.
If it is a sc signal, the output of the rate converter 104 is also 525
This is a 1:1 16fsc signal. Mixing circuit 10
6 uses a motion detection signal to control the mixing ratio according to motion. The output of the mixing circuit 106 is converted into an analog signal by the D/A converter 14, resulting in a 525-line 1:1 non-interlaced signal. In addition to this, this invention
Of course, various modifications can be made without departing from the gist of the invention.

[0041]

[Effects of the Invention] As explained above, according to the high-definition television signal processing device according to the present invention, the simple MUSE
When a down converter is connected to an EDTV signal processing circuit for signal processing, it is possible to remove aliasing noise between still image fields by performing interpolation between fields, and also to convert an interlaced signal to a non-interlaced signal. progressive scan conversion can be performed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a high-definition television signal processing device of the present invention.

FIG. 2 is a diagram for explaining a video signal interpolation method.

FIG. 3 is a diagram for explaining a video signal interpolation method.

FIG. 4 is a diagram for explaining a video signal interpolation method.

FIG. 5 is a diagram for explaining a video signal interpolation method.

FIG. 6 is a diagram for explaining a video signal interpolation method.

FIG. 7 is a configuration diagram showing another embodiment of the high-definition television signal processing device of the present invention.

FIG. 8 is a configuration diagram showing a conventional EDTV signal processing circuit.

FIG. 9 is a configuration diagram showing a conventional EDTV signal processing circuit.

FIG. 10 is a configuration diagram showing a conventional simple MUSE down converter.

FIG. 11 is a configuration diagram showing a conventional simple MUSE down converter.

[Explanation of symbols]

2, 4... Line memory, 3... Field memory, 5, 6
... Adder, 7, 8, 13, 105 ... Selector, 11, 1
2,102,103...double speed memory, 9,10,106...
Mixing circuit, 14...D/A converter, 15...Motion detection circuit,
17...Exclusive OR circuit, 104...Rate conversion circuit.

Claims (3)

[Claims] 1. A first method for obtaining a first television signal interlaced from a high-definition television signal which is band-compressed by offset subsampling that goes around in n fields and has a greater number of scanning lines than the current television signal. and a second converting means for obtaining a second television signal sequentially scanned from the first television signal, wherein the first television signal a first delay means that delays the first television signal by one horizontal period; a second delay means that delays the first television signal by one field; and a first delay means that delays the first television signal and the output of the first delay means. a first addition means for adding together; a first addition means for selectively outputting the output of the second delay means and the output of the first addition means using a selection signal containing information of the first television signal; a signal switching means, a third delay means for delaying the output of the second delay means by one horizontal period, and a second delay means for adding the output of the second delay means and the output of the third delay means. an addition means; and a second signal switching means for selectively outputting the output of the second addition means and the output of the first delay means using a selection signal containing phase information of the first television signal. , a motion detecting means for detecting the amount of motion of the first television signal, and mixing control of the output of the first signal switching means and the output of the first adding means according to the output of the motion detecting means. a first mixing means for controlling the mixing of the output of the second signal switching means and the output of the first delay means in accordance with the output of the motion detection means; a first double-speed memory means for double-speed converting the output of the mixing means; a second double-speed memory means for double-speed converting the output of the second mixing means; and third signal switching means for alternately selectively outputting the output of the double-speed memory means. 2. A first television signal that is interlaced scanned from a high-definition television signal that is band-compressed by offset subsampling that goes around in n fields and has a greater number of scanning lines than the current television signal, and a first television signal that is scanned sequentially. a high-definition television signal comprising: a first conversion means for obtaining a second television signal scanned from the first television signal; and a second conversion means for obtaining a third television signal sequentially scanned from the first television signal. In the processing device, a first delay means for delaying the first television signal by one horizontal period, a second delay means for delaying the first television signal by one field, and a first delay means for delaying the first television signal by one field. and an output of the first delay means, and an output of the second delay means and an output of the first addition means including information of the first television signal. a first signal switching means for selectively outputting using a select signal; a third delay means for delaying the output of the second delay means by one horizontal period; a second addition means for adding the output of the second addition means and the output of the first delay means using a selection signal containing phase information of the first television signal; a second signal switching means for selectively outputting the signal, a first double-speed memory means for double-speed converting the output of the first signal switching means, and a second double-speed memory means for double-speed converting the output of the second signal switching means. a memory means; a third signal switching means for alternately selecting and outputting the output of the first double-speed memory means and the output of the second double-speed memory means; and detecting the amount of movement of the first television signal. a rate converting means for converting an output of the motion detecting means into a sample rate corresponding to the output of the third signal switching means and the second television signal, and the third signal switching means. and the second television signal according to the output of the rate converting means. 3. The high-definition television signal processing apparatus according to claim 1, wherein the selection signal is obtained using a field offset subsampling phase signal.