JPH0454063A - Picture reader - Google Patents

Abstract

PURPOSE:To prevent a density level difference between channels from being caused regardless of a type of an original picture by providing a clamp means which processes a signal while leaving a DC component of a point sequential picture signal obtained through photoelectric conversion by a photoelectric conversion means and has a time constant being a multiple of N of a horizontal scanning period H to the reader. CONSTITUTION:A point sequential color signal from which an undesired sampling frequency component is eliminated is inputted to an amplifier 33 and a DC level fluctuation of an analog color signal whose DC level is fluctuated due to a temperature rise in a sensor is eliminated. A feedback clamp circuit consists of a sample-and-hold circuit 34a and a comparison amplifier 34b, an output level of a dark state output section of an analog color signal outputted from the amplifier 33 is detected by the sample-and-hold circuit 34a and compared with a GND (ground) level inputted to an inverting input of the comparison amplifier 34b, the difference is fed back and the dark state output part of the output of the amplifier 33 is fixed to the GND level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device that reads images using a plurality of image sensors.

[Prior Art] Conventionally, as an image sensor used for image reading, an image sensor in which a stripe type color filter is provided on a one-line image sensor and color separation signals are read out point-sequentially in a time-division manner has been known. It is being

For example, when reading an A4 297 mm long document,
Silicon crystal image sensors are suitable for high-speed reading, but due to manufacturing constraints, it is difficult to make a long type on a single chip, and it is difficult to physically arrange multiple silicon crystal image sensors. With this ingenuity, it is configured as a 1-line sensor.

Since the image sensor output signal has a DC voltage (offset voltage) superimposed on it, the DC voltage in the image sensor output signal is removed from the power supply voltage of the signal processing system and the ease of signal processing, and the average voltage of the signal component is The signal is transmitted to the signal processing circuit so that the signal level is zero volts, the dark output part of the image sensor is detected by the clamp circuit only once per horizontal scan, and DC reproduction is performed so that this signal level becomes a predetermined potential. Ta.

[Problems to be Solved by the Invention] However, in the conventional example described above, since the long type image sensor is composed of multiple chips, reflected light leaks from the edges of the cut surface of each chip into the image sensor dark output section. It becomes a change. Since the dark output section is fixed at a predetermined potential by the clamp circuit, the effective image level changes relatively.

Here, if the bright light corresponding to the white of the original image is applied to the part corresponding to the dark output part of the chip with the image sensor (then the density will change in the horizontal scanning direction, and the density level difference will occur between the images corresponding to each chip. There was a drawback that it occurred.

SUMMARY OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide an image reading device in which no difference in density level occurs between channels, regardless of the type of original image.

[Means for Solving the Problems] The present invention provides an image reading device having a photoelectric conversion means for converting an optical signal from a medium having image information into an electrical signal, in which a point obtained by photoelectric conversion by the photoelectric conversion means is provided. It is equipped with an analog signal processing means having a processing means for sequentially processing a signal while leaving a DC component of the image signal, and a clamping means having a time constant N times the horizontal scanning period (H) of the image signal.

It is also possible to provide a clamp pulse selection means that sets the clamp period of the image signal to H by the clamp means when the original image is not read during standby, and sets the clamp period to NXH when the original image is read during copying. .

[Function] In the present invention, in an image reading device that illuminates a medium having image information with an illumination light source and outputs an image signal from a photoelectric conversion means, the signal is read while leaving the DC component of the read dot-sequential video signal. analog signal processing means for processing;
A clamping means included in the analog signal processing means has a time constant N times the horizontal scanning period (H) of the image signal, and when the document image is not being read (standby), the clamping means sets the clamping period of the image signal to H. By providing a clamp pulse selection means that sets the clamp period to NXH when reading an original image (copying), the IH clamp during standby cancels the dark current change due to temperature rise of the photoelectric conversion means, and when copying, the clamp period changes to NXH. Therefore, it is possible to eliminate the influence of level changes due to leakage light to the dark output section of the photoelectric conversion means, and to suppress differences in density levels between channels.

[Embodiment] Hereinafter, an image reading device that is an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a signal processing block of a color image reading device. The original is first irradiated with an exposure lamp, and the reflected light is separated into colors for each image and read by a color reading sensor 6 in the original scanning unit 3, and amplified to a predetermined level by an amplifier circuit (preamplifier) 8. 7 provides a pulse signal for driving the color reading sensor; C;
It is a CD driver, and the necessary pulse source is generated by the system control pulse generator 16.

Figures 2(a) and 2(b) show the color reading sensor and drive pulses. Here, FIG. 2(a) shows the color reading sensor used in this embodiment. In order to read the main scanning direction divided into 5 parts, each pixel is 63.5 μm, and 96060 pixels, that is, 1 pixel is It is divided into three parts in the scanning direction by B, G, and R, so the total number is 96.
It has an effective number of pixels of 0 x 3 =2880. on the other hand,
Each chip 18 to 22 is formed on the same ceramic substrate, and the 1st, 3rd, and 5th sensors (18, 20, 22) are on the same line LA, and the 2nd and 4th sensors (19, 21) are on the same line LA. line (63.5um x 4 = 252μl11
) on the line LB, and is scanned in the direction of the arrow AL force when reading a document.

In each of the five CCDs, l, 3.5th drive pulse group 0DRV501, 2.4th drive pulse group EDRV502 i
, mJ: are driven independently and synchronously. 0
60φIA, 0φ2A included in DRV501, EφIA, Eφ2A, E included in OR3 and EDRV502
RS is a charge transfer lock and a charge reset pulse within each sensor, and due to mutual interference and noise limitations between the 1st, 3.5th and 2nd and 4th sensors, they are completely synchronized with each other to avoid jitter. generated. For this reason, these pulses are generated from one reference oscillation source 05C17 (see FIG. 1).

FIG. 3(a) shows 0DRV501. The circuit block diagram for generating the EDRV 502, FIG. 3(b) is its timing chart, and is included in the system control pulse generator 16 shown in FIG. φ5 is a clock obtained by dividing the original clock CLKφ generated from a single 03C17.
46 is a clock that generates reference signals 5YNC2 and 5YNC3 that determine the generation timing of 0DRV and EDRV, and 5YNC2 and 5YNC3 are clocked according to the set values of presettable counters 24 and 25 set by a signal line 550 connected to the CPU bus. The output timing is determined, and 5YNC2 and 5YNC3 initialize the frequency divider 26.27 and the drive pulse generation section 28.29.

In other words, the CI output from one oscillation source O8C is based on HSYNC544 input to this block.
Since they are generated by Jφ and the divided clocks that are all generated synchronously, 0DRV501 and EDRV50
Each of the two pulse groups is obtained as a synchronized signal with no jitter at all, and it is possible to prevent signal disturbance due to interference between sensors.

Here, sensor drive pulses 0D obtained in synchronization with each other
RV501 uses EDRV50 as the 1st and 3.5th sensors.
2 is supplied to the second and fourth sensors, and each sensor 18.
From 19.20.21.22, video signals V1 to V5 are independently output in synchronization with the drive pulse, and are adjusted to a predetermined voltage value by an independent amplifier circuit (preamplifier) 8 for each channel shown in Figure 1. Amplified and coaxial cables 508-512
Through the timing test V1.00553g shown in FIG. 2(b). V3. The V5(7) signal changes to V2. at the timing of EOS543. The V4 signals are respectively sent out and input to the video processing unit.

Analog color image signals read by the aforementioned 5-chip equal-magnification color sensor are input to the analog signal processing circuit 9 shown in the first diagram for each channel. Since the signal processing circuits corresponding to each channel are the same circuit, the fifth
The process will be explained according to the illustrated processing block diagram together with the timing chart of FIG.

The input analog color image signal is 5iG as shown in Figure 5.
The order is as shown in A < B-G-H, and in addition to the 2880 effective pixels, there is an empty transfer section that is not connected to the photodiode of the 12-pixel color sensor before the effective pixel, and then 4
This is a composite signal consisting of a total of 2952 pixels, consisting of an 8-pixel photodiode, a dark output section (optical plaque) shielded with aluminum, and a 12-pixel blank transfer section (see FIG. 4).

The analog color image signal 5iGA is input to the buffer 30 and impedance converted. Next, buffer 30
The reset portion of the composite signal is removed by the S/H circuit 31 according to the S/H pulse, and the output signal becomes an S/H output signal from which waveform distortion caused by high-speed driving has been removed (S/H0UT in Figure 6). ).

Since the sampled/held point-sequential color signal contains unwanted components at the frequency of the sampling pulse,
In order to remove this, we next use a low-pass filter (LPF).
) Enter 32. The point-sequential color signal from which unnecessary sampling frequency components have been removed is input to the amplifier 33, where it is amplified to a specified signal output, and at the same time, DC level fluctuations of the analog color signal whose DC level fluctuates due to sensor temperature rise are removed. In order to fix the DC level of the image signal to the optimal operating point of the amplifier 33, the feedback clamp circuit 34 clamps the image signal to zero level.

The feedback clamp circuit is composed of an S/l (circuit 34a) and a comparator amplifier 34b, and the eight levels of the dark output part (optical black) of the analog color signal pressed by the amplifier 33 are detected by the S/H circuit 34a. G input to the inverting input terminal of the comparator amplifier 34b
It is compared with the ND (ground) level, and the difference is fed back to the amplifier 33, and the dark output part of the output of the amplifier 33 is always fixed at the GND level.

Here, the DK image signal is a signal indicating the section of the dark output part of the analog color signal, and by supplying it to the S/H circuit 34a, when the original image is not being read (during standby), the DC of the dark output part of the analog color signal is Level horizontal scanning period rJ1 (
It can be detected once every 11().

Further, when reading an original image (copying), the DC level of the dark output section is detected once every NH, but the S/H circuit 34a.

Since the comparison amplifier 34b has a time constant of NH, it is hardly affected by changes in the dark output level due to light leakage.

The zero clamp circuit also has the purpose of eliminating input offset when the amplitude is varied in the next stage dot sequential amplitude control circuit. The signal whose dark output portion of the analog color signal is zero-clamped is then input to a point-sequential amplitude control circuit. Here, gain adjustment is performed for each color separation signal of the dot sequential color signal using CPLIIIJ@.

Reference numerals 35a, b, and c shown in FIG. 5 are analog switches, and data is set via the data bus 533 of the CPU, and the resistance voltage division ratio of each attenuator is determined by a combination of at least one analog switch. The point sequential signals, each attenuated with a predetermined voltage division ratio, are sent to an analog switch 37 via buffers 36a, b, and c.
Gate signal GSEL by a, b, c.

Each color separation signal is extracted under the control of BSEL and BSEL.

The color-balanced point-sequential signal then enters a voltage controlled amplifier (VCA) 3g, where point-sequential color signal common gain adjustment is performed. 39 is a D/A converter, and data is set via a data bus 533 of the CPU. D/
A converter output V. ut is V. -” Vr-r/N O<N<1.

where N is the binary-fractional value of the input digital code.

Reference numeral 38 denotes a voltage controlled amplifier having a multiplier configuration, a gain control input terminal of which is connected to the output terminal of the D/A converter 39, and a dot sequential color signal inputted to the other input terminal. D
The relationship between the set data of the /A converter 39 and the gain is shown in the seventh
As shown in the figure.

A/ when the original scanning unit 3 reads the uniform white plate
The data of the D/A converter 39 is set from the CPU data bus 533 so that the D-converted output data (R, G, B) becomes a predetermined value, and the color signal level is dot-sequentially amplified.

The level controlled analog color signal is then passed through an amplifier 40
and is amplified to the input dynamic range of the A/D converter 44, and at the same time, the DC level is controlled by the feedback clamp circuit 42 and the multiplier 43.

Next, a feedback clamp system composed of the multiplier 43 and the feedback clamp circuit 42 will be explained. This feedback clamp system has almost the same configuration as the feedback clamp circuit 34 at the previous stage. A CPυ controlled multiplier 43 is connected to obtain a reference voltage for a feedback clamp circuit composed of an S/H circuit 42a and a comparison amplifier 42b. Also,
In the channel connection correction process to be described later, in order to shift the level of the read black level image signal, the CPU
The reference voltage is varied by multiplier 43 at a level determined by digital data set in an internal latch via data bus 533 of amplifier 40 . Buffer 41 clamps the amplified analog color signal to a reference voltage level.

As shown in FIG. 8(a), the multiplier 43 includes a multiplication D/A converter 550 and operational amplifiers 552 and 556.
and resistance value R of resistance 553.554 and resistance value 2R
It is a multiplier in all four quadrant modes, which is constructed of a resistor 555, and outputs bipolar voltages as shown in FIG. 8(b) according to 8-bit digital data set by the CPU.

The buffer 41 is a large-power buffer for the A/D converter 44, and has a low output impedance and high speed so that its impedance is less than the reference resistance value of the A/D internal comparator that guarantees the linearity accuracy of A/D processing. It is configured as a buffer.

Now, the point-sequential color signal that has been amplified to a predetermined white level and black level and DC-clamped is input to the A/D converter 44, becomes digital data A/D OUT, and is then processed for timing adjustment with the digital signal processing circuit. and enters the latch circuit 45 for reliable digital data transmission. 0LA
The latch output data latched with TCHCLK is latched in the next digital signal processing circuit with a latch clock of opposite polarity to 0LATCHCLK, thereby making it possible to receive digital data at a reliable timing. The same applies to the analog signal processing circuits of channels 2 to 5.

Next, the digitally converted dot-sequential color signals 513 to 517 of each channel enter the digital signal processing circuit 10, and the FiFo memory 11 performs image connection between the channels, and the dot-sequential color signals of each channel are R, G
, B are three-color parallel signals (518 to 520).

Next, the R, G, and B digital color signals are input to the black correction/white correction circuit 13. First, the black correction circuit will be explained.

The black level outputs of channels 1 to 5 have large variations between chips and between pixels when the amount of light input to the sensor is small.

If this is output as is and an image is output, streaks and unevenness will occur in the data portion of the image.

Therefore, it is necessary to correct the output variation of this black part. Therefore, prior to the copying operation, the original scanning unit 3 is moved to the position of a black plate with uniform density placed in the non-image area at the tip of the original platen, the halogen lamp is turned on, and the black level image signal is sent to this circuit. input. One line of this image data is stored in the black level memory and becomes the black reference value (hereinafter referred to as black reference value import mode).

For example, if the data number i of the black level data DK(i) has a width in the longitudinal direction of A4 in the main scanning direction, it is 400 dpi.
15.75 x 297mm = 4678 pixels/each color, but to cover that length, 61-axis CC
If 5 D chips are lined up to form one line, it will be 15.75.
x 61 mm x 5 = 4800 pixels/i = 1 to 4800 (7) values corresponding to each color can be taken.

When reading an image, for example, in the case of a blue signal, Bin(i) −〇k(i) for black level data DK(i)
=Bout(1), a black correction output is obtained (black correction mode).Similarly, green Gin and red Rin are also controlled in the same manner, resulting in a black correction output GOutlROut.

Next, a white level correction (shading correction) circuit will be explained.

White level correction is to correct variations in sensitivity of the illumination system, optical system, and sensor based on white data obtained when the document scanning unit 3 is moved to a uniform white plate position and irradiated. The basic circuit configuration is the same as the black correction circuit, but
The difference is that black correction uses a subtracter, whereas white correction uses a multiplier. During white correction, first, when the original scanning unit 3 is at the uniform white plate position (home position), that is, before copying or reading, the exposure lamp is turned on and one line of uniform white level image data is Store in color level memory.

For example, if it has an A4 longitudinal width in the main scanning direction, 15.75 x 297 mm = 467 at 400 dpi
Although it has 8 pixels, the image data of 1 CCD chip is 96 pixels.
If each pixel is composed of 0 pixels (400 dpi x 61 mm), the result is 960 x 5 = 4800 pixels. That is, if the capacity of the white level memory is at least 4800 bytes, and the white board data of the i-th pixel is W(i),
i=1 to 4800.

On the other hand, for W(i), the read value of the normal image of the i-th pixel is 0+fi(1), and the image data after correction is D0□(i)=D+n(i)XFFH/W(i). , green (G), blue (B), and red (R).

Next, when reading the base film of various photographic films, if the color balance of the G, B, and R signals is off, the data is set again to the analog switches 35a, b, and c via the data bus 533 of the CPU. , color balance is adjusted, and white shape ink correction is performed again.

Three color image signals (521
~523) are then input to the image processing circuit 14. Then, a logarithmic conversion circuit that converts luminance data into density data, spectral characteristic correction of the color separation filter of the CCD sensor, and unnecessary absorption characteristics of color toner (Y, M, C) transferred to copy paper in the color printer 2 are used. Min (Yi,
Mi, Ci) (minimum value of Yi, Mi, Ci) is calculated, this is used as a black toner, and black toner is added afterwards.A summarizing circuit reduces the amount of each coloring material added according to the added black component. The image is processed through an under color removal (UCR) circuit (see 524 in FIG. 1).

The three color image signals are then input to the printer interface 15. In addition to the digital video signal, the interface signals include a synchronization signal (ITO) in the image feeding direction (sub-scanning direction).
P), a synchronization signal (BD) in the raster scan direction (main scan direction) that occurs once per raster scan, a synchronization clock (VCLK) for sending the digital video signal to the color printer unit 2, and a BD multiplication signal base. A synchronization signal (I(S) generated by synchronizing jitter-free VCLK
YNC) and signals for half-duplex bidirectional serial communication (SRCOM).

Image information and instructions are sent from the league section to the printer section through these signal lines, and the printer section exchanges printer section status information such as jam, out of paper, weight, etc.

[Effects of the Invention] As explained above, according to the present invention, there is provided an analog signal processing means for processing a signal while leaving a DC component of a point-sequential video signal output from a photoelectric conversion means, and an analog signal processing means included in the analog signal processing means. The clamping means has a time constant that is N times the horizontal scanning period (H) of the image signal, and the clamping means sets the clamping period of the image signal to H when the original image is not being read (during standby), and when the original image is being read (during copying). ), by providing a clamp pulse selection means with a clamp period of NXH, the I clamp during standby cancels dark current changes due to temperature rise of the photoelectric conversion means, and during copying, the clamp period becomes NXH and dark current of the photoelectric conversion means is canceled. It is possible to eliminate the influence of level changes due to light leakage to the output section, and to suppress differences in density levels between channels.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal processing unit in a league section in a digital color copying machine according to an embodiment of the present invention, FIG. 2(a) is a layout diagram of a color CD sensor, and FIG.
b) is a signal timing diagram of each part shown in Fig. 2(a), Fig. 3(a) is a diagram showing the CCD drive signal generation circuit (circuit inside the system control pulse generator 16), Fig. 3(b) is a timing diagram showing the operation of FIG. 3(a), FIG. 4 is a CCD drive timing diagram, and FIG. 5 is a block diagram showing this embodiment of one channel of the analog signal processing circuit 9 shown in FIG. 1. , FIG. 6 is a signal timing diagram of each part shown in FIG. 5, FIG. 7 is a characteristic diagram of the voltage-controlled amplifier circuit, FIG. 8(a) is a circuit diagram of the multiplier 43 shown in FIG. 7, FIG. 8(b) is a diagram showing the code table. 9... Analog signal processing circuit, lO... Digital signal processing circuit. 2...Color laser beam printer, 3...Document scanning unit, 4...Video processing unit, 5...Control unit, Fig. 7 Tenidagus 533 Fig. 8 (.) Fig. 8 (b) )

Claims (1)

[Scope of Claims] 1) In an image reading device having a photoelectric conversion means for converting an optical signal from a medium having image information into an electric signal, a direct current of a point-sequential image signal obtained by photoelectric conversion by the photoelectric conversion means is provided. An image reading device characterized by comprising an analog signal processing means having a processing means for processing a signal while leaving a component, and a clamping means having a time constant N times the horizontal scanning period (H) of an image signal. 2) In the image reading device according to claim 1, the clamping means sets the clamping period of the image signal to H when the original image is not being read during standby, and the clamping period is set to N× when the original image is being read during copying. An image reading device characterized by comprising a clamp pulse selection means denoted by H.