JPH03273760A - Picture reader - Google Patents

Abstract

PURPOSE:To suppress density level difference between respective channels by providing a sample pulse generating means to stop a sample pulse during a block corresponding to the dark output part of a photoelectric conversion means in the case of sample/hold, and a direct current reproducing means to directly reproduce a signal level corresponding to the stop block at a prescribed poten tial. CONSTITUTION:A dot sequence video signal to be photo-electrically converted by the photoelectric conversion means is sampled/held by the sample/hold means and in the case of this sample/hold, the sample pulse generating means stops the input of the sample pulse for the block corresponding to the dark output part of the photoelectric conversion means. Further, in the outputs of the sample /hold means, the signal level corresponding to the sample pulse stop block in the dark output part of the photoelectric conversion means is directly repro duced at the prescribed potential by the direct current reproducing means. Thus, an influence caused by leaked light to the dark output part of the photoe lectric conversion means upon a level change is eliminated and the density level difference between respective channels can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device that reads images using a plurality of image sensors.

[Conventional technology]

2. Description of the Related Art Conventionally, as an image sensor used for image reading, one in which a stripe type color filter is provided on a one-line image sensor and color separation signals are read out point-sequentially in a time-division manner is known.

For example, when reading an A4 297 mm long document,
Silicon crystal image sensors are suitable for high-speed reading, but due to manufacturing constraints, it is difficult to make a long type of silicon crystal image sensor with one chip, so multiple silicon crystal image sensors are used. A one-line sensor is configured by physically placing the sensor at a predetermined position.

In addition, various drive pulse leak noises included in the image sensor output signal, especially reset pulse leak noise and transient noise at transfer lock cross points, are removed, and the image sensor output signal due to high load capacitance during high-speed reading is reduced. In order to remove the influence of waveform rounding and perform stable sampling in an A/D converter, a method has been known in which a sample and hold (S/H) circuit is used to convert the signal into a stable level signal.

Furthermore, in order to stabilize the reference level of the image sensor output signal, a DC regeneration (clamp) circuit has been used to fix the dark output section of the image sensor to a predetermined potential.

[Problem to be solved by the invention]

However, in the conventional example described above, since the long type image sensor is composed of a plurality of chips, reflected light leaks into the image sensor dark output section from the edge of the cut surface of each chip, resulting in a change in level. Since this is sampled and held by the S/H circuit and the dark output section is fixed at a predetermined potential by the clamp circuit, the effective image level changes relatively.

Here, when bright light corresponding to the white of the original image comes to the part corresponding to the dark output part of the chip with the image sensor, the density changes in the horizontal scanning direction, and a difference in density level occurs between the images corresponding to each chip. There were some problems.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide an image reading device in which no difference in density level occurs between channels, regardless of the type of original image.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides an image reading device having a photoelectric conversion means for converting an optical signal from a recording medium on which image information is recorded into an electrical signal. A sample hold means samples and holds a point-sequential video signal obtained by photoelectric conversion by the photoelectric conversion means, and a section corresponding to the dark output part of the photoelectric conversion means among the sample pulses manually inputted to the sample hold means is sampled. The present invention is characterized by comprising sample pulse generation means for suspending input of pulses.

Furthermore, the present invention is characterized by comprising DC regeneration means for regenerating a signal level corresponding to a sample pulse rest period of the dark output section of the photoelectric conversion means out of the output of the sample hold means to a predetermined potential. .

[For production]

In the present invention, a point-sequential video signal obtained by photoelectric conversion by the photoelectric conversion means is sampled and held by the sample and hold means, and when sample-holding, input of a sample pulse in an interval corresponding to the dark output section of the photoelectric conversion means is performed. The signal level corresponding to the sample pulse pause section of the dark output section of the photoelectric conversion means is DC-regenerated to a predetermined potential by the DC regeneration means, and the signal level corresponding to the sample pulse pause period of the dark output section of the photoelectric conversion means is DC-regenerated to a predetermined potential. It is possible to eliminate the influence of level changes due to light leakage to the dark output section, and to suppress differences in density levels between channels.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An image reading device that is an embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of a signal processing block of a color image reading device. The original is first irradiated by an exposure lamp, and the reflected light is separated into colors for each image and read by a color reading sensor 6 in the original scanning unit 3, and amplified to a predetermined level by a preamplifier 8. 7 is a CCD driver that supplies pulse signals for driving the color reading sensor, and the necessary pulse source is generated by the system control pulse generator 16.

Figures 2 and 3 illustrate the color read sensor and drive pulses. Here, FIG. 2 shows the color reading sensor used in this embodiment. In order to read the main scanning direction divided into 5 parts, each pixel is 63.5 μm, and each pixel is divided into 960 pixels. B in the main scanning direction
, G, and R, so the total is 960
3 = 2880 effective pixels. On the other hand, each chip 18 to 22 is formed on the same ceramic substrate, and the 1st, 3rd, and 5th sensors (18, 20, 22) are on the same line LA, and the 2nd and 4th sensors (19, 21) are on the same line LA. is arranged on line LB separated by four lines (63.5 μm x 4 =252 μm), and is scanned in the direction of arrow AL when reading the document.

In each of the five CCDs, the 1st and 3.5th drive pulse group is 0DRV501, and the 2nd and 4th are EDRV50.
2, each is driven independently and synchronously.

Included in 0DRV501: 60φlA, 0$2A, OR3
and EφIA, Eφ2A included in EDRV502,
ER3 is a charge transfer lock within each sensor,
These are charge reset pulses, and are generated in complete synchronization with each other without jitter due to mutual interference between the 1st, 3.5th and 2nd, 4th pulses and noise limitations. Therefore, these pulses are connected to one reference oscillator source 05CI? (See Figure 1).

Figure 4 shows 0DRV501. The circuit block that generates EDRV502, FIG. 5 is its timing chart,
System control pulse generator 1 shown in the first diagram
Included in 6.

The clock φ546 is the frequency-divided original clock CLKφ generated by a single 03C17, and the reference signal 5YNC2, 5YNC determines the generation timing of 0DRV and EDRV.
This is a clock that generates 3. Reference signal 5YNC2,5
The output timing of YNC3 is determined according to the set value of the presettable counter 24.25 set by the signal line 550 connected to the CPU bus, and
NC3 is a frequency divider 26, 27 and a drive pulse generator 28
．． 29 is initialized.

In other words, with reference to H3YNC544 input to this block, all C output from one oscillation source O8C
LKφ and the divided clocks that are all generated synchronously, so 0DRV501 and EDRV
Each of the pulse groups 502 is obtained as a synchronized signal with no jitter at all, and signal disturbances due to interference between sensors can be prevented.

Here, sensor drive pulses 0D obtained in synchronization with each other
RV501 has EDRV5 on the 1st and 3.5th sensors.
02 is supplied to the second and fourth sensors, and each sensor 18.
From 19.20.21.22, video signals v1 to V5 are independently output in synchronization with the drive pulse, and are amplified to a predetermined voltage value by an independent preamplifier 8 for each channel shown in Figure 1, and then connected to the coaxial cable. 508 to 512, Vl, V3.
V5 (7) signals are sent respectively, and at the timing of EOS543, V2. The V4 signals are respectively sent out and input to the video processing unit.

Analog color image signals read by the aforementioned 5-chip equal-magnification color sensor are input to the analog signal processing circuit 9 shown in FIG. 1 for each channel. Since the signal processing circuits corresponding to each channel are the same circuit, the circuit of channel 1 (chi) will be explained with reference to the processing block diagram shown in FIG. 7 and the timing chart shown in FIG. 8.

The analog color image signal input manually is 5 as shown in Figure 7.
Like iGA, it is in the order of B-4G-1R, and 28
In addition to the 80 effective pixels, there is a 12-pixel empty transfer section in front of the effective pixels that is not connected to the photodiode of the color sensor, a dark output section (optical black) shielded with aluminum on the 488-pixel photodiode, and a 12-pixel empty transfer section. This is a composite signal composed of a total of 2,952 pixels consisting of 10 pixels (see FIG. 6).

The analog color image signal 5iGA is input to the buffer 30 and impedance converted. Next, buffer 30
The reset portion of the composite signal is removed by the S/H circuit 31 according to the S/H pulse, and the output signal becomes an S/H output signal from which waveform distortion caused by high-speed driving has been removed (S/H circuit 31 in FIG. H0UT).

Here, the sample pulse (S/HP in FIG. 8) is paused over 488 pixels of the dark output part of the sensor, and
Instead of the dark output section, the empty transfer section is held and output at the /H output.

The sampled/held point-sequential color signal contains unnecessary components at the frequency of the sampling pulse, so to remove them, a low-pass filter (LPF) is applied.
) enters 32. The point-sequential color signal from which unnecessary sampling frequency components have been removed is input to the amplifier 33, where it is amplified to a specified signal output, and at the same time, DC level fluctuations of the analog color signal whose CD level fluctuates in an AC manner are removed. In order to fix the DC level of the image signal at the optimal operating point of the amplifier 33, it is clamped to zero level by the feedback clamp circuit 34.

The feedback clamp circuit is composed of an S/H circuit 34a and a comparator amplifier 34b, and the output level of the idle transfer hold section of the analog color signal output from the amplifier 33 is detected by the S/H circuit 34a, and the output level of the analog color signal output from the amplifier 33 is detected by the S/H circuit 34a. The difference is fed back to the amplifier 33, and the idle transfer hold section of the output of the amplifier 33 is always fixed at the GND level.

Here, the CP signal is a signal indicating the section of the idle transfer hold section of the analog color signal, and by supplying it to the S/H circuit 1 2 34a, the DC level of the idle transfer hold section of the analog color signal is adjusted during the horizontal scanning period. It can be detected once every (1H).

The zero clamp circuit also has the purpose of eliminating input offset when the amplitude is varied in the next stage dot sequential amplitude control circuit. The signal in which the idle transfer hold section of the analog color signal has been clamped to zero is then input to a point-sequential amplitude control circuit. Here, gain adjustment is performed for each color separation signal of the dot sequential color signal under CPU control.

Reference numerals 35a, 35b, and 35c shown in FIG. 7 are analog switches, data is set via the data bus 533 of the CPU 5, and the resistance voltage division ratio of each attenuator is determined by a combination of at least one analog switch. The point-sequential signals attenuated with predetermined voltage division ratios are passed through buffers 36a, 36b, and 36c to analog switches 37a, 37b, and 37c, and each color separation signal is extracted under the control of gate signals GSEL, BSEL, and BSEL. .

The color balanced dot sequential signal then enters a voltage controlled amplifier (VCA) 38 where point sequential color signal common gain adjustment is performed. 39 is a D/A converter, C
Data is set via the data bus 533 of PU5. D/A converter output V. Ua is VOut= Vr=
r/N O<N<1. where N is the binary-fractional value of the input digital code.

Reference numeral 38 denotes a voltage controlled amplifier having a multiplier configuration, a gain control input terminal of which is connected to the output terminal of the D/A converter 39, and a dot sequential color signal inputted to the other input terminal. FIG. 9 shows the relationship between the set data of the D/A converter 39 and the gain.

A/ when the original scanning unit 3 reads the uniform white plate
The data of the D/A converter 39 is set from the CPU data bus 533 so that the D-converted output data (R, G, B) becomes a predetermined value, and the color signal level is dot-sequentially amplified.

Next, the level-controlled analog color signal is input to the amplifier 40 and amplified to the input dynamic range of the A/D converter 44, and at the same time, the DC level is controlled by the feedback clamp circuit 42 and the multiplier 43.

Next, a feedback clamp system composed of the multiplier 43 and the feedback clamp circuit 42 will be described.

This feedback clamp system has almost the same configuration as the feedback clamp circuit 34 at the previous stage. Then, in order to obtain the reference voltage of the feedback clamp circuit composed of the S/H circuit 42a and the comparison amplifier 42b,
A CPU-controlled multiplier 43 is connected. In addition, in the channel connection correction processing described later, in order to shift the level of the read black level image signal, the multiplier 43 is used at a level determined by digital data set in an internal latch via the data bus 533 of the CPU. The reference voltage is varied and the amplifier 40. Buffer 41 clamps the amplified analog color signal to a reference voltage level.

As shown in FIG. 10, the multiplier 43 includes a multiplying D/A converter 550, an operational amplifier 552, 556, a resistor 553, 554 with a resistance value R, and a resistor 555 with a resistance value 2R.
It is a multiplier with all four quadrant modes, consisting of CPU
According to the 8-bit digital data set from , bipolar voltages are output as shown in Table 1.

Table 1 The buffer 41 is an input buffer for the A/D converter 44, and has a low output impedance so that its impedance is less than the reference resistance value of the A/D internal comparator that guarantees the linearity accuracy of A/D processing. It is also configured as a high-speed buffer.

Now, the point-sequential color signal amplified and DC-clamped to predetermined white and black levels is input to the A/D converter 44 and becomes digital data A/D OUT. next,
It enters a latch circuit 45 for timing alignment with the digital signal processing circuit and reliable digital data transmission. 0
The latch output data latched by LATCHCLK is
In the next digital signal processing circuit, the signal is latched by a latch clock of opposite polarity to 0LATCHCLK.
Digital data can be received with reliable timing.

The same applies to the analog signal processing circuits of channels 2 to 5 as described above.

Next, the digitally converted dot sequential color signals 513 to 517 of each channel enter the digital signal processing circuit 10, and the FiFo memory 11 performs image connection between the channels, and the dot sequential color signals of each channel are R,
The parallel signals of the three colors G and B are 518° 6 519520.

Next, the R, G, and B digital color signals are input to the black correction/white correction circuit 13. First, the black correction circuit will be explained.

The black level outputs of channels 1 to 5 have large variations between chips and between pixels when the amount of light input to the sensor is small. If this is output as is and an image is output, streaks and unevenness will occur in the data portion of the image, so it is necessary to correct output variations in the black portion. Therefore, prior to the copying operation, the document scanning unit 3 is moved to the position of a black plate with uniform density located in the non-image area at the tip of the document table.
Turn on the halogen lamp and input the black level image signal to this circuit. One line of this image data is stored in the black level memory and becomes the black reference value (hereinafter referred to as black reference value import mode).

For example, if the black level data DK(i) has a width in the longitudinal direction of A4, the number i of the black level data DK(i) is 400d.
Pi is 15.75 x 297mm = 4678 pixels/each color, but to cover that length, 61mm
If five CCD chips are one line, then 15.
75 x 61 mm x 5 = 4800 pixels/i=1 to 4800 chips corresponding to each color can be taken.

When reading an image, for example, in the case of a blue signal, B+n(i)-D*(i
)=t+a, a black correction output is obtained as t(i) (black correction mode). Similarly, Green Gin, Red R
In control is performed, and the black correction output G. ut, Rout
becomes.

Next, a white level correction (shading correction) circuit will be explained.

White level correction is to correct variations in sensitivity of the illumination system, optical system, and sensor based on white data obtained when the document scanning unit 3 is moved to a position of a uniform white plate and irradiated with it. The basic circuit configuration is the same as the black correction circuit, but the difference is that black correction uses a subtracter, whereas white correction uses a multiplier. During white correction, first, when the document scanning unit 3 is at the uniform white plate position (home position), that is, before copying or reading, the exposure lamp is turned on and image data of uniform white level is captured for 1947 minutes. color level memory.

For example, if the width in the longitudinal direction is A4 in the main scanning direction,
00dpi is 15.75 x 297mm = 4678 pixels, but if the image data of one CCD chip is composed of 960 pixels (400dpi x 61mm),
960X5=4800 pixels. That is, the capacity of the white level memory is at least 4800 bytes, and if the white board data of the i-th pixel is W(i), then i = 1 to
4800 roar.

On the other hand, for W(i), the reading value of the normal image of the i-th pixel. For (i), the image data after correction is Dout(i) = DIll fi) X FFH
/W(t), and white correction is performed for each color of green (G), blue (B), and red (R).

Next, when reading the base film of various photographic films, if the color balance of the G, B, and R signals is disrupted, the data is sent to the analog switches 35a, 35b, 3 again via the data bus 5339 of the CPU.
5c, color balance is adjusted, and white shading correction is performed again.

Three color image signals (52
1 to 523) are then manually input to the image processing circuit 14.

Then, in the logarithmic conversion circuit that converts luminance data into density data, the spectral characteristic correction of the color separation filter of the CCD sensor, and the unnecessary absorption characteristics of color toner (Y, M, C) transferred to copy paper in the color printer 2. Min (Y
i, Mi, Ci) (minimum value of Yi, ML, Ci), and uses this as ink (black) to add black toner later, and the amount of each color material to be added according to the added black component. The image is then processed through an under color removal (OCR) circuit that reduces the color difference (see 524 in FIG. 1).

Next, the three color image signals are sent to the printer interface 15.
is input. In addition to digital video signals, interface signals include a synchronization signal (ITOP) in the image feed direction (sub-scan direction), a synchronization signal (BD) in the raster scan direction (main scan direction) that occurs once per raster scan, and digital video. Synchronous clock (VCLK) for sending signals to color printer section 2
, a synchronization signal (H3YNC) generated by synchronizing jitter-free VCLK based on the BD signal, and a signal for half-duplex bidirectional serial communication (SRCOM).

Image information and instructions are sent from the league section to the printer section through these signal lines, and the printer section exchanges printer section status information such as jam, out of paper, weight, etc.

〔Effect of the invention〕

As explained above, according to the present invention, when sample-holding the point-sequential video signal output from the photoelectric conversion means by the sample-hold means, the sample pulse is stopped in the section corresponding to the dark output section of the photoelectric conversion means. By providing a sample pulse generation means for generating a sample pulse and a DC regeneration means for DC regeneration of a signal level corresponding to a sample pulse rest period to a predetermined potential, the effects of level changes due to leakage light to the dark output section of the photoelectric conversion means are eliminated, and the original Regardless of the image, when using an image sensor with a multi-chip configuration, it is possible to suppress density level differences between each channel.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the video signal processing unit of the league section in a digital color copying machine according to an embodiment of the present invention, FIG. 2 is a diagram showing the arrangement of the CCD sensor 6 shown in the first diagram, and FIG. FIG. 4 is a diagram showing an example of the signal timing of each part shown in FIG. 4. FIG. FIG. 6 is a diagram showing an example of CCD drive timing; FIG. 7 is a block diagram showing one channel of the analog signal processing circuit 9 shown in FIG. 1; FIG. 8 is a diagram showing each part shown in FIG. 7. FIG. 9 is a diagram showing the characteristics of the voltage-controlled amplifier circuit. FIG. 10 is a diagram showing the configuration of the multiplier shown in FIG. 7. 2... Color laser beam printer, 3... Document scanning unit, 4... Video processing unit, 5... Control unit, 9... Analog signal processing circuit, lO... Digital signal processing circuit. 3 4 JP-A-3 273760 (12)

Claims (1)

[Scope of Claims] 1) In an image reading device having a photoelectric conversion means for converting an optical signal from a recording medium on which image information is recorded into an electric signal, a dot-sequential video signal obtained by photoelectric conversion by the photoelectric conversion means. sample-holding means for sampling and holding the sample-holding means; and sample-pulse generating means for suspending input of the sample pulse during a section corresponding to the dark output section of the photoelectric conversion means among the sample pulses input to the sample-holding means. An image reading device characterized by: 2) The image reading device according to claim 1, further comprising DC regeneration means for regenerating a signal level corresponding to a sample pulse rest period of the dark output section of the photoelectric conversion means out of the output of the sample hold means to a predetermined potential. An image reading device characterized by: