JPH03126371A - Picture reader - Google Patents

Abstract

PURPOSE:To avoid deviation of picture joints between channels caused by the temperature characteristic of a logarithmic transformation circuit by providing a synthesis means, a D/A converter means, a logarithmic transformation means and a 2nd D/A converter means to a post-stage of a 1st A/D converter means receiving a color signal. CONSTITUTION:A color signal outputted from an image sensor 6 is converted into a digital signal by a 1st A/D converter means 9, D/A conversion processing 16 is applied to each color signal after joints of pictures of each channel, and a logarithmic transformation means 18 and a 2nd A/D conversion means 19 are provided to the post stage. Thus, the deviation of picture joints of each channel due to the temperature characteristic of the logarithmic transformation means 18 and the accuracy of the 1st A/D converter means 9 is multiplied by a multiple of the gain by the logarithmic transformation means 18 and the deterioration in the accuracy with respect to a low level signal is relieved especially.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device that reads images using a plurality of channels of image sensors.

[Prior Art] Conventionally, as an image sensor used for high-speed image reading, there has been a method in which a stripe-type color filter is attached to a single-line image sensor and color separation signals are read out point-sequentially in a time-division manner. be.

As a logarithmic conversion circuit for converting luminance signal data into density signal data, it is known to construct a table in a memory such as a ROM in a digital domain and perform logarithmic conversion after connecting images between each channel. Another method is to approximate the logarithmic conversion using a polygonal line by shifting the intermediate level of the reference voltage of the A/D converter over multiple points from the normal level in the analog range before the A/D conversion.
Some systems perform logarithmic conversion by inserting a logarithmic conversion amplifier before the /D converter.

[Problems to be Solved by the Invention] However, when a logarithmic conversion circuit in the digital domain is configured with a memory such as a ROM, low-level signals after logarithmic conversion (in black areas of the original image) high level signal (equivalent to the white part of the original image)
This results in a large gain compared to . For this reason, the accuracy after A/D conversion is multiplied by the gain, resulting in a disadvantage that the gradation of black areas becomes poor.

In addition, in order to configure a logarithmic conversion circuit in the analog domain,
If a voltage is applied from an external circuit to the intermediate level of the /D converter's reference voltage at multiple points, and logarithmic conversion is approximated using a polygonal line shifted from the normal level, a disadvantage is that the polygonal level changes depending on the temperature characteristics of the external circuit. There is.

Furthermore, even when a logarithmic converter is inserted before the A/D converter, there is a problem in that the temperature characteristics of the logarithmic conversion circuit for each channel impede image connection between channels.

SUMMARY OF THE INVENTION Therefore, in view of the above-mentioned points, an object of the present invention is to provide an image reading device that is configured to eliminate the image connection deviation between each channel caused by the temperature characteristics of the logarithmic conversion circuit, and to obtain appropriate image signals over all levels. I will provide it.

[Means for Solving the Problems] The present invention provides an image reading device that reads a medium having image information using an image sensor, and a first ^/D that inputs color signals sequentially output from the image sensors of a plurality of channels. a converting means; a synthesizing means connected after the first D/D converting means and for connecting images between each channel; a D/A converting means connected after the synthesizing means; The apparatus includes: a logarithmic conversion means connected after the logarithmic conversion means; and a second ^/D conversion means connected after the logarithm conversion means.

[Function] According to the present invention, the color signal output from the image sensor is converted into a digital signal by the first D/D conversion means, and the D/D conversion is performed for each color signal after the images of each channel are connected.
By performing the conversion process to 8 and then providing the logarithmic conversion means and the second A/D conversion means, it is possible to eliminate the image connection deviation of each channel due to the temperature characteristics of the logarithm conversion means,
Furthermore, the accuracy of the first A/D conversion means is multiplied by the gain by the logarithmic conversion means, making it possible to reduce deterioration in accuracy particularly for low level signals.

[Embodiment] Hereinafter, an embodiment of a color image reading device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a signal processing block of a color image reading device. The document is first irradiated with an exposure lamp, and the reflected light is separated into colors for each image and read by a color reading sensor 6 in the document scanning unit 3, and amplified to a predetermined level by an amplifier circuit (preamplifier) 8. 7 is a CCD driver that supplies pulse signals for driving the color reading sensor, and the necessary pulses are generated by the system control pulse generator 23.

Figures 2(a) and 2(b) show the color reading sensor and drive pulses. Here, FIG. 2(a) shows the color reading sensor used in this embodiment, and it reads 62.5 am (
With 1/16III11) as one pixel, there are 976 pixels, that is, one pixel is divided into three by G, B, and R in the main scanning direction as shown in the figure, so the total number of effective pixels is 1024X 3 =3072.

On the other hand, each chip 25 to 29 is formed on the same ceramic substrate, and the 1st, 3rd, and 5th chips (25, 27, 29) of the sensor
is on the same line LA, and the 2.4th (26, 28) is on the L
It is placed on line LB, which is separated from A by 4 lines (62.5μΦX4=250μm), and when reading the original,
Arrow AL is scanned in the force direction. In each of the five CCDs,
1.3.5th is drive pulse group 0DRV501 D, 2
, and the fourth are driven independently and synchronously by the EDRV 502. 0φ1 included in 0DRV501
^, 0φ2A.

ORS and EDRV502 include EφIA, Eφ
2A and ER5 are the charge transfer lock and charge reset pulses in each sensor, respectively, and the 1st, 3.5th, and 2nd
．． Due to mutual interference with the fourth signal and noise limitations, they are generated in complete synchronization with each other without jitter. For this reason, these pulses are generated from one reference oscillator source 05C24 (FIG. 1).

FIG. 3(a) shows a circuit block for generating 0DRV501 and EDRV502, and FIG. 3(b) shows a related timing chart. The original clock CL generated by a single 05C24 is divided by φ, and φ549 is a reference signal 5YNC2 that determines the generation timing of 0DRV and EDRV.

This is the clock that generates 5YNC3, and 5YNC2,5
The output timing of YNC3 is determined according to the set value of the presettable counter 31.32 set by the signal line 551 connected to the CPU bus, and the output timing of 5YNC2, 5Y
NC3 is frequency divider 33.34J3 and drive pulse generator 3
Initialize 5.36. That is, with HSYNC547 input to this block as a reference, all oscillation sources O5C
Since it is generated by φ and the divided clock that is all generated in synchronization with CL output from CL, 0DRV
Each of the pulse groups 501 and EDRV 502 is obtained as a synchronized signal with no jitter at all, and it is possible to prevent signal disturbance due to interference between sensors.

Here, the sensor drive buff 1z0DRV501 obtained in synchronization with each other is applied to the 1st and 3.5th sensors.
502 is supplied to the 2.4th sensor, and each sensor 25
, 28° 27.28.29, video signals v1 to v5 are independently output in synchronization with the drive pulse, and an independent amplifier circuit (preamplifier) 8 is provided for each channel as shown in FIG.
is amplified to a predetermined voltage value, and the coaxial cables 508 to 51
2 through 005541 timing shown in FIG. 2(b) -t-Vl, V3. V5(7) signal is EO5546(
7) A timing signal of V2°vl is sent out and input to the video processing unit.

Analog color image signals read by the aforementioned 5-chip equal-magnification color sensor are input to the analog signal processing circuit 9 shown in the first diagram for each channel. Since the signal processing circuits corresponding to each channel are the same circuit, the fifth
The process will be explained according to the processing block diagram shown in the figure, together with the timing chart shown in FIG.

The input analog color image signal is in the order of G −8−+R as shown in FIG. 5 for SiG, and 3072
In addition to the effective pixels, in front of the effective pixels there is an empty transfer section that is not connected to the photodiode of the 12-pixel color sensor, and then a dark output section (optical black) shielded with aluminum on the 24-pixel photodiode, 36 This is Composite No. 48, which is composed of a total of 3156 pixels, including a dummy pixel and 24 dummy pixels located after the effective pixel (see FIG. 4).

Analog color image 4M-? 5S t G A is input to the buffer 37 and subjected to impedance conversion. Next, the output signal S/l of the buffer 37 ((sample/hold) circuit 38 removes the reset part of the composite signal according to the S/11 pulse, and the S/11 output signal from which the waveform distortion caused by high-speed driving is removed. (6th
Figure (7) S/II O[JT] Since the point sequential color signal subjected to S/H contains unnecessary components at the frequency of the sampling pulse, a low pass filter (LPF) is next applied to remove them. ) Enter 39.

The point-sequential color signal from which unnecessary sampling frequency components have been removed is input to the amplifier 40, where it is amplified to a specified signal output, and at the same time removes DC level fluctuations of the analog color signal whose DC level fluctuates in an AC manner. The T level is clamped by a feedback clamp circuit 41 for fixing the OC level of the image signal at the optimum operating point of 40.

The feedback clamp circuit is composed of an S/H circuit 41a and a comparison amplifier 41b, and the S/11 circuit 41a detects the output level of the dark output part (optical black) of the analog color signal output from the amplifier 40. , and the GND level input to the inverting input terminal of the comparator amplifier 41b, and the difference is fed back to the amplifier 40, so that the dark output part of the output of the amplifier 40 is always GND level.
Fixed to ND.

Here, the signal D is a signal indicating the section of the dark output part of the analog color signal, and by supplying it to the S/11 circuit 41a, the DC level of the dark output part of the analog color signal is adjusted to the horizontal scanning period (IH). Detected once.

Further, this zero clamp circuit also has the purpose of eliminating input offset when the amplitude is varied in the amplitude control circuit that is entered next.

The signal in which the dark output portion of the analog color signal is zero-clamped is then input to an amplitude control circuit. Here, gain adjustment is performed for common point-sequential color signals under CPU control.

44 is a D/A converter, and the data bus 53 of the CPU
6, the data is set, and the D converter output Vo
ut becomes Vout=-Vrefl/N O (N<1, where N is the binary fractional value of the input digital code.

A voltage controlled resistor 43 is composed of a dual gate FET or the like, and its resistance value changes depending on the D/A output voltage. Initial data is set in the D/A converter 44 in advance, and the voltage control resistor 4 is set according to the D output at this time.
The resistance value (RVCR) of No. 3 is a certain fixed value. The gain of the amplifier 42 at this time is Av=l+Rf/RVCR. Here, If indicates the feedback resistance of the amplifier 42.

FIG. 7 shows the relationship between set data and gain of the D/A converter 44.

When the original scanning unit 3 reads the uniform white plate ^/
The data of the D/A converter 44 is transferred to the CP11 so that the D conversion output data (R, G, B) becomes a predetermined value.
By setting from the data bus 536 and using it in combination with amplitude variable means for each color signal in a point-sequential DC level control circuit to be described later, the R, G, and B signal levels of the point-sequential color signals are adjusted to achieve color balance. Take.

The level-determined point-sequential color signal is then sent to an amplifier 45.
The signal is input to the input signal, is amplified to a predetermined level, and at the same time is level clamped by the feedback clamp circuit 46. Since this feedback clamp system has exactly the same configuration as the feedback clamp circuit 41 in the previous stage, its operation will not be explained in detail here, but this is due to the amplitude control circuit using the D/A converter 44 in the previous stage. This is to remove the output offset caused by variable gain and fix the dark output portion of the analog color signal to zero level.

Again; an analog color signal clamped to a level is
Next, it is input to a point-sequential DC level control circuit.

Here, the level of each R, G, and B signal of the dot sequential signal is adjusted, and the DC level is adjusted dot sequentially for each R, G, and B under CPU control. The purpose of this is to shift the DC level of the read black level image signal in channel connection correction to be described later.

49a to 49c are analog switches composed of FETs, etc., and gate signals GSEL, BSEL, RSEL.
When the logic is "H", the analog switch becomes conductive and has a low impedance, and when the logic is "L", the analog switch becomes non-conductive and has a high impedance.

50a to 50c are multipliers, and as shown in FIG.
．． 559 and a resistor 557. of resistance value R. Resistor 556 with resistance value 2R, resistor R3 (558) and R4 (5
80) is a multiplier with all four quadrant modes,
According to the 8-bit digital data set from the CPU, a bipolar voltage is output to the stock shown in FIG. 10(b).

Ra, Rb, and Rc are resistors for varying the gain of the amplifier 47 for each G, B, and R in order to balance the color of the dot-sequential color signal, and when the GSEL signal is logic "H", the G
The gain for the signal is 1 + Ill / (R2+ RON+
Ra) = 8.

becomes. Here, 11ON is analog switch 49a-4
The resistance value when 9c is conductive is shown.

The same applies to other color signals B and H, and each gate signal B
When SEL and RSEL are logic “H”, the gain is 1 + R1/ (R2 + R4N + Rb
) = Aa1 + Ro1 / (R2+
RON, +RC) = AR. Now, the color ratio of the point sequential color signal of the image sensor is G:B:
Assuming that R=K:1:iL, in order to achieve color balance, the gain of the amplifier 47 for each G, B, and 11 signal is set to Aa:As:AR=t/:1:l.
/j! The resistors Ra, Rb, and Rc may be selected so that . Here, since the gain for each G, B, and R signal changes, the DC output voltage of the amplifier 47 is adjusted for each G, B, and B signal with respect to the CPU set data value of the multipliers 50a to 50c.
, to do the same for 11 signals, as shown in FIG. 10(a).

For example, the value of the resistor R3 shown in (b) for the G signal is (R3/2R) X [R1/(R2+ Ro,
, +na] ml, R3-(2R/ l1l) X (R2+ Ro
N+Ra), and for the other color signals B and H, the value of each R3 is R3-(2R/R1) X (R2+ RON+Rh)
R3-(2R/ R1) X (I12+ RON+
RC), the multipliers 50a to 50
For the CPU set data value of c, the DC of the amplifier 47
The output voltage is the same for each G, B, and R signal, and by changing the gain, the rate of change in DC level is the same for each G, B, and B signal.
.

There will no longer be any difference regarding R.

In this way, the color balance of each color signal is maintained by the dot-sequential DC level control circuit, and the DC level of the dot-sequential color signal is controlled in time series by the cPU set data.

The buffer 48 (see Figure 5) is an input buffer for the A/D converter 51, and is designed so that its output impedance is less than the reference resistance value of the A/D internal comparator that guarantees the linearity accuracy of the A/D converter. Configured as a low output impedance and high speed buffer.

Now, the point-sequential color signal that has been amplified and DC-clamped to a predetermined white level and black level is input to the A/D converter 51, becomes digital data 8/D OUT, and is then subjected to timing adjustment with the digital signal processing circuit. It enters a latch circuit 52 for reliable digital data transmission.

The latch output data latched at 0LACII CL is processed by the next digital signal processing circuit at 0LATGI ((:
By being latched with a latch clock having a polarity opposite to that of LK, digital data can be received with reliable timing. The same applies to the analog signal processing circuits of channels 2 to 5.

Next, the digitally converted dot-sequential color signals 513 to 517 of each channel enter the digital signal processing circuit IO, and the FIFO memory 11 performs image connection between channels, and the dot-sequential color signal of each channel is converted into R
, G, B three color parallel signals (518-520)
.

Next, the R, G, and B digital color signals enter signal processing circuits 13 to 15 (see FIG. 1) specific to this embodiment. Here, since the G, B, and R signal processing circuit configurations are completely the same, the G (X-il+ processing circuit) will be explained.

The digital signal is converted into an analog signal by a D/A converter 16 and then enters a low pass filter (LPF) 17. Here, the cutoff frequency is selected to be 172 of the D/A conversion clock.

The analog color signal that has passed through the LPF 17 enters the logarithmic conversion amplifier 18, where the luminance No. 18 data is converted into density signal data, and then converted again into a digital signal by the A/D converter 19. In other words, in this signal processing circuit ■3,
The missing signal component is reproduced by the LPF 17 with the precision of the first A/D converter 51, and is logarithmically converted in the analog domain.

Next, the R, G, and B digital color signals are subjected to black correction/
The white correction circuit 20 is entered. First, the black correction circuit will be explained. When the amount of light input to the sensor is small, the black level outputs of channels 1 to 5 have large variations between chips and pixels. If you output this image as it is (outputting the image, streaks and unevenness will occur in the data part of the image.Therefore, it is necessary to correct the output variation of this black part.Prior to the copying operation, the document scanning unit 3 is moved to the front edge of the document table. Move to the position of a black plate with uniform density placed in a non-image area, turn on a halogen lamp, and input a black level image signal to this circuit.One line of this image data is stored in a black level memory.
This becomes the black reference value (this is the black reference value import mode).

For example, if the data number i of the black level data DK(i) has a width in the longitudinal direction of A4 in the main scanning direction, it is 16 pel/
ff1II+ has 16x 297+nm = 4752 pixels/each color, but to cover the length, 61m
If 5 +n ccD depths are arranged in one line, then 1
6X 61n+mX 5 = 4880 pixels/i can take a value from 1 to 4880 corresponding to each color.

When reading an image, for example, in the case of a blue signal, Bin (i) - OK (i) is used for the black level data DK (i).
- A black correction output is obtained as [1out(i) (black correction mode). Similar control is performed for green Gin and red Rin, and black correction outputs Gout and Rout
becomes.

Next, a white level correction (shading correction) circuit will be explained. White level correction is based on the white data when moving the document scanning unit 3 to the position of a uniform white plate and irradiating it.
Corrects sensitivity variations in the illumination system, optical system, and sensor. The basic circuit configuration is the same as that of the black correction circuit, but the difference is that black correction uses a subtracter, whereas white correction uses a multiplier. During white correction, first, when the original scanning unit 3 is at the uniform white plate position (home position), that is, before copying or reading, the exposure lamp is turned on and one line of uniformly white level image data is scanned. white level memory.

For example, if it has an A4 longitudinal width in the main scanning direction, then
6pel/+am is 16x297mm = 4752 pixels, but the image data of the CCDI chip is 976 pixels (1
97 when configured with 6pel/mm x 61++on)
6 x 5 = 4880 pixels, that is, at least the capacity of the white level memory requires 4880 bytes, and if the i-th pixel white plate data is W (i), i = 1 to 4880
becomes. On the other hand, for the read value Din(i) of the normal image of the i-th pixel, the corrected image data is Dout(
i)=Din(i)xFFII/W(i), and white correction is performed for each color of green (G), blue (B), and red (R).

Three color image signals (52
4 to 526) then enter the image processing circuit 21, where the spectral characteristics of the color separation filter of the CCD sensor and the color toner (Y, M, C) to be transferred to the transfer paper in the color printer 2 are input to the image processing circuit 21.
A color correction circuit (input masking, output masking) that corrects unnecessary absorption characteristics of each color component image data Yi, M
i, Ci by Min(Yi, Mi, Ci) (Yi.

Mi, [: the minimum value of i) is calculated, and this is sumi (
The undercolor removal circuit (I) reduces the amount of each coloring material added according to the added black component.
The image is processed through the IcR) circuit (527 in Figure 1).
reference).

Next, the three color image signals are sent to the printer interface 22.
to go into. In addition to digital video signals, interface signals include a synchronization signal (I) in the image feeding direction (sub-scanning direction).
TOP), synchronization signal (BD) in the raster scan direction (main scan direction) that occurs once per raster scan,
Synchronous clock (VCL) for sending the digital video signal to the color printer section 2, Synchronous signal ()ISYNC) generated in synchronization with jitter-free VC:LK based on the BD signal, Half-duplex Contains signals for bidirectional serial communication (SRCOM). Image information and instructions are sent from the reader section to the printer section through these signal lines, and the printer section exchanges status information of the printer section, such as jam, out of paper, weight, etc.

Other Embodiments In the embodiments described above, logarithmic conversion amplification and A
/D conversion is performed, but even if a voltage is applied from an external circuit to the intermediate level of the A/D converter's reference voltage at multiple points, and the logarithmic conversion is approximated using a polygonal line shifted from the normal level, the same result will be obtained. can get. This is shown in FIG. FIG. 9 shows the human output characteristics of the A/D converter at this time.

[Effects of the Invention] As explained above, according to the present invention, the image connection deviation between channels due to the temperature characteristics of the logarithmic conversion circuit is eliminated, and the accuracy of the first ^/D conversion means is lower than that of the logarithmic conversion circuit. The gain is multiplied by the gain, which makes it possible to reduce the deterioration of precision especially for low-level signals, and it becomes possible to improve the gradation of black parts of the original image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video signal processing unit of a reader section in a digital color copying machine according to an embodiment of the present invention, FIG. 2(a) is a layout diagram of a color CCD sensor, and FIG. Figure 2 (a) is a signal timing diagram of each part, Figure 3 (a) is a diagram showing the CCD drive signal generation circuit (circuit inside the system control pulse generator 23), Figure 3 (b) is a diagram showing each timing signal. Waveform diagram, Figure 4 is a CCD drive timing diagram, Figure 5 is a block diagram showing one channel of the analog signal processing circuit 9 shown in Figure 1, Figure 6 is a signal timing of each part shown in Figure 5. 7 is a characteristic diagram of a voltage-controlled amplifier circuit, FIG. 8 is a block diagram of a video signal processing unit showing a second embodiment of the present invention, and FIG. Input of D converter 19
Output characteristic diagram, Figure 1θ (a) shows the multipliers 50a to 50c shown in Figure 5.
The circuit diagram of FIG. 1O(b) is a diagram showing the code table of FIG. 1O(a). 3... Original scanning unit, 4... Video processing unit, 16... D/8 converter, 17... LPF. 18... Logarithmic conversion circuit, l9... 8/D converter, 20... Black correction/white correction circuit. φΦ 8ψ Fig. 7 D/A〃Tochiri F Mouth Hex] o'y4 '/2 3/! I VREFVREF VREF ΔKatana@Pressure VREF Figure Tenitahas 536 Figure 10 (0) Figure 10 (b)

Claims (1)

[Scope of Claims] 1) In an image reading device that reads a medium having image information using an image sensor, a first A/D conversion means inputs color signals sequentially output from the image sensor of a plurality of channels; a synthesizing means connected after the first A/D converting means and for connecting images between each channel; a D/A converting means connected after the synthesizing means; a succeeding stage of the D/A converting means An image reading device comprising: a logarithmic conversion means connected to the logarithm conversion means; and a second A/D conversion means connected after the logarithm conversion means. 2) The image reading device according to claim 1, wherein the accuracy of the first A/D conversion means is higher than that of the second A/D conversion means. 3) input processing means that performs predetermined processing on image information read by the image sensor and converts it into a digital signal; D/A conversion means that converts the digital signal into an analog signal; An image reading device comprising: an image processing unit that performs logarithmic conversion processing. 4) The image reading device according to claim 3, wherein an analog-logarithmic conversion circuit is used as the image processing means. 5) The image reading device according to claim 3, wherein an A/D converter in which the intermediate level of the reference voltage is changed over a plurality of points is used as the image processing means.