JPH0265376A - Picture reading device - Google Patents

Abstract

PURPOSE:To attain picture reading with simple constitution by constituting a circuit system, which executes the analog signal processing of an image sensor output signal, by using an amplitude control circuit and a dot sequential direct current level control circuit. CONSTITUTION:In an analog signal processing circuit, impedance conversion is executed for an analog color picture signal SiGA in a buffer 30 and the reset part of a composite signal is removed in a sample/hold (S/H) circuit 31 according to an S/H pulse (S/HP.) Then, an S/H output signal, for which waveform distortion is removed, is obtained. An unnecessary component to be included in such an S/H dot sequential color signal is passed through an LPF32 and amplified in an amplifier 33. Simultaneously, the DC level fluctuation of the analog color signal, whose DC level is fluctuated like an AC, is removed and zero-level clamp is executed in a feedback clamp circuit 34. A signal, for which the zero-clamp is executed to the dark output part of the analog color signal in the feedback clamp circuit 34, is inputted to an amplifier 35 and gain control is executed by CPU control commonly for the dot sequential color signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device that reads images using an image sensor.

(Prior Art) Conventionally, as an image sensor used for high-speed image reading, there has been a method in which a stripe-type color filter is configured in an L-line image sensor and color separation signals are read out point-sequentially in a time-division manner. Yes.

Here, due to the spectral sensitivity characteristics of the color filter used to obtain the color separation signals and the spectral sensitivity characteristics of the image sensor itself, the spectral sensitivity characteristics are worse in the low wavelength region than in the high wavelength region. Therefore, the output signal from the image sensor when reading a reference image such as a standard white board does not become a point-by-point analog video signal with good color balance. Therefore, in order to ensure a sufficient dynamic range (S/N ratio) of the color separation signals, it is necessary to adjust the levels of each color separation signal in the analog video signal processing circuit.

To this end, in the past, point-sequential color signals were sampled and held (hereinafter referred to as S/H
) They were separated using a circuit and converted to simultaneous color No. 13, and signal processing such as amplification was performed on each, and color balance was adjusted by adjusting the level of each color separation signal when reading a standard white board. . In addition, each color separation circuit system has a DC level adjustment circuit, and by shifting the DC level of the black level signal read by the image sensor, the level between each channel of the image sensor composed of multiple image sensors is adjusted, and the channels are connected. was doing.

As many signal processing circuits as the number of decomposed signals are required after the S/H circuit. For example, when reading 297n+m of A4 longitudinal width with a sensor for one line, a silicon crystal type image sensor is suitable for high-speed reading, but due to manufacturing constraints, a silicon crystal type image sensor can print a long type with one chip. It is difficult to make, and requires several lines to be arranged as a single line sensor. In that case, the number of signal processing circuits after the S/) circuit of the same type will be required by multiplying the number of color separation signals by the number of chips that make up the image sensor, and the circuit configuration will have to be extremely large. There was a drawback that it had to be done.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image reading device that is capable of high-speed analog color image signal processing with a simple circuit configuration.

(Problem to be Solved by the Invention) However, in the conventional example described above, in order to separate the dot-sequential color signal into simultaneous color signals using the 578 circuit, the present invention solves the problem. An amplitude control means for controlling the amplitude of the dot sequential analog video signal as the dot sequential signal; and a DC level control means for controlling the DC level of the dot sequential analog video signal whose amplitude has been controlled by the S width control means as the dot sequential signal. Equipped with.

(Function) According to the present invention, the amplitude of the point-sequential analog video signal output from the image sensor is controlled as the point-sequential signal,
By controlling the DC level, dot-sequential color signals are separated into simultaneous color signals, and one system can be used for each chip making up an image sensor, for example, without having to adjust the amplitude and DC level in each circuit system. Since it is possible to adjust the amplitude and DC level of each color separation signal using only the 578 circuit and the subsequent signal processing circuit, the circuit configuration is simple and the apparatus can be made smaller.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of a signal processing block of a color image reading device. The original is first illuminated by an exposure lamp, and the reflected light from the original is separated into colors for each image by a color reading (CCD) sensor 6 in the original scanning unit 3 and read, and then adjusted to a predetermined level by an amplifier circuit (preamplifier) 8. amplified. 7 is a CCD driver that supplies pulse signals for driving the color reading sensor 6, and the necessary pulse source is generated by the system control pulse generator 16. Figure 2 shows the color reading sensor and drive pulses. FIG. 2(a) shows the color reading sensor used in this example, and this sensor has a reading speed of 62.5μa+(
1718II1m) as one pixel, 976 pixels, that is, one pixel is divided into three in the main scanning direction by G, B, and R as shown in the figure, so the total number of effective pixels is 1024X 3 = 3072. On the other hand, each C that makes up this sensor
CD chips 18 to 22 are formed on the same ceramic substrate, the 1st, 3rd and 5th (18, 20, 22) are on the same line LA, and the 2.4th (19, 21) are on the same line LA.
line (52.5 μm x 4 = 250.4111
) is placed on the line LB separated by a distance. This sensor scans in the direction of arrow ^L when reading a document. Of the five CCD chips, the 1st and 3.5th chips are driven by a drive pulse group (ODRV) 501, and the 2.4th chips are driven by a drive pulse group (EDRV) 502, independently and synchronously. 0φ included in ODRV501
Eφ1^, Eφ2A and εR5 included in IA, 0φ2^ and OR5 and EDRV502 are the charge transfer lock and charge reset pulses in each sensor, respectively, and the 1st and 3.5th CCD chips and the 2.4th CCD chip Due to mutual interference with the CCD chip and noise limitations, they are generated in perfect synchronization with green without any jitter. Therefore, these pulses are generated by one reference oscillation source (O5C117 (
(Fig. 1).

Figure 3 (a) shows 0DRV501 and EDRV502.
The circuit blocks included in the system control pulse generator 16 of FIG. 1 for all generation pulses are shown, and the third
Figure (b) shows a timing chart. single 05C1
The original clock (1:LKφ) generated from 7 is sent to frequency divider 2.
The clock (φ) 546 whose frequency is divided by 3 is the reference signal (SYNC) that determines the generation timing of 0DRV and EDRV.
2,5YNC3) is a clock that generates 5YNC3).
2, 5YNC3 is the zawata signal line 550 connected to the CPU bus
The output timing is determined according to the setting value of the presettable counter 24.25 set by 5YNC2.
, 5YNC3 initialize the frequency divider 26.27 and the drive pulse generator 28.29. In other words, using the horizontal synchronization signal (H5YNC) 544 manually inputted to this block as a reference, 0DRV5
The pulse groups of 01 and E[1RV502 noso t'L are obtained as synchronous signals with no jitter at all, and it is possible to prevent signal disturbance due to interference between sensor chips.

Here, sensor drive pulses 0 obtained in synchronization with each other
DRV501 has ED on the 1st and 3.5th sensor chips.
RV502 is supplied to the 2nd and 4th sensor chips, and each sensor chip +8, 19, 20, 21, 22>) independently outputs video signals v1 to v5 in synchronization with the drive pulse. As shown in FIG. 1, each channel is amplified to a predetermined voltage value by an independent amplifier circuit (preamplifier) 8, and then passed through coaxial cables 508 to 512.
Signals Vl, V3. V5 is shown in Figure 2 (b) (f) 0
O5538f) ') Imi: /g, signal V2. V
4 are respectively sent out at the timing of EO5543 and input to the video processing unit 4.

Conventionally, the color image signals obtained by manually reading the original inputted into the video processing unit 4 by dividing it into five parts in the main scanning direction are sent to the sample hold circuit S/H as shown in FIG. It is separated into three colors: (green) and B (blue). Therefore, Si (after being reduced to 1, 3x5=15
The system becomes an analog signal processing system. In Figure 5,
The input color image signal for one channel is sampled and held, amplified, and then manually input to the ^/D conversion circuit and multiplexed digital data 0LAT.
A resulting processing block diagram of CII OUT is shown. 6th
The timing chart is shown in the figure. Next, an explanation will be given of the analog signal processing circuit 9, which requires only one signal processing circuit system per channel by using the point sequential amplitude control circuit of the present invention.

Video signal Vl manually input to video processing unit 4~■
As shown in FIG. 1, signals 5 and 5 are respectively input to analog signal processing circuits 9 corresponding to each channel. Since the signal processing circuit 9 is the same circuit, channel 1 (chi)
The circuit will be explained in accordance with the block diagram of the signal processing circuit shown in FIG. 5 and the timing chart shown in FIG. 6.

As shown in FIG. 5, the video signal (analog color image signal) input to the buffer 30 is in the order of G→B→R as shown in FIG. The empty transfer part 9 which is not connected to the photodiode of the 12-pixel color sensor in front, then the dark output part (optical black) shielded with A pattern on the photodiode of 24 pixels, the dummy pixel of 36 pixels, and the 24-pixel after the effective pixel. This is a composite signal consisting of a total of 3156 pixels including dummy pixels.

As shown in FIG. 5, the analog color image signal 5iGA is input to the buffer 30 and subjected to impedance conversion.
Next, the sample/hold (S/H) circuit 31
The reset part of the composite signal is removed according to the H pulse (S/HP, ), resulting in an S/H output signal from which waveform distortion caused by high-speed driving is removed (S/HOU in Figure 6).
T). The point-sequential color signal subjected to S/■ contains unnecessary components at the frequency of the sampling pulse, so in order to remove them, a low-pass filter (L
PF) 32. The point-sequential color signal from which unnecessary sampling frequency components have been removed by the LPF 32 is sent to the amplifier 3.
3, is amplified to the specified output, and at the same time AC
In order to remove the OC level fluctuation of the analog color signal whose DC level fluctuates over time and to fix the DC level of the image signal at the optimum operating point of the amplifier 33, it is composed of an S/H circuit 34a and a comparison amplification Q 34b. The feedback clamp circuit 34 clamps the τ level. That is, the output level of the dark output part (optical black) in the analog color signal outputted from the amplifier 33 is detected by the S/H circuit 34a, and compared with the GND level manually applied to the negative input of the comparator amplifier 34b. , the difference signal is fed back to the amplifier 33, and the dark output portion of the output signal of the amplifier 33 is always fixed at the GND level. Here, the OK double signal input to the S/H circuit 34a is a signal indicating the section of the dark output part in the analog color signal, and by supplying it to the S/H circuit 34a, the DC level of the dark output part in the analog color signal is is detected once during the horizontal scanning period (IH).

The feedback clamp circuit 34 also has the purpose of eliminating manual offset when the amplitude is varied in the next stage amplitude control circuit. The dark output portion of the analog color signal is clamped by a feedback clamp circuit 34; the clamped signal is then input to an amplifier 35 constituting an amplitude control circuit. Here, gain adjustment is performed for common point-sequential color signals under CPU control.

37 is a D/A converter, which connects to the data bus 53 of the CPU.
3, and the output Vout of the D/A converter 37 is V6ut=-Vrefl/N O<N<
It becomes 1. N is the binary-fractional value of the input digital code. A voltage controlled resistor 36 is composed of a dual gate FET or the like, and its resistance value changes depending on the output voltage of the D/A converter 37. Initial data is set in the D/A converter 37 in advance, and the D/A converter 37 at this time
The resistance value (RVCR) of the voltage control resistor 36 is set to a certain fixed value depending on the output. The gain of the amplifier 35 at this time is ^v=1+Rf/RvcR, where Rf indicates the feedback resistance of the amplifier 35.

FIG. 7 shows the relationship between the set data of the D/A converter 37 and the gain of the amplifier 35. A/D conversion output data (R, G,
B) sets the data of the D/A converter 37 from the CPU data bus 533 so that it becomes a predetermined value,
In combination with a means for varying the amplitude of each color signal in a point-sequential DC level control circuit to be described later, the levels of the R9G and B signals of the point-sequential color signals are adjusted to achieve color balance.

The level-controlled point-sequential color signal from the amplifier 35 is then input to the amplifier 38, where it is amplified to a predetermined level, and at the same time, it is amplified by the feedback clamp circuit 39, which is composed of an S/H circuit 39a and a comparator amplifier 39b. Once the τ level is clamped, this feedback clamp circuit 39 has exactly the same configuration as the feedback clamp circuit 34 at the previous stage, so a detailed explanation of its operation will not be given here.
This is to remove the output offset caused by the gain variation in the amplitude control circuit according to No. 7, and fix the dark output portion of the analog color signal to zero level.

The analog color signal clamped again to the T level by the feedback clamp circuit 39 is then inputted from the amplifier 38 to a point sequential DC level control circuit having the following configuration. Here, the levels of each R, G, and B signal in the point sequential signal are adjusted, and the CPU
Through control, DC level adjustment is performed point-sequentially for each R5G and B. The purpose of this is to shift the DC level of the black level image signal read in channel connection correction to be described later. First, reference numerals 42a to 42c are analog switches, which are composed of FETs, etc., and are connected to the gate signal GS.
When EL, BSEL, and R5EL are at logic "H", they are conductive and have low impedance, and when they are at logic "L", they are non-conductive and have high impedance. 43
A to C are multipliers, which, as shown in FIG. 9(a), include a multiplying D/^ converter 550, operational amplifiers 552 and 556, a resistor 554 with a resistance value of R, and a resistor with a resistance value of 2.
Total 4 consisting of resistor R 553 and resistors R3 and R4
It is a quadrant mode multiplier and is set to 8 by the CPU.
According to the bit digital data, bipolar voltages are output as shown in FIG. 9(b).

In FIG. 5, Ra, Rh, and Rc are resistors for varying the gain of the amplifier 40 for each of G, B, and R in order to balance the color of the point-sequential color signal.

When the signal GSEL is at logic "H", the gain of the amplifier 40 for the G signal is 1 +RI/(R2+Ro, +R,) = 〇. Here, R2H indicates the resistance value when the analog switches 42a to 42c are conductive. The same goes for the other color signals B and H, and each gate signal BSEL.

The gain of the amplifier 40 when R5EL is logic “H” is 1 + R1/ (R2 + RoH + Rb) =^
.

1 +R1/(R2+RoH+Re) becomes electric AR. Now, assuming that the color ratio of the point-sequential color signals of the color reading CCD sensor is G:B:R=:1:It, in order to achieve color balance, the amplifier 4o for each G, B, and R signal must be The gain is AG: AB: 8R=1/k: 1:
The resistance values of the resistors R, Rb, and RC may be selected so as to be 1/1. Here, each G in the amplifier 40.

1 multiplier 43a because the gains for the B and R signals change.
For CPU set data values of ~43c, amplifier 40
In order to make the DC output voltage the same for each G, B, and R signal, the value of the resistor R3 shown in FIGS. 9(a) and (b) should be changed to (R3/2R) for the G signal, for example.
X [R1/ (R2+Ros +R-)]” From the relational expression 1, R3=(2R/R1)
Ra), and for the other color signals B and R, set the values of 13 each as R:l= (2R/R1) X (R2+RON +
Rh)R3= (2R/R1) x (R2+Ros
+Re), the multipliers 43a~
For a CPIJ set data value of 43c, amplifier 40
The DC output voltage is the same for each G, B, and R signal, and the DC level does not differ for each G, B, and R signal due to changing the gain of the amplifier 40. In this way, the color balance of each color signal is maintained by the dot-sequential DC level control circuit, and the DC level of the dot-sequential color (No. 3) is controlled in time series by the CPII set data.

Buffer 41 Li, A10 is a human-powered buffer for the transformer 44, and its output impedance is below the reference resistance value of the internal comparator of the A/D converter 44 that guarantees the linearity accuracy of the A/D converter 44. It is configured as a high-speed buffer with low output impedance.

Now, the dot-sequential color signal that has been amplified and DC-clamped to a predetermined white level and black level is turned into digital data A/D OUT by the ^/D converter 44, and is then processed by timing alignment with the digital signal processing circuit and reliable digital data. The data is input to the latch circuit 45 for data transmission.

In the latch circuit 45, the latch clock 0LACHC
The latch output data latched at L is latched by the next digital signal processing circuit using a latch clock of opposite polarity to 0LATCHCL, so that it is received at a reliable timing. The same applies to the analog signal processing circuits of channels 2 to 5 in FIG. 1.

Next, in FIG. 1, the dot sequential color signal 5 of each channel is digitally converted by the analog signal processing circuit 9
13 to 517 enter the digital signal processing circuit 10 and F
The iFo memory 11 connects images between channels, and the dot-sequential color signals of each channel are R, G, B.
Three color parallel signals 518 to 520 are formed.

The color signals 518 to 520 on which the images have been connected from the FiFo memory 11 enter the black correction/white correction circuit I3. First, the black correction circuit will be explained. When the amount of light applied to the sensor is small, the black level output of channels 1 to 5 varies greatly between two pixels on the chip. If an image signal is output without this change, streaks or unevenness will occur in the data portion of the image. Therefore, it is necessary to correct this variation in the output of the black part. Prior to the copying operation, the original scanning unit 3 is moved to the position of a black plate with uniform density placed in the non-image area at the tip of the original platen, the halogen lamp is turned on, and a black level image signal is manually input to the main circuit 13. do. This circuit 1 corresponds to one line of this image data (black level data).
3, and becomes the black reference value (hereinafter referred to as black reference value import mode).

The black level data oy, the number i of (+) data is, for example, if the sensor has a width in the longitudinal direction of A4 paper in the main scanning direction, 16 pel/ll 1 m = 16 x 297 mm =
There are 4752 pixels/each color, but in order to cover that length, five 611Ilffl CCD chips are arranged in one row.
If it is a line, 16 x 61 mm x 5 = 4880 pixels/i can take a value of 1 to 4880 corresponding to each color.

When reading an image, for example, in the case of a blue signal, Bin (i) - D is (i) = (1) for black level data D.
A point correction output is obtained as Bout(i) (black correction mode). Similarly, Green Gin, Red R4n
Similar control is performed for point correction outputs Gout and Ro
It becomes ut.

Next, the white level correction (shading correction) circuit will be explained.

White level correction is performed based on white data obtained when the document scanning unit 3 is moved to the position of a uniform white plate and irradiated, and correction is made for variations in sensitivity of the illumination system, optical system, and sensor. The basic circuit configuration is the same as that of the black correction circuit, but the difference is that black correction uses a subtracter, whereas white correction uses a multiplier. When the original scanning unit 3 is at the uniform white plate position (home position) during zero correction, that is, before copying or reading, the exposure lamp is turned on and one line of image data with a uniform white level is scanned. It is stored in the white level memory in the circuit 13.

For example, if the sensor has the width of A4 paper in the main scanning direction, it is 16 x 297 mm at 16 pel/mm.
= 4752752 pixels, if the image data of the CCDI chip is composed of 976 pixels (1apel/miX 61mm) each, it becomes 976 x 5 = 4880 pixels, that is, the capacity of at least the white level memory is 4880 bytes, and the i-th pixel white plate If the data is W (i), i=
1 to 4880. On the other hand, for W (+), the corrected image data for the read value Din(i) of the normal image of the i-th pixel is Dout(i) = Din(i
)xFF, 4/W(i), and white correction is performed for each color of green (G), blue (B), and red (fl). The three color image signals (521 to 523) subjected to black correction and white correction by the black correction/white correction circuit 13 are as follows:
Next, the image processing circuit 14 inputs a logarithmic conversion circuit that converts the luminance data into density data, spectral characteristic correction of the color separation filter of the CCD sensor, and color toner (Y, Y, M, C)
A color correction circuit (input masking output masking) that corrects unnecessary absorption characteristics of each color component image data Yi, M
i.

Min (Yi, Mi, Ci) (Yi
, Mf, and Ci), and converts it into black toner, adding black toner later. Undercolor removal (Ufl) reduces the amount of each coloring material added according to the added black component. :R) The image is processed through the circuit.

The three color image signals subjected to image processing by the image processing circuit 14 enter the printer interface 15. In addition to digital video signals, interface signals include a synchronization signal (ITOP) in the image feed direction (sub-scan direction), a synchronization signal (BD) in the raster scan direction (main scan direction) that occurs once per raster scan, and a digital video signal. Synchronous clock (V
CLK), VCLK without jitter based on 8D signal
The image information is transmitted from the reader section to the printer section 2 through these signal lines (525 to 530). An instruction is sent, and the printer unit sends printer status information such as jam or no FA.

Information such as weights is exchanged.

In the embodiment described above, the amplitude control circuit is configured as a variable gain amplifier circuit, but similar results can be obtained even if the amplitude control circuit is configured as an attenuator circuit. This is shown in FIG. In FIG. 8, the amplifier 3 of FIG.
5, a resistor RATT and a voltage control resistor 50 are used, and the other configuration is the same as that of FIG.

Furthermore, in the description of the above embodiments, a color image forming apparatus using electrophotography was used as an example, but it is not limited to electrophotography, and it is also possible to apply various recording methods such as inkjet recording and thermal transfer recording. . Further, although an example has been described in which the reading section and the image forming section are arranged close to each other as a copying apparatus, the present invention can of course also be applied to a format in which the reading section and the image forming section are separated and image information is transmitted through a communication line.

As explained above, by configuring the circuit system for analog signal processing of image sensor output signals using an amplitude control circuit and a point-sequential DC level control circuit, color signals are processed point-sequentially through the S/H circuit for each color. There is no need to separate simultaneous color signals and provide similar signal processing circuits for each color, and only one signal processing circuit system is required for each image sensor chip channel. It is possible to make the circuit size of the image sensor extremely small.

[Effects of the Invention] According to the present invention, an image reading device can be configured with a simple configuration, and the device can be downsized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the video signal processing unit of the reader section in the digital color copying machine of this embodiment, FIG. 2(a) is a layout diagram of the color CCD sensor, and FIG. ), Figure 3 (a) is a diagram showing the CCD drive signal generation circuit (circuit inside the system control pulse generator 16), Figure 3 (b) is a diagram showing the CCD drive signal generation circuit (circuit inside the system control pulse generator 16), Figure 3 (b) is 4 is a CCD drive timing diagram, FIG. 5 is a block diagram showing this embodiment of one channel of the analog signal processing circuit 9 of FIG. 1, and FIG. 7 is a characteristic diagram of a voltage-controlled m-width circuit, FIG. 8 is a block diagram of one channel of an analog signal processing circuit 9 showing another embodiment of the present invention, and FIG. (a)
is a circuit diagram of the multipliers 43a to 43C in FIG. 5, FIG. 9(b) is a diagram showing its code table, and FIG.
A block diagram showing a conventional example of one channel of the analog signal processing circuit 9 shown in the figure, and FIG. 11 is a signal timing diagram of each part of FIG. 10. ψφ 8φ F (I Hex) Figure 533 Figure (0) Figure (b)

Claims (1)

[Scope of Claims] An amplitude control means for controlling the amplitude of a point-sequential analog video signal from an image sensor as the point-sequential signal; and a point-sequential control for controlling the DC level of the point-sequential analog video signal amplitude-controlled by the amplitude control means. An image reading device comprising a direct current level control means for controlling the signal as it is.