JPH0453315B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention is applicable to display devices that extract image information drawn in an image memory and display it on a screen, such as a CRT terminal device, which can enlarge and display the image information. The present invention relates to an image display device.

2. Description of the Related Art In recent years, display devices using digital technology have been actively used to collect information and display data processing. These devices store image information in memory and sequentially retrieve and display it.

Hereinafter, a conventional display device with an enlargement function will be described with reference to the drawings. FIG. 9 is a schematic block diagram of a conventional image display device. 101 is a control circuit, 102 is an n-ary counter, 103 is an address generation circuit, 104 is a clock signal generation circuit,
105 is an image memory, 106 is an output control circuit, 1
07 is a CRT.

The operation of the enlargement function in the conventional image display device configured as described above will be described below. The control circuit 101 is the clock signal generation circuit 10
4 and the n-ary counter 102, the n-ary counter 102 is controlled by the control circuit 101.
The horizontal synchronizing signals issued to the CRT 107 are counted, and every time n horizontal synchronizing signals are counted, a signal instructing the update of the vertical address is given to the address generating circuit 103.
At this time, regarding the display of n horizontal scanning lines, since the vertical address of the address signal sent from the address generation circuit 103 to the image memory 105 is not changed, the n scanning lines display the same content in the horizontal direction. As a result, the data is enlarged and displayed n times in the vertical direction. A conventional technique is disclosed in, for example, Japanese Patent Publication No. 185082/1982.

Problems to be Solved by the Invention However, in the above configuration, the horizontal synchronizing signals are simply counted up to the enlargement magnification n and the vertical address is updated, so it cannot be enlarged when the scanning method is interlaced scanning. There was a problem.

In view of the above-mentioned problems, the present invention uses different scanning methods depending on the hardware functions of displays such as CRTs and LCDs, and visibility conditions such as flickering and resolution. The present invention also provides a display device that enables enlarged display.

Means for Solving the Problems In order to solve the above problems, the display device of the present invention continuously reads data from an image memory in which image information is stored corresponding to the display device. In an image display device, a counter for counting horizontal synchronizing signals according to the enlargement ratio, a clock delay circuit for delaying the counted signal according to the enlargement ratio, and a clock control circuit for dividing the clock are used. and a selector for switching the clock of the address counter of the image memory generated in accordance with each scanning method of interlaced scanning, repeated scanning, and overlapping scanning to read one horizontal direction information n times from the image memory in the vertical direction. By switching with this selector, it is possible to display the image enlarged by n times in the vertical direction in any of the above scanning methods.

Effects The present invention provides an image display device having the above-described configuration, which adds a function that can be enlarged even in the case of interlaced scanning by devising the address operation of the image memory, and which can enlarge it in any scanning method. Become.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. Here, the scanning method in which the scanning line of the next field is deflected between the scanning lines of the first field is interlaced scanning, and the scanning method in which the scanning line of the next field is deflected between the scanning lines of the first field is called interlaced scanning. A scanning method in which the same data is displayed is referred to as repeated scanning, and a scanning method in which the scanning line of the first field and the scanning line of the next field are deflected to the same position and displaying the same data is referred to as overlapping scanning. FIG. 1 is a schematic block diagram of an image display device according to an embodiment of the present invention. In Fig. 1, 1 is a horizontal synchronization generation circuit, 2 is an expansion coefficient setting circuit, 3 is a counter, 4 is a selector, 5 is an even/odd signal, and 6
is a clock delay circuit, 8 is a clock control circuit, and 9 is a clock delay circuit.
is a repetitive scan/interlaced scan signal, 10 is a selector, 11
12 is a Y address counter, 12 is an X address counter, 13 is an adder, 14 is an image memory, 15 is an output control circuit, and 16 is a CRT. The signal generated by the horizontal synchronization generating circuit 1 is input to a counter 3, a selector 4, and a clock delay circuit 6. The enlargement factor setting circuit 2 is for setting an enlargement factor that represents the enlargement factor when enlarging an integral number of times in the vertical direction.A counter 3 counts horizontal synchronizing signals according to this enlargement factor, and the counted signal is input to the selector 4. The selector 4 selects the horizontal synchronization signal and the signal obtained by counting it in response to the enlargement/non-enlargement switching signal from the enlargement coefficient setting circuit 2, and its output is inputted to the selector 10 as the repetitive scanning clock a. , is also input to the clock control circuit 8. The output of the clock control circuit 8 is input to the selector 10 as the clock c when no expansion is performed by interlaced scanning.
Further, the signal counted by the counter 3 is clocked by the clock delay circuit 6 according to the expansion coefficient set by the expansion coefficient setting circuit 2 and the even/odd number signal 5 based on the horizontal synchronization signal.
The delayed and synthesized signal is input to the selector 10 as clock b when expanded by interlaced scanning.
The selector 10 selects the input according to the enlargement/non-enlargement switching signal from the enlargement count setting circuit 2 and the repetitive scanning/interlace scanning signal 9, and its output is input to the Y address counter 11. The outputs of the Y address counter 11 and the X address counter 12 are added by an adder 13 and inputted to the image memory 14 as an address. It is input into the image memory 14 as an address. Output data from the image memory 14 is displayed on the CRT 16 through an output control circuit 15.

The operation of the image display device of this embodiment configured as described above will be described below. First, a method of accessing the image memory 14 in which image information during the display period is written will be described. Here, the display screen has, for example, 256 pixels in the horizontal direction, and one data in the image memory 14 is allocated to each pixel.
The display is assumed to be a CRT, and addresses in the image memory 14 are manipulated so that data is displayed on the screen by sequentially extracting data according to the beam scanning of the CRT 16. The address corresponds to the X-Y coordinates, where the origin is at the top left of the screen, the horizontal direction to the right is the X direction, the vertical direction is downward to the Y direction, and the unit length is 1 pixel. The address is expressed in hexadecimal) and the address in the Y direction (00~). Note that the address when accessing the surface image memory 14 is obtained by setting the X address as the lower byte and the Y address as the upper byte. When the image is not enlarged by repeated scanning, the selector 4 and selector 10 select the output from the horizontal synchronization generating circuit 1, which becomes the clock for the Y address counter 11. That is, as shown in FIG. 2, within the same field, the Y address is sequentially updated by +1 every time the horizontal synchronizing signal clock is input, that is, for each scanning line, and predetermined data is obtained. Here, FIG. 2 shows the relationship between the scanning line period of each of the first field and the next field and the address of the image memory 14 that provides the horizontal direction data corresponding to that scanning line, in the case where the field is not enlarged by repeated scanning. It is something.

Next, when enlarging by repeated scanning, the enlargement coefficient n
The signal counted by the counter 3 of horizontal synchronization signals up to (an integer) passes through the selectors 4 and 10 and becomes the clock for the Y address counter, so that the Y address is updated by +1 for each n scanning line in the same field. Therefore, the data in the horizontal direction is displayed repeatedly n times, that is, it is enlarged n times in the vertical direction. Here, FIG. 3 shows the scanning line period of each of the first field and the next field in the case of three-fold enlargement in the vertical direction by repeated scanning, and the Y address of the image memory 14 that provides horizontal data corresponding to the scanning line. This shows the relationship between In addition,
The difference between overlapping scanning and repetitive scanning is whether the scanning line of the first field and the scanning line of the next field are deflected to the same position, and the principle of the magnification function in overlapping scanning is exactly the same as in repetitive scanning. It is. Regarding deflection, output control circuit 1
Do it in 5.

The operation when not enlarging with interlaced scanning is as follows. The horizontal synchronizing signal passes through the selector 4 and enters the clock control circuit 8, where one clock of the horizontal synchronizing signal is divided by a gate circuit into two clocks each having a clock width less than 1/2 of the original clock width. The clock signal passes through the selector 10 to the Y address counter 1.
It is counted as 1. In other words, as shown in Figure 4, the Y address is + for each horizontal display period in the same field.
It will be updated in increments of 2. Here, Figure 4 shows
This figure shows the relationship between the scanning line period of each of the first field and the next field and the address of the image memory 14 that provides horizontal direction data corresponding to the scanning line, in the case of not enlarging by interlaced scanning.
In addition, in the first field, the Y address starts from 00,
The clock control circuit 8 is set to start from 01 in the next field.

When enlarging by interlaced scanning, the operation is slightly different when enlarging by an even number and when enlarging by an odd number. First, when enlarging the clock by an even number of 2m (m is an integer), the clock delay circuit 6 delays the signal obtained by counting the horizontal synchronization signal by 2m by the counter 3 by m clocks of the horizontal synchronization signal, and the signal obtained by counting the horizontal synchronization signal by 2m. The logical sum signal is sent to the Y address counter 11.
By setting the clock to , the Y address of both the first field and the next field is updated by +1 every m scanning lines, and the Y address is expanded by 2m in the vertical direction. In the case of interlaced scanning, the Y address is set to start from 00 for both the first field and the next field. Next, when enlarging the clock by an odd number (2m+1), the signal obtained by counting the horizontal synchronizing signal (2m+1) by the counter 3 in the clock delay circuit 6 is converted into the horizontal synchronizing signal (m+1) by the even/odd signal 5.
The signal delayed by clocks, and in the next field, the signal delayed by m clocks of the horizontal synchronizing signal, and the counted signal (2m+1) are ORed together. Note that the even/odd signal 5 is a signal for distinguishing between the first field and the next field. By using this OR signal as the clock for the Y address counter 11, in the first field (m+
1) Y address is updated by +1 for each scanning line of m and m, respectively, and in the next field, m and (m
+1) Each scanning line has a Y address of +
1 is updated. In other words, if you look at a single display screen that combines the first field and the next field,
1 horizontal display information is always displayed from the top of the screen (2m + 1)
Since the image is repeated vertically twice, it is possible to obtain a screen that is enlarged (2m+1) times in the vertical direction. Here, FIG. 5 shows the scanning line period of each of the first field and the next field, and the image memory 14 which provides horizontal data corresponding to the scanning line, in the case of 5 times enlargement in the vertical direction by interlaced scanning.
This shows the relationship between the Y address and the Y address.

FIG. 6 is a schematic block diagram of a clock delay circuit and its peripheral circuits according to an embodiment of the present invention.
51 is a horizontal synchronization signal, 52 is an expansion coefficient signal, 53
is a counting signal, 54 is a clock signal of the Y address counter, 5 is an even/odd signal, 55 is an adder, 5
6 is a counter, 57 is an OR gate, and 6 is a clock delay circuit. This clock delay circuit works when enlarging by interlaced scanning, and its structure and operation will be explained below. First, when expanding by an even number of 2m (m is an integer), an adder 55 divides the expansion coefficient by 2, or m, based on the expansion coefficient signal 52, creating a signal that is m, and inputs this signal to the counter 56 as input data. do. Note that the even/odd signal 5 is not used when enlarging by an even number. Then, the count signal 53, which is a signal obtained by counting the horizontal synchronization signal by 2m, is used as a load signal for the counter 56, and the horizontal synchronization signal 51 is used as the load signal for the counter 56.
6 clock, the counter 5 is loaded at the m-th clock of the horizontal synchronizing signal 51.
6 carry out signal is output. Here, it is assumed that the counter 56 outputs a carry-out signal at the n-th clock after loading when n is input data. This signal and the count signal 53 are logically summed by an OR gate 57, and a signal is used as a clock signal 54 of the Y address counter. Horizontal synchronization signal 51 and counting signal 5 when expanded 4 times in the vertical direction
3. A time chart of the carry-out signal of the counter and the clock signal 54 of the Y address counter is shown in FIG.

As can be seen from Figure 7, the first field,
The Y address of each of the following fields is updated by +1 every m clocks of the horizontal synchronizing signal 51, that is, every m scanning lines, and is enlarged by 2m in the vertical direction. In addition, in the case of interlaced scanning, the first field,
Set the Y address for both of the following fields to start from 00.

Next, when enlarging by an odd number (2m+1),
Based on the expansion coefficient signal 52 and the even/odd signal 5, an adder 55 adds 1 to the expansion coefficient in the first field.
In the next field, 1 is subtracted from the expansion factor to create a signal that is divided by 2, which is m, and these are input data of the counter 56. do. And horizontal sync signal (2m+1)
The counted signal 53 is sent to the counter 56.
By using the horizontal synchronization signal 51 as the clock of the counter 56, the first field is loaded at the (m+1)th clock of the horizontal synchronization signal 51, and the next field is the mth clock of the horizontal synchronization signal 51.
A carry-out signal from the counter 56 is output at the clock. These signals and the count signal 53 are logically summed by an OR gate 57, and a signal is used as a clock signal 54 of the Y address counter. Horizontal synchronization signal 51 and counting signal 5 when expanded 5 times in the vertical direction
3. Time charts of the carry-out signal of the counter and the clock signal 54 of the Y address counter in the first field and the next field are shown in FIG.

As can be seen from Figure 8, in the first field, the Y address is updated by +1 for every (m+1) and m scanning lines, and in the next field, for every m and (m+1) scanning lines, respectively. +1
It will be updated one by one. In other words, when looking at one display screen that combines the first field and the next field, one horizontal display information is always (2m+) from the top of the screen.
1) Since the image is repeated vertically, a screen enlarged (2m+1) times in the vertical direction can be obtained.

Effects of the Invention As is clear from the above description, the present invention is applicable to devices that display images by continuously reading data from a memory in which image information is previously stored. The reading address from the memory is manipulated according to each scanning method, and one horizontal direction information is repeatedly retrieved from the memory n times in the vertical direction, thereby being able to be enlarged by n times in the vertical direction. Therefore, beam scanning as described above can be considered depending on the hardware configuration of the display such as CRT or LCD, or the visibility requirements such as flickering and resolution, but for either method, it is possible to The display device of the present invention can perform enlarged display and is highly versatile.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an image display device according to an embodiment of the present invention, FIG. 2 is a diagram showing the correspondence between scanning lines and addresses of the image memory when the image is not enlarged by repeated scanning, and FIG. A diagram showing the correspondence between the scanning line and the Y address of the image memory when the image is enlarged three times in the vertical direction by repeated scanning, and Figure 4 shows the correspondence between the scanning line and the address of the image memory when it is not enlarged by interlaced scanning. FIG. 5 is a diagram showing the correspondence between the scanning line and the Y address of the image memory when vertically expanded five times by interlaced scanning, and FIG. 6 is a diagram showing the clock delay circuit according to the above embodiment and its A schematic block diagram of the peripheral circuit. Fig. 7 is a time chart of each signal when magnified by 4 times by interlaced scanning. Fig. 8 is a time chart of each signal when enlarged by 5 times by interlaced scanning. Fig. 9. 1 is a schematic block diagram of a conventional image display device with an enlargement function. 1...Horizontal synchronization generation circuit, 3...Counter, 5
...even/odd signal, 6...clock delay circuit,
8...Clock control circuit, 9...Repetitive scanning/interlaced scanning signal, 11...Y address counter, 14...
...image memory, 55...adder, 56...counter.

Claims (1)

[Claims] 1. An image memory storing image information corresponding to a display device, a counter for counting horizontal synchronization signals according to the enlargement ratio, and delaying the counted signal according to the enlargement ratio. A clock delay circuit for dividing the clock, a clock control circuit for dividing the clock, and generation of interlaced scanning, repetitive scanning, and overlapping scanning, respectively, so that one horizontal direction information is read out from the image memory n times in the vertical direction. An image display device comprising a selector for switching the clock of an address counter of the image memory, and by switching with the selector, the image is enlarged by n times in the vertical direction and displayed in any of the above scanning methods. 2. An image display device according to claim 1, which has a clock delay circuit equipped with an adder that outputs a signal according to the expansion factor, a counter that counts horizontal synchronization signals using the signal, and a gate circuit for signal synthesis. .