JPH0452748A - Bus arbitration circuit - Google Patents

Abstract

PURPOSE:To easily change the bus using priority among plural data transfer modules in accordance with the bus using situations by providing a priority converting register which stores previously plural priorities of bus using request signals outputted from those modules into a storage means and enables the selection of these priorities. CONSTITUTION:A priority converting register 7 is provided to store the data for conversion of the bus using priority together with a storage means 8 which stores previously the bus using grant data. The bus using requests 101 - 10n given from the data transfer modules 1.1 - 1.n are held in the corresponding bits of a bus using request register 2. The output of the register 2 and the value of the register 7 are inputted to a priority storage means 8 as address, and the data on the priority are outputted. These data are held by a bus using grant register 4 and the bus using grant signals 111 - 11n are outputted to the modules 1.1 - 1.n respectively. Thus it is possible to flexibly cope with the change of the bus using priority without increasing the hardware capacity.

Description

TECHNICAL FIELD The present invention relates to a bus arbitration circuit, and more particularly to a bus arbitration circuit that grants bus usage permission to bus usage requests from a plurality of data transfer modules according to predetermined priorities. be.

Prior Art An example of a conventional bus arbitration circuit of this type is shown in FIG. In the figure, a plurality of data transfer modules 1 to 1.n each make a bus use request (REQ) 10 to a common bus 1.
1 to 10n. These bus use requests 101-I
on is set and held in the corresponding bits of the request register 2, respectively.

These held outputs 401 to 40n are respectively input to the priority order determining means 3, and bus use permission (ACK) 411 to 4in is given to the bus use request according to a predetermined priority order.
are generated and set and held in the corresponding bits of the bus permission register 4, respectively.

A circuit example of the priority determining means 3 is shown in FIG.
In this example circuit, a circuit for determining priorities for bus use requests 401, 402, and 403 from three data transfer modules is shown.

These bus use requests 401 to 403 are handled by the AND gate 31
- 33 are each staffed by one person, and there are 40 requests to use the bus.
1 and 402 are inputs of the inverters 34 and 35, respectively.

The output of the inverter 34 becomes the external power of the ant gate 3', 2.33, and other requests 402 other than the own request 401,
403 is suppressed.

Further, the output of the inverter 35 becomes another input of the AND gate 33, and other requests 403 are suppressed.

The outputs of these AND gates 131-33 become the bus usage permission 411-4in, which is set in the bus usage permission FiJ register 4 in Figure 3, and the output of this register 4 becomes the final bus usage permission 111-lln. .

For example, when bus use requests 401 to 403 are input at the same time, bus use request 401 is inputted to AND gate 31 and at the same time is inverted by inverter 34 to close ant gates 32 and 33. Therefore, the bus use fraud is delayed by the output 411 of ANDKATE 31, and register 4
is held and output as a lotus usage permit 61111.

The output bus use permission 111 resets the bus use request register 2 that holds the own bus use request, and at the same time is input to the OR gate 5 to suppress the bus use request 315.
generate.

When the transfer module 1 that has received the bus usage permission 111 completes the data transfer, it outputs a transfer completion signal 211 to the OR gate 6. As a result, the bus use permission register reset signal 320 is generated from the OR gate 6, and all the registers 4 are reset. In response to this, the lotus use inhibition 315 generated by the OR gate 5 is canceled, and other bus use requests can be accepted.

In such conventional bus arbitration circuits, the priority order determining means 3 for arbitrating bus use requests is constituted by hardware such as AND gates and inverter gates, so the priorities are not fixed at the time of circuit design. Put it away. Therefore,
If you want to change the priority order or add a data transfer module, you need to either change the configuration 31 or prepare a separate priority order determination means.

Furthermore, as the number of data transfer modules increases, the amount of hardware for the circuit that determines the priority order also increases.

Purpose of the Invention Therefore, the present invention has been devised to eliminate such drawbacks of the conventional ones.The purpose of the present invention is to solve the problem of increasing the amount of hardware due to changes in priorities, addition of data transfer modules, etc. An object of the present invention is to provide a bus arbitration circuit that can be flexibly handled.

According to the present invention, there is provided a bus arbitration circuit for granting permission to use a bus according to a predetermined priority order in response to bus use requests from a plurality of data transfer modules, the circuit comprising: a priority conversion register for storing conversion data of the data transfer module, and a storage means which uses the contents of the priority conversion register and the bus use request from the data transfer module as address inputs and stores bus use permission data in advance; A bus arbitration circuit is obtained, characterized in that bus use permission is granted based on bus use permission data read from the storage means.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 3 are designated by the same reference numerals. Bus usage requests 101 to 1 from multiple data transfer modules 1-.1 to 1.n
10n are held in the corresponding bits of the bus use request register 2, respectively. The output of this register 2 and the value of the priority conversion register 7 (the value of the conversion register 7 can be changed by software or other means depending on the usage status of the bus) are manually entered into the priority storage means 8 as an address. , the data as a priority is output.

The output data is held in the bus permission register 4, and bus permissions 111 to lln are output to the data transfer module, respectively. The bus use permissions 111 to lln reset their own bus use request registers 2, and at the same time input the bus use request suppression IL signal 315 as the highest address of the priority notation means 8 by the OR gate 5 which is the request signal suppression means. This will suppress other bus usage requests.

When the data transfer module to which the bus use permission has been output completes the data transfer and outputs the transfer end signals 211 to 21n to the OR gate 6 which is the termination means, the bus use permission register reset signal 320 is input to the bus use permission register 4. This register 4 is reset by this. Therefore, the bus usage permissions 111 to Iln held are “0”.
゛Cleared.

At the same time, the inhibition signal 315 for other bus use requests becomes "0", and other bus use requests are accepted.

FIG. 2 shows the relationship between addresses of the RAM 8, which is a priority storage means, and stored data. In this example, there are three data transfer modules, and the value of the conversion register is “
00'', the bus use request IDI (
REQI), bus use request 102 (R2O3), and bus use request 103 (REQ3), and when the value of the conversion register is "01", the priority is set from the highest to bus use request 102.
(R2O3), bus use request 103 (REQ3), bus use request 1.01 (REQI), and when the value of the conversion register is "10", the priority is set from the highest to bus use request 103 (REQ3), bus use request 101 (REQ
I) This is an example in the case of bus use request 102 (R2O3).

A rewritable RAM is used as the priority storage means 7, and bus use requests (REQI° to REQ n') from the data transfer modules 1 to 1 and n are made to correspond to the addresses thereof, and bus use permissions 411 to 41n ( ACK l”〜A
Priority order is determined by writing CK n') as data in advance.

In addition, the most significant bit of the address is an input signal from the OR gate 5 which is the inhibiting means, and when "1" is reached, the RA
By writing a pattern that sets the output of M8 to "0", that is, a inhibited state, it is possible to inhibit other bus usage requests.For example, if the value of conversion register 7 is set to "00", Bus use request (REQ3) is in RAM
8, the address becomes "000001" and "001" is output as the permission signal.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. For example, the value of conversion register 7 is set to “00” and the priority order is set to bus use request 101 (REQI).
, bus use request 102 (R2O3), and bus use request 103 (REQ3), it is assumed that these three bus use requests are input at the same time. These bus use requests are held in the bus use request register 2 as address inputs of the RAM 8.

Next, since the priority pattern data written in advance, that is, the address is "000111", the output signal "1.
00'' is outputted by the RAM 8 as bus use permission and held in the bus use permission register 4.

This register 4 outputs a bus use permission 111 to the data transfer module 1 that sent the bus use request signal REQI. In addition, the bus use permission 111 is manually inputted to the OR gate 5, which is a deterrent means, and becomes a deterrent signal 315, and the RAM
By being given as the most significant bit of 8, other bus usage requests during data transfer are suppressed.

When the data transfer module that has received permission to use the bus, that is, the data transfer module 1 that has generated the bus use request 101 (REQI), completes the data transfer, a termination signal 211 or the OR gate 6, which is the termination means, manually outputs a termination signal 211, and permission to use the bus is issued. By outputting the register reset signal 320 and resetting the register 4, the inhibit signal 315 of the OR gate 5 is canceled and other bus use request signals are accepted.

Although a RAM is used as an example of the priority storage circuit 8, it is of course possible to use a ROM.

As described in detail, according to the present invention, when setting the priority means to arbitrate bus use request signals output from a plurality of data transfer modules, a plurality of priority orders are stored in advance in the storage means. , and by providing a conversion register that allows selection of a plurality of priority orders, it becomes possible to easily change the priority order according to the usage status of the bus. Furthermore, by changing the data stored in the priority storage means, it is possible to easily deal with the case where a data transfer module is added.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure shows the addresses of the RAM 8 in FIG. 1 and the symbols of the main parts of the stored data.
...Conversion register 8...Priority storage I? AM applicant Kofu E
J Denkirin Shiki Company

Claims (1)

[Claims] (1) A bus arbitration circuit that grants bus usage permission to bus usage requests from a plurality of data transfer modules according to a predetermined priority order, which has priority for storing converted data for converting the priority order. a priority conversion register, the contents of this priority conversion register, and a bus use request from the data transfer module as address inputs;
a storage means in which bus use permission data is stored in advance;
A bus arbitration circuit characterized in that bus use permission is granted based on bus use permission data read from the storage means.