JPH0451573A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0451573A JPH0451573A JP2160603A JP16060390A JPH0451573A JP H0451573 A JPH0451573 A JP H0451573A JP 2160603 A JP2160603 A JP 2160603A JP 16060390 A JP16060390 A JP 16060390A JP H0451573 A JPH0451573 A JP H0451573A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- tunnel
- tunnel insulating
- film thickness
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000005530 etching Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- 238000010306 acid treatment Methods 0.000 abstract description 6
- 238000011282 treatment Methods 0.000 abstract description 5
- 238000004140 cleaning Methods 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 4
- 238000001039 wet etching Methods 0.000 abstract description 4
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 3
- 229910000510 noble metal Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000010970 precious metal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
乙の発明は、半導体装置の製造方法に関するもので、Ｆ
ｌ ｏ ｔ ｏ ｘ （Ｆｌｏａｔｉｎｇ ｔｕｎｎ
ｅｌ ｏｘｉｄｅ）構造およびＭ Ｎ ＯＳ （Ｍｅｔ
ａｌ Ｎ１ｔｒｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ）
構造を有するＥＥＦＲＯＭに関するものである。[Detailed description of the invention] [Industrial field of application] The invention of B relates to a method of manufacturing a semiconductor device, and
Floating tune
el oxide) structure and M N OS (Met
al N1tride Sem1conductor)
The present invention relates to an EEFROM having a structure.
第４図は、例えば２トランジスタ・セルを有する従来か
らのＦｌｏｔｏｘ型ＥＥＰＲＯＭ、、１％リセルの簡易
断面構造である。左部トランジスタが不揮発性メモリ・
トランジスタである。この不揮発性メモリ・トランジス
タをさらに拡大した例を第５図に示す。FIG. 4 shows a simplified cross-sectional structure of a 1% recell, a conventional Flotox type EEPROM having, for example, two transistor cells. The left transistor is a non-volatile memory
It is a transistor. A further enlarged example of this nonvolatile memory transistor is shown in FIG.
これらの図において、１は制御ゲート、２はフローティ
ングゲ−１・、３は選択ゲー１−１４は１−ンネル絶縁
膜、５はｎ＋拡散層、６はトンネルｎ領域、７はｐ型シ
リコン基板、８はゲート絶縁膜、１４は制御ゲート１と
フローティングゲート２の間の絶縁膜である。In these figures, 1 is a control gate, 2 is a floating gate 1, 3 is a selection gate 1-14 is a 1-channel insulating film, 5 is an n+ diffusion layer, 6 is a tunnel n region, and 7 is a p-type silicon substrate. , 8 is a gate insulating film, and 14 is an insulating film between the control gate 1 and the floating gate 2.
従来はトンネル領域のトンネル開孔部形成のために、ド
ライまたはウェットエツチングによりゲ−Ｉ−絶縁膜８
に１−ンネル開孔部を生成し、その後、レジス１−残渣
除去のための酸処理および残存酸化膜除去のためのフッ
酸処理２ならびに熱処理時に重金属とか貴金属などがシ
リコン中に拡散されるのを避けるための王水処理などの
、いわゆる洗浄処理をなし、かつこれらの各処理後にあ
って、トンネル開孔部に対して）・ンネル絶縁膜４を形
成させるようにしている。そして、フローティングゲ１
−２上に絶縁膜１４を介し、制御ゲート１を形成するわ
けであるが、その絶縁膜１４の形成においてＥＥＰＲＯ
Ｍの信頼性特性の１つであるリテンンヨン（Ｒｅｔｅｎ
ｔｉｏｎ ：保持特性）向上のために、約１０００℃の
高温化を有した酸化法が用し）られている。Conventionally, in order to form a tunnel opening in a tunnel region, a gate I-insulating film 8 is etched by dry or wet etching.
1-Nel pores are formed in the silicon, and then, during resist 1-acid treatment to remove residue, hydrofluoric acid treatment 2 to remove residual oxide film, and heat treatment, heavy metals, precious metals, etc. are diffused into the silicon. A so-called cleaning treatment such as an aqua regia treatment is performed to avoid this, and after each of these treatments, a tunnel insulating film 4 is formed on the tunnel opening. And floating game 1
The control gate 1 is formed on the -2 through the insulating film 14, and in the formation of the insulating film 14, the EEPRO
Retenyon, one of the reliability characteristics of M.
In order to improve the retention characteristics, an oxidation method with a high temperature of about 1000° C. is used.
そして、この従来例による装置構造での動作について述
べると、まず、装置のフローテイングゲト２に１０ Ｍ
Ｖ ／ ｃ ｒｎ程度の正の高電界をかけることによ
り、トンネル絶縁膜４が見掛は上薄くなる。この減少を
エネルギバッド図で示すと第６図のようになる。Then, to describe the operation of the device structure according to this conventional example, first, a 10 M
By applying a high positive electric field of about V/crn, the tunnel insulating film 4 becomes thinner in appearance. This decrease is shown in an energy budget diagram as shown in FIG.
第６図において、９は伝導帯、１ｏは価電子帯、１１は
電子である。すなわち、この第６図から明らかなように
、電子１１は薄くなったｌ・ンネル絶縁膜４の禁制帯を
トンネリングして、フローティングゲート２の伝導帯９
に流入する。つまり、この状態がいわゆる“書き込み状
態″である。In FIG. 6, 9 is a conduction band, 1o is a valence band, and 11 is an electron. That is, as is clear from FIG. 6, the electrons 11 tunnel through the forbidden band of the thinned l-channel insulating film 4 and reach the conduction band 9 of the floating gate 2.
flows into. In other words, this state is the so-called "write state."
そしてまた、前記状態とは反対にフローティングゲート
２に１０ Ｍ Ｖ ／ ｃ ｍ程度の負の高電界をかけ
ると、ここでもトンネル絶縁膜４が見掛は上薄くなり、
これを同様にエネルギバンド図で示すと・第７図のよう
になって、電子１１ζよ薄くなつたＩ、ンネル絶縁膜４
の禁制帯をトンネリングし、ｎ″拡散層５の伝導帯９に
流入する。つまり、この状態が、いわゆる゛′消去状態
″である。Contrary to the above state, when a high negative electric field of about 10 MV/cm is applied to the floating gate 2, the tunnel insulating film 4 also becomes thinner in appearance.
If this is similarly shown in an energy band diagram, it will become as shown in Figure 7.
tunnels through the forbidden band of and flows into the conduction band 9 of the n'' diffusion layer 5. In other words, this state is the so-called ``erased state.''
従来構造のＥＥＰＲＯＭメモリセルのトンネルｎ−領域
４は以上のようにして形成されるが、ここでのＥＥＰＲ
ＯＭにあっては、トンネル絶縁膜４におけるピンホール
などの欠陥よりも電界ス）・Ｌ・スによる疲労、いわゆ
るＴ Ｄ Ｄ Ｂ （Ｔｉｍｅ Ｄｅｐｅｎｄｅｎｔ
Ｄｉｅｌｅｃｔｒｉｃ Ｂｒｅａｋｄｏｗｎ）が問題と
なり、これが書き換え時のしきい値電圧差（ウィンドウ
）縮め、繰り返し書き換え可能な回数を制限することに
なるという不都合があった。The tunnel n-region 4 of the conventionally structured EEPROM memory cell is formed as described above.
In OM, fatigue caused by electric fields S), L, and S, so-called TDD B (Time Dependent
Dielectric breakdown (Dielectric Breakdown) is a problem, which reduces the threshold voltage difference (window) during rewriting and limits the number of times that rewriting can be repeated.
とりわけ、トンネル絶縁膜４の上層部は、トンネル絶縁
膜４の形成終了時のトンネル絶縁膜生成装置への０２の
巻き込みや、汚染モードの影響等で膜質は良質とはいい
難い。In particular, the film quality of the upper layer of the tunnel insulating film 4 is not good due to the involvement of 02 in the tunnel insulating film generation device when the formation of the tunnel insulating film 4 is completed and the influence of the contamination mode.
この発明は、上記のような問題点を改善するためになさ
れたもので、その目的とするところは、ＥＥＰＲＯＭに
おいてＴＤＤＢ特性を向上させた１−ンネル絶縁膜を形
成できるようにした半導体装置の製造方法を提供するこ
とにある。This invention was made to improve the above-mentioned problems, and its purpose is to manufacture a semiconductor device in which a 1-channel insulating film with improved TDDB characteristics can be formed in an EEPROM. The purpose is to provide a method.
この発明に係る半導体装置の製造方法は、フロティング
ゲーｌ−とトンネル領域との間のトンネル絶縁膜の形成
に際し、トンネル絶縁膜を目標膜厚より厚ぺ形成した後
、目標膜厚までエッチバックするようにしたものである
。In the method for manufacturing a semiconductor device according to the present invention, when forming a tunnel insulating film between a floating gate L- and a tunnel region, the tunnel insulating film is formed to be thicker than a target film thickness, and then etched back to the target film thickness. It was designed to do so.
この発明においては、トンネル絶縁膜を目標膜厚より厚
く生成した後、目標膜厚までエッチバックすることから
、■−ンネル絶縁膜形成終了時のトンネル絶縁膜生成装
置への０２の巻き込みや、汚染モードの影響等の中で形
成された良質でない１−ンネル絶縁膜上層部を除去でき
、いわゆる電界ストレスに伴う疲労（ＴＤＤＢ）を早め
るファクタを大幅に除去することができる。In this invention, after the tunnel insulating film is formed thicker than the target film thickness, it is etched back to the target film thickness. It is possible to remove the upper layer of the 1-channel insulating film which is not of good quality, which is formed under the influence of the mode, and it is possible to significantly remove the factors that accelerate fatigue due to so-called electric field stress (TDDB).
以下、この発明について説明する。 This invention will be explained below.
第１図はこの発明の一実施例を示す要部断面図で、第５
図に対応する図である。第１図において、４は！・ンネ
ル絶縁膜、５はｎ ’ｒ拡散層、６はトンネルｎ−領域
、７はｐ型シリコン基板、８はデー１−絶縁膜である。FIG. 1 is a cross-sectional view of essential parts showing one embodiment of the present invention, and FIG.
FIG. In Figure 1, 4 is! - tunnel insulating film, 5 is an n'r diffusion layer, 6 is a tunnel n- region, 7 is a p-type silicon substrate, and 8 is a D1- insulating film.
トンネル絶縁膜４は目標膜厚のものであり、１２はフィ
ールド酸化膜であり、１３は前記トンネル絶縁膜４をさ
らに厚く生成させた過剰生成１〜ンネル絶縁膜である。The tunnel insulating film 4 has a target thickness, 12 is a field oxide film, and 13 is an over-produced tunnel insulating film 1 to which the tunnel insulating film 4 is made thicker.
この第１図は目標膜厚より厚いトンネル絶縁膜形成時点
の概要構成を示す断面図である。FIG. 1 is a sectional view showing a schematic configuration at the time of forming a tunnel insulating film thicker than the target film thickness.
第２図はこの実施例によるトンネル開孔部形成からフロ
ーティングゲ−１・形成までの製造プロセスの要部を示
すフローチャートである。また、第３図は、第２図のフ
ローに対応する半導体装置の要部の断面図である。なお
、第２図、第３図における（１）〜（５）は各ステップ
を示す。トンネル開口部の形成後、直ちに目標膜厚であ
るトンネル絶縁膜４を形成していた従来例に対して、こ
の実施例では、ドライまたはウエッｌ〜エツチングによ
りゲト絶縁膜８にトンネル開孔部８ａを穿孔させるとと
もに（１）、その後、レジスト残渣除去のための酸処理
および残存酸化膜除去のためのフッ酸処理ならびに熱処
理時に重金属とか貴金属などがシリコン中に拡散される
のを避けるための王水処理などのいわゆる洗浄処理をな
しく２）、続し）で、第１図（こ示すように、穿孔され
たトンネル開孔部に目標膜厚より厚いｌ・ンネル絶縁膜
（４＋１３１を形成させる（３）。次に、目標膜厚であ
るトンネル絶縁膜４までドライエツチング、あるいはウ
ェットエツチングでエッチバックさせる。いわば過剰生
成トンネル絶縁膜１３を除去してしまう（４）。その後
、フローティングゲート２を生成するものである（５）
。FIG. 2 is a flowchart showing the main parts of the manufacturing process from the formation of the tunnel opening to the formation of the floating gate 1 according to this embodiment. Further, FIG. 3 is a sectional view of a main part of the semiconductor device corresponding to the flow shown in FIG. 2. Note that (1) to (5) in FIGS. 2 and 3 indicate each step. In contrast to the conventional example in which the tunnel insulating film 4 having the target thickness is formed immediately after the tunnel opening is formed, in this embodiment, the tunnel opening 8a is formed in the gate insulating film 8 by dry or wet etching. (1), followed by acid treatment to remove resist residue, hydrofluoric acid treatment to remove residual oxide film, and aqua regia to prevent heavy metals and precious metals from diffusing into the silicon during heat treatment. In order to eliminate the so-called cleaning process such as 2), continued), an L-channel insulating film (4+131) thicker than the target film thickness is formed in the drilled tunnel opening (as shown in FIG. 1). 3) Next, the tunnel insulating film 4 having the target thickness is etched back by dry etching or wet etching.In other words, the excess tunnel insulating film 13 is removed (4).Then, the floating gate 2 is formed. (5)
.
たとえば、１００人のトンネル絶縁膜４を得るために、
まず、１２０人生成し、２０人エッチＡツクし、その後
、フローティングゲート２を形成したものがその例であ
る。For example, to obtain 100 tunnel insulating films 4,
For example, first, 120 people were generated, 20 people were etched, and then the floating gate 2 was formed.
上述のように、トンネル絶縁膜４の形成の際、目標膜厚
より厚く生成した後、目標膜厚までエッチバックして過
剰生成ｌ・ンネル絶縁膜１３を除去してしまうというプ
ロセスは、トンネル絶縁膜４の形成終了時のトンネル絶
縁膜生成装置へのＯ２の巻き込みや、汚染モードの影響
等の中で形成された良質てないトンネル絶縁膜上層部を
除去でき、いわゆる電界ストレスに伴う疲労（ＴＤＤＢ
）を早めるファクタを大幅に除去してしまう作用がある
。なお、動作に関しては、前述した“従来技術の動作″
と全く同様である。As mentioned above, when forming the tunnel insulating film 4, the process of forming the tunnel insulating film 4 thicker than the target thickness and then etching back to the target film thickness to remove the excess formed tunnel insulating film 13 is a process that It is possible to remove the poor quality upper layer of the tunnel insulating film formed under the influence of O2 intrusion into the tunnel insulating film generation device and the contamination mode at the end of the formation of film 4, and to reduce fatigue due to so-called electric field stress (TDDB).
) has the effect of largely eliminating the factors that accelerate the process. Regarding the operation, the above-mentioned "operation of the conventional technology"
It is exactly the same.
なお、上記の実施例では、過剰生成トンネル絶縁膜１３
を除去した後、フローテイングゲ−１−２を形成させる
例を示したが、過剰生成１−ンネル絶縁膜１３を除去し
た後、洗浄処理を施し、フローティングゲート全形成し
てもかまわない。Note that in the above embodiment, the excessively produced tunnel insulating film 13
Although an example has been shown in which the floating gates 1-2 are formed after removing the overly produced 1-channel insulating film 13, a cleaning process may be performed to form the entire floating gate.
以上説明したように、この発明は、フローティングゲー
トとトンネル領域との間のトンネル絶縁膜の形成に際し
、トンネル絶縁膜を目標膜厚より厚く形成した後、目標
膜厚までエッチバックするようにしたので、トンネル絶
縁膜形成終了時の１−ンネル絶縁膜生成装置への０２の
巻き込みや、汚染モードの影響の中で形成された良質で
ないトンネル絶縁膜上層部が除去されるので、ＴＤＤＢ
特性を向上させたトンネル絶縁膜を形成でき、そのため
信頼性を向上できる効果がある。As explained above, in the present invention, when forming the tunnel insulating film between the floating gate and the tunnel region, the tunnel insulating film is formed to be thicker than the target film thickness, and then etched back to the target film thickness. , since the upper layer of the poor-quality tunnel insulating film formed under the influence of contamination mode and the entanglement of 02 into the 1-channel insulating film generation device at the end of tunnel insulating film formation is removed, TDDB
A tunnel insulating film with improved characteristics can be formed, which has the effect of improving reliability.
【図面の簡単な説明】
第１図はこの発明の半導体装置の製造方法の一実施例を
説明するための要部の断面図、第２図は、第１図の半導
体装置の製造プロセスを説明するフローチャー１・、第
３図は、第２図のフローに対応する半導体装置の要部の
断面図、第４図は従来の半導体装置を示す要部の断面図
、第５図は、第４図のトンネル開孔領域を拡大した断面
図、第６図はＥＥＰＲＯＭの書き込み状態を表したエネ
ルギバンド図、第７図はＥＥＰＲＯＭの消去状態を表し
たエネルギーバンド図である。
図において、１は制御ゲート、２はフローティングゲー
ト、３は選択ゲート、４はｌ・ンネル絶縁膜、５はｎ＋
拡散層、６はトンネルｎ−領域、７はｐ型シリコン基板
、８はゲート絶縁膜、９は伝導帯、１０は価電子帯、１
１は電子、１２はフィールド酸化膜、１３は過剰生成ｌ
・ンネル絶縁膜である。
なお、各図中の同一符号は同一または相当部分を示す。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a sectional view of essential parts for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. Flowchart 1. FIG. 3 is a cross-sectional view of the main part of a semiconductor device corresponding to the flow of FIG. 2, FIG. 4 is a cross-sectional view of the main part of a conventional semiconductor device, and FIG. 4 is an enlarged cross-sectional view of the tunnel opening region, FIG. 6 is an energy band diagram showing the write state of the EEPROM, and FIG. 7 is an energy band diagram showing the erase state of the EEPROM. In the figure, 1 is a control gate, 2 is a floating gate, 3 is a selection gate, 4 is an l-channel insulating film, and 5 is an n+
diffusion layer, 6 a tunnel n-region, 7 a p-type silicon substrate, 8 a gate insulating film, 9 a conduction band, 10 a valence band, 1
1 is electron, 12 is field oxide film, 13 is excess generation l
・It is a channel insulation film. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
絶縁膜の形成に際し、前記トンネル絶縁膜を目標膜厚よ
り厚く形成した後、前記目標膜厚までエッチバックする
ことを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, comprising: forming a tunnel insulating film between a floating gate and a tunnel region, forming the tunnel insulating film thicker than a target thickness, and then etching back to the target thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160603A JPH0451573A (en) | 1990-06-19 | 1990-06-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160603A JPH0451573A (en) | 1990-06-19 | 1990-06-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451573A true JPH0451573A (en) | 1992-02-20 |
Family
ID=15718516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2160603A Pending JPH0451573A (en) | 1990-06-19 | 1990-06-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451573A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100316086B1 (en) * | 1992-06-01 | 2002-03-21 | 클라크 3세 존 엠. | High density 'electrically erasable and programmable read only memory (EEPROM)' cell arrays with new programming means and methods of making them |
| KR100316089B1 (en) * | 1992-06-01 | 2002-03-21 | 클라크 3세 존 엠. | " EEPROM " omitted |
-
1990
- 1990-06-19 JP JP2160603A patent/JPH0451573A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100316086B1 (en) * | 1992-06-01 | 2002-03-21 | 클라크 3세 존 엠. | High density 'electrically erasable and programmable read only memory (EEPROM)' cell arrays with new programming means and methods of making them |
| KR100316089B1 (en) * | 1992-06-01 | 2002-03-21 | 클라크 3세 존 엠. | " EEPROM " omitted |
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