JPH0451116A - Method for driving active matrix liquid crystal display panel - Google Patents

Method for driving active matrix liquid crystal display panel

Info

Publication number
JPH0451116A
JPH0451116A JP16019490A JP16019490A JPH0451116A JP H0451116 A JPH0451116 A JP H0451116A JP 16019490 A JP16019490 A JP 16019490A JP 16019490 A JP16019490 A JP 16019490A JP H0451116 A JPH0451116 A JP H0451116A
Authority
JP
Japan
Prior art keywords
signal
common
amplitude
gate pulse
common signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16019490A
Other languages
Japanese (ja)
Inventor
Fumihiro Ogawa
小川 文博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16019490A priority Critical patent/JPH0451116A/en
Publication of JPH0451116A publication Critical patent/JPH0451116A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a picture of uniform and good quality without having unequal luminance by changing the low level of a gate pulse signal with the in- phase with a common signal by as much as the amplitude of the pulse of the common signal. CONSTITUTION:The offset level of the common signal impressed to a common electrode is set the same as the offset level of the amplitude generated in a pixel electrode and the amplitude V/20 thereof is set at 0.5V. The polarity of the common signal is inverted with each of frames. The level of +15v of the gate pulse signal is for turning on a thin-film transistor (TFTR) and the amplitude is supplied through the drain bus line via the TFTR to the pixcel electrode during the time of this +15V. The low levels -4V, -5V of the gate pulse signal maitain the TFTR in an off state and the video signal is held. The low level of the gate pulse signal changes with the in-phase by as much as the same amplitude in synchronization with the inversion of the common signal (a) in this case. The generation of the unequal luminance by each line is obviated in this way.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、アクティブマトリクス液晶表示パネルの駆動
方法に関し、特に薄膜トランジスタのゲート・ソース間
の容量によるフィールド・スルーの影響をなくす駆動方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving an active matrix liquid crystal display panel, and more particularly to a method for driving an active matrix liquid crystal display panel that eliminates the influence of field through due to capacitance between the gate and source of a thin film transistor.

〔従来の技術〕[Conventional technology]

この種のアクティブマトリクス液相表示パネルの駆動は
、ドレインバスラインに交流の映像信号を印加し、ゲー
トバスラインに線順次走査でゲートパルス信号を印加し
、共通電極に共通信号を印加することにより行なってい
るが、従来の駆動方法では、ゲートパルス信号のローレ
ベルは、薄膜トランジスタアレイのオフ状態を保つもの
で一定値である。
This type of active matrix liquid phase display panel is driven by applying an AC video signal to the drain bus line, applying a gate pulse signal to the gate bus line in line sequential scanning, and applying a common signal to the common electrode. However, in the conventional driving method, the low level of the gate pulse signal maintains the off state of the thin film transistor array and is a constant value.

第3図は、薄膜トランジスタをアクティブ素子として用
いた液晶表示パネルの1ビクセル分の等価回路を示した
もので、ゲートバスライン6によりオン/オフの制御さ
れる薄膜トランジスタ5を介し、トレインパスライン7
より供給される映像信号により、ビクセル電極9aと、
共通電極りb間に電荷が蓄積される。第4図は、各部の
電圧波形を示したもので、第4図(a)は、ゲートノく
スラインに印加されるゲートパルス信号を示す。デユー
ティ分の1のパルスを印加することにより、第3図のビ
クセル電極9aに電圧が発生するが、これは、薄膜トラ
ンジスタのオフ状態(第4図(a>の信号のローレベル
)で保持される。共通電極9bに印加される共通信号は
、第4図(C)に示すようにフレーム毎に極性が反転す
るが、これによって、ビクセル電極9aの電圧は、第4
図(b)に示すように変化する。この変化量Δ■′は、
第3図に示す薄膜トランジスタの寄生容量10により一
部の電荷がフィールド・スルーされるので、共通信号の
変化量Δ■よりも小さい。以上を図示すると、ビクセル
電極−共通電極間の電位は、第4図(d)のようになる
FIG. 3 shows an equivalent circuit for one pixel of a liquid crystal display panel using thin film transistors as active elements.
By the video signal supplied from the vixel electrode 9a,
Charge is accumulated between the common electrodes b. FIG. 4 shows voltage waveforms at various parts, and FIG. 4(a) shows a gate pulse signal applied to the gate cross line. By applying a pulse equal to 1 duty, a voltage is generated at the vixel electrode 9a in FIG. 3, but this voltage is maintained in the off state of the thin film transistor (the low level of the signal in FIG. 4 (a>)). The polarity of the common signal applied to the common electrode 9b is reversed every frame as shown in FIG.
It changes as shown in Figure (b). This amount of change Δ■′ is
Since part of the charge is field-through due to the parasitic capacitance 10 of the thin film transistor shown in FIG. 3, the amount of change in the common signal is smaller than the amount of change Δ■. To illustrate the above, the potential between the vixel electrode and the common electrode is as shown in FIG. 4(d).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上述べたように、従来の駆動方法は、共通信号のフィ
ールド毎の反転により一部の電荷が逃げ、ビクセル電極
−共通電極間の電圧が下がる。
As described above, in the conventional driving method, a part of the charge escapes due to field-by-field inversion of the common signal, and the voltage between the vixel electrode and the common electrode decreases.

この電圧が下がる時間は、フレーム反転後ゲート電極間
が印加されるまでの時間であり、従って、液晶表示パネ
ルの上部と下部では印加電圧に大きな開きがある。これ
を軽減する手段として、寄生容量を小さくすることが考
えられるが、寄生容量を小さくすると薄膜トランジスタ
のオン抵抗が大きくなる関係があるので限度がある。
The time for this voltage to fall is the time after frame inversion until the voltage is applied between the gate electrodes, and therefore there is a large difference in the applied voltage between the upper and lower parts of the liquid crystal display panel. One way to reduce this problem is to reduce the parasitic capacitance, but there is a limit because reducing the parasitic capacitance increases the on-resistance of the thin film transistor.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は薄膜トランジスタをアクティブ素子として用い
た液晶表示パネルのドレインバスラインに交流の映像信
号を印加し、ゲートバスラインに線順次走査でゲートパ
ルス信号を印加し、共通電極に前記交流の映像信号と逆
相の共通信号を印加するアクティブマトリクス液晶表示
パネルの駆動方法において、前記ゲートパルス信号のロ
ーレベルが前記共通信号のパルスの振幅分だけ前記共通
う信号と同相で変化するようにしたことを特徴とする。
The present invention applies an AC video signal to the drain bus line of a liquid crystal display panel using a thin film transistor as an active element, applies a gate pulse signal to the gate bus line in line sequential scanning, and applies the AC video signal and the AC video signal to a common electrode. A method for driving an active matrix liquid crystal display panel in which a common signal of opposite phase is applied, characterized in that the low level of the gate pulse signal changes in phase with the common signal by the amplitude of the pulse of the common signal. shall be.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(d)は、本発明の第1の実施例の駆動
方法の電気信号波形を模式的に示したものである。薄膜
トランジスタとしてアモルファス・シリコンの薄膜トラ
ンジスタを用いた場合について説明する。第1図(a)
の共通電極に印加する共通信号は、そのオフセットレベ
ルをビクセル電極に発生する映像信号のオフセットレベ
ルと同じにし、その振幅ΔV/2を0.5■にする。共
通信号の極性は、フレーム毎に反転される。ゲートパル
ス信号(b)、(c)、(d)は、それぞれ1番目、i
番目及び最後のn番目のゲートバスラインに印加される
。ゲートパルス信号の+15Vのレベルは、薄膜トラン
ジスタをオンにするためのもので、この+15Vの時間
の間、ドレインバスラインを通じ映像信号が薄膜トラン
ジスタを介してビクセル電極に供給される。ゲートパル
ス信号のローレベル−4V、−5Vは、薄膜トランジス
タをオフ状態に保つもので、前述の供給された映像信号
が保持される0図で示すように、共通信号(a)の反転
に同期してゲートパルス信号のローレベルは、同じ振幅
だけ同相で変化する。
FIGS. 1(a) to 1(d) schematically show electrical signal waveforms of the driving method according to the first embodiment of the present invention. A case will be described in which an amorphous silicon thin film transistor is used as the thin film transistor. Figure 1(a)
The common signal applied to the common electrode has the same offset level as the offset level of the video signal generated at the vixel electrode, and has an amplitude ΔV/2 of 0.5■. The polarity of the common signal is reversed every frame. The gate pulse signals (b), (c), and (d) are the first and i
It is applied to the th and last nth gate bus line. The +15V level of the gate pulse signal is for turning on the thin film transistor, and during this +15V time, the video signal is supplied to the vixel electrode via the thin film transistor through the drain bus line. The low level -4V, -5V of the gate pulse signal is to keep the thin film transistor in the off state, and as shown in the above-mentioned figure 0 where the supplied video signal is held, it synchronizes with the inversion of the common signal (a). The low level of the gate pulse signal changes by the same amplitude and in phase.

第2図(a)、(b)は、本発明の第2の実施例の電圧
信号波形を示す。第1の実施例では、共通信号をフレー
ム毎に反転したが、本実施例では、ライン毎に共通信号
を反転させる。共通信号(a)は、ライン毎に極性が反
転し、かつフレーム毎に極性を逆相にする。1番目のゲ
ートパルス信号(b)のローレベルは、共通信号(a>
に同期し変化する。本実施例の場合も、第1の実施例と
同様に共通信号の極性反転毎の電荷のフィールドスルー
がないので、ライン毎の輝度ムラが生じない効果がある
FIGS. 2(a) and 2(b) show voltage signal waveforms of a second embodiment of the present invention. In the first embodiment, the common signal is inverted for each frame, but in this embodiment, the common signal is inverted for each line. The polarity of the common signal (a) is inverted for each line, and the polarity is reversed for each frame. The low level of the first gate pulse signal (b) is the common signal (a>
changes in sync with. In the case of this embodiment as well, as in the first embodiment, there is no charge field-through every time the polarity of the common signal is reversed, so there is an effect that brightness unevenness from line to line does not occur.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、共通電極に印加される共
通信号の振幅と同じ幅だけ、ゲートバスラインに印加す
るパルス信号のローレベルを共通信号と同期して同じ幅
だけ同相で変化させることにより、共通電極とゲート電
極間にあるビクセル電極の電位も同じ幅だけ変化するの
で、結果としてビクセル電極と共通電極間の電圧は変化
しない。従って、液晶表示パネルの上と下で同じ電圧が
印加されるので、輝度ムラのない均一な良質の画面が得
られる効果がある。
As explained above, the present invention allows the low level of the pulse signal applied to the gate bus line to be changed in phase by the same width in synchronization with the common signal by the same width as the amplitude of the common signal applied to the common electrode. As a result, the potential of the vixel electrode between the common electrode and the gate electrode changes by the same width, and as a result, the voltage between the vixel electrode and the common electrode does not change. Therefore, since the same voltage is applied to the top and bottom of the liquid crystal display panel, it is possible to obtain a uniform, high-quality screen without uneven brightness.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は、本発明の第1の実施例の駆動
方法を説明するための駆動信号波形を示す図、第2図(
a)、(b)は、本発明の第2の実施例の駆動信号波形
を示す図、第3図は、アクティブマトリクス液相パネル
の1ビクセル分の等価回路、第4図(a)〜(d)は、
従来の駆動方法を説明するための波形を示した図である
。 5・・・薄膜トランジスタ、6・・・ゲートバスライン
、7・・・ドレインバスライン、8・・・共通電極ライ
ン、9a・・・ビクセル電極、9b・・・共通電極、1
0・・・ゲート・ビクセル間の寄生容量。
FIGS. 1(a) to 1(d) are diagrams showing drive signal waveforms for explaining the driving method of the first embodiment of the present invention, and FIG.
a) and (b) are diagrams showing drive signal waveforms of the second embodiment of the present invention, FIG. 3 is an equivalent circuit for one pixel of an active matrix liquid phase panel, and FIGS. d) is
FIG. 3 is a diagram showing waveforms for explaining a conventional driving method. 5... Thin film transistor, 6... Gate bus line, 7... Drain bus line, 8... Common electrode line, 9a... Vixel electrode, 9b... Common electrode, 1
0... Parasitic capacitance between gate and vixel.

Claims (1)

【特許請求の範囲】[Claims] 薄膜トランジスタをアクティブ素子として用いた液晶表
示パネルのドレインバスラインに交流の映像信号を印加
し、ゲートバスラインに線順次走査でゲートパルス信号
を印加し、共通電極に前記交流の映像信号と逆相の共通
信号を印加するアクティブマトリクス液晶表示パネルの
駆動方法において、前記ゲートパルス信号のローレベル
が前記共通信号のパルスの振幅分だけ前記共通信号と同
相で変化することを特徴とするアクティブマトリクス液
晶表示パネルの駆動方法。
An alternating current video signal is applied to the drain bus line of a liquid crystal display panel using a thin film transistor as an active element, a gate pulse signal is applied to the gate bus line in line sequential scanning, and a signal having a phase opposite to the alternating current video signal is applied to the common electrode. An active matrix liquid crystal display panel driving method in which a common signal is applied, wherein the low level of the gate pulse signal changes in phase with the common signal by an amount of the amplitude of the pulse of the common signal. driving method.
JP16019490A 1990-06-19 1990-06-19 Method for driving active matrix liquid crystal display panel Pending JPH0451116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16019490A JPH0451116A (en) 1990-06-19 1990-06-19 Method for driving active matrix liquid crystal display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16019490A JPH0451116A (en) 1990-06-19 1990-06-19 Method for driving active matrix liquid crystal display panel

Publications (1)

Publication Number Publication Date
JPH0451116A true JPH0451116A (en) 1992-02-19

Family

ID=15709849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16019490A Pending JPH0451116A (en) 1990-06-19 1990-06-19 Method for driving active matrix liquid crystal display panel

Country Status (1)

Country Link
JP (1) JPH0451116A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362689A (en) * 1991-06-10 1992-12-15 Sharp Corp Driving circuit for display device
JP2007298799A (en) * 2006-05-01 2007-11-15 Hitachi Displays Ltd Liquid crystal display device
WO2020149000A1 (en) * 2019-01-17 2020-07-23 株式会社ジャパンディスプレイ Display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362689A (en) * 1991-06-10 1992-12-15 Sharp Corp Driving circuit for display device
JP2007298799A (en) * 2006-05-01 2007-11-15 Hitachi Displays Ltd Liquid crystal display device
WO2020149000A1 (en) * 2019-01-17 2020-07-23 株式会社ジャパンディスプレイ Display device
US11587522B2 (en) 2019-01-17 2023-02-21 Japan Display Inc. Display device

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