JPH0450756B2 - - Google Patents

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Publication number
JPH0450756B2
JPH0450756B2 JP56088398A JP8839881A JPH0450756B2 JP H0450756 B2 JPH0450756 B2 JP H0450756B2 JP 56088398 A JP56088398 A JP 56088398A JP 8839881 A JP8839881 A JP 8839881A JP H0450756 B2 JPH0450756 B2 JP H0450756B2
Authority
JP
Japan
Prior art keywords
layer
intrinsic layer
photoelectric conversion
sih
intrinsic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56088398A
Other languages
Japanese (ja)
Other versions
JPS57202788A (en
Inventor
Masatoshi Kitagawa
Shinichiro Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56088398A priority Critical patent/JPS57202788A/en
Publication of JPS57202788A publication Critical patent/JPS57202788A/en
Publication of JPH0450756B2 publication Critical patent/JPH0450756B2/ja
Granted legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24Deposition of silicon only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は、アモルフアス光電変換素子の製造方
法に関する。 本発明は、光電変換効率を決定する重要な要素
である光伝導層として使用される真性層のフエル
ミ準位を連続に変化させることにより、その真性
層そのものに内蔵電場を作り、光電変換効率を向
上させる光電変換素子の製造方法を提供するもの
である。 従来、アモルフアスシリコン光電変換素子の真
性層は、フエルミ準位を示す活性化エネルギーは
一定の条件で作製するため、およそ0.7〜0.9eVの
内の一つの値を取つている。そのため、光が真性
層に入射し、電子、正孔対が生成されても拡散に
より電子、正孔が正極と負極にそれぞれ分離され
るまでに再結合が行なわれる確率が高かつた。そ
こで、これを防止するために、真性層に微量の不
純物を徐々に添加して真性層に内蔵電場を作る考
えがあつた。すなわち、内蔵電場によつて電子、
正孔がそれぞれ正極、負極側に向かつて加速さ
れ、再結合される前に電極から取り出される確率
が高くなる。 しかし、このように不純物の添加によつてフエ
ルミ準位を制御する方法では実際に不純物を添加
する場合、不純物添加量を非常に微量な値とせね
ばならないため、その制御が極めて困難である。
また例えばホウ素やリン元素を添加してフエルミ
準位を制御した場合、光伝導度が極端に低下し真
性層としての役割が果たせなくなる欠点がある。 第1図は、不純物の添加によつて光伝導度が大
幅に低下することを示した図である。横軸がジボ
ラン(B2H6)とシランガス(SiH4)の体積比、
縦軸が堆積された層の光伝導度を示す。シランガ
スに対するジボランの体積比を大きくしてゆく
程、即ちホウ素の添加が大きい程、堆積層の光伝
導度が低下していることがわかる。 本発明は、不純物を添加することなく、真性層
を堆積させる際に工夫を与えることによつて上記
従来の問題点を改善するものであり、本発明の光
電変換素子の製造方法の実施例を説明する。 第2図は、発明のアモルフアス光電変換素子の
製造方法を実施する装置の構成例を示す。同図に
示すように、グロー放電反応管1を、排気口2よ
りロータリポンプ等(図示せず)のポンプによつ
て排気した後、0.1〜1Torrの圧力になるまで、
SiH4及びH2を主成分とするガス、さらに適当に
H2で希釈したジボラン及びホスフインガスを、
ガス導入口3より反応管1内に導入する。なお同
図において4は電極、5はヒータ付基板ホルダ兼
電極であり6はSiH4ボンベ、7はH2ガスボンベ、
8はジボランガスボンベ、9はホスフインガスボ
ンベでありこれらのボンベからのガスは任意の混
合できるように構成されている。 上記構成の装置において、SiH4ガスボンベ6
とH2ガスボンベ7からSiH4とH2を任意の体積比
で混合させ、グロー放電を発生させて真性アモル
フアスシリコン層を電極5に設けた基板上に堆積
させた所、前記真性アモルフアスシリコン膜のフ
エルミ準位を0.6〜1.0eVの範囲で制御可能であつ
た。 これを示したのが第3図である。SiH4の体積
比が大きい程、真性層の活性化エネルギーが大き
くなつているのが判る。なお、真性層の活性化エ
ネルギーとは、一般的に用いられているとおりの
概念を意味し、この場合伝導帯からフエルミレベ
ルまでのエネルギー差のことである。又、この時
の光伝導度は、どの真性層でも非常に大きく、光
電変換素子としては十分なものであることが判か
つた。これを第4図に示す。 SiH4とH2の混合比を変化させることによる真
性層の変化に関するメカニズムは、堆積時の薄膜
形成反応、及び表面反応の変化によるものではあ
るが、未だ詳細な理由は不明である。水素の希釈
を増すことにより活性化エネルギーが単調に減少
する理由としては、膜幅に入り込む水素量が多く
なることにより電子状態が変化するという考え方
と、逆に膜が緻密化して、バンド端付近の状態密
度が変化するといる考え方があり、定説はない。 上記のような真性層の活性化エネルギーの変化
に基づき、H2に対するSiH4の混合比はSiH4/H2
を単調に変化させれば、活性化エネルギーは単調
に変化するので、層の両端において内蔵電位が生
ずる。すなわち、連続的かつ単調にSiH4とH2
体積比を変化させながら真性層を堆積させること
によつて真性層自身に内蔵電位を0.4V与えるこ
とができる。例えばp−i−n型の光電変換素子
を作る場合、p層、即ちホウ素添加層を堆積させ
た後、真性層を、SiH4の体積比を大きい方から
小さい方へ連続に変化させ、その後、n層、即ち
リン添加層を堆積させるとなお、P層の活性化エ
ネルギーは〜0.4eV程度(0.4〜0.6eV)で、これ
は価電子帯からの値であり、伝導体は1.2〜1.4eV
となり、真性層で最も大きい値である1.1eVより
大きい。また、n層の活性化エネルギーは0.2〜
0.3eV(伝導帯から)で、真性層で最も最も小さ
い値は0.6eVである。従つて、真性層内に内蔵電
位を与えても、P層またはn層との関係で問題を
生じることはない。 次表は従来の方法によつて堆積した真性層(i
層)を用いたp−i−n型光電変換素子と、本実
施例の方法によつて堆積した真性層を用いたp−
i−n型光電変換素子の特性を比較して示したも
のでここで、単一の真性層すなわち従来の方法に
よつて堆積した真性層は、混合比SH4/H2が20
%のもので、厚みは5000Aである。 真性層以外の層の堆積条件は、次の通りであ
る。 P:B2H6/SiH4百分比は0.25% 厚み150A N:PH3/SiH4百分比は1% 厚み350A また本発明による真性層を備えた素子は、P層
を150A堆積させた後、真性層として、H2に対す
るSiH4の混合比SH4/H2を100%から5%まで一
方向に単調に減少させた層を、約5000A堆積させ
た後、n層を約350A堆積させたものである。
The present invention relates to a method for manufacturing an amorphous photoelectric conversion element. The present invention creates a built-in electric field in the intrinsic layer itself by continuously changing the Fermi level of the intrinsic layer used as a photoconductive layer, which is an important element that determines photoelectric conversion efficiency, thereby increasing photoelectric conversion efficiency. The present invention provides a method for manufacturing a photoelectric conversion element that improves the performance of the photoelectric conversion element. Conventionally, the intrinsic layer of an amorphous silicon photoelectric conversion element has a value of about 0.7 to 0.9 eV because the activation energy indicating the Fermi level is produced under constant conditions. Therefore, even if light is incident on the intrinsic layer and electron-hole pairs are generated, there is a high probability that recombination will occur before the electrons and holes are separated into the positive electrode and the negative electrode due to diffusion. Therefore, in order to prevent this, an idea was developed to create a built-in electric field in the intrinsic layer by gradually adding a small amount of impurity to the intrinsic layer. In other words, due to the built-in electric field, electrons,
The holes are accelerated toward the positive and negative electrodes, increasing the probability that they will be extracted from the electrodes before being recombined. However, in this method of controlling the Fermi level by adding impurities, when actually adding impurities, the amount of impurities added must be a very small value, so it is extremely difficult to control.
Furthermore, if the Fermi level is controlled by adding, for example, boron or phosphorus elements, there is a drawback that the photoconductivity is extremely reduced and the layer cannot function as an intrinsic layer. FIG. 1 is a diagram showing that the photoconductivity is significantly reduced by adding impurities. The horizontal axis is the volume ratio of diborane (B 2 H 6 ) and silane gas (SiH 4 ),
The vertical axis shows the photoconductivity of the deposited layer. It can be seen that as the volume ratio of diborane to silane gas increases, that is, as the amount of boron added increases, the photoconductivity of the deposited layer decreases. The present invention improves the above-mentioned conventional problems by devising a method for depositing an intrinsic layer without adding impurities. explain. FIG. 2 shows an example of the configuration of an apparatus for carrying out the method of manufacturing an amorphous photoelectric conversion element of the invention. As shown in the figure, after the glow discharge reaction tube 1 is evacuated from the exhaust port 2 by a pump such as a rotary pump (not shown), the pressure is increased to 0.1 to 1 Torr.
Gases mainly composed of SiH 4 and H 2 , as well as suitable
diborane and phosphine gas diluted with H2 ,
The gas is introduced into the reaction tube 1 through the gas introduction port 3. In the figure, 4 is an electrode, 5 is a heater-equipped substrate holder/electrode, 6 is a SiH 4 cylinder, 7 is an H 2 gas cylinder,
8 is a diborane gas cylinder, and 9 is a phosphine gas cylinder, and the gases from these cylinders can be mixed as desired. In the device with the above configuration, SiH 4 gas cylinder 6
SiH 4 and H 2 are mixed in an arbitrary volume ratio from a H 2 gas cylinder 7, a glow discharge is generated, and an intrinsic amorphous silicon layer is deposited on the substrate provided on the electrode 5. The Fermi level of the film could be controlled within the range of 0.6 to 1.0 eV. Figure 3 shows this. It can be seen that the activation energy of the intrinsic layer increases as the volume ratio of SiH 4 increases. Note that the activation energy of the intrinsic layer means the concept as it is generally used, and in this case refers to the energy difference from the conduction band to the Fermi level. Furthermore, it was found that the photoconductivity at this time was extremely high in all the intrinsic layers, and was sufficient for a photoelectric conversion element. This is shown in FIG. The mechanism of changes in the intrinsic layer by changing the mixing ratio of SiH 4 and H 2 is due to changes in thin film formation reactions and surface reactions during deposition, but the detailed reason is still unknown. The reason why the activation energy decreases monotonically with increasing dilution of hydrogen is that the electronic state changes as the amount of hydrogen that enters the film width increases, and conversely, the film becomes denser and the activation energy decreases near the band edge. There is an idea that the density of states changes, but there is no established theory. Based on the change in the activation energy of the intrinsic layer as described above, the mixing ratio of SiH 4 to H 2 is SiH 4 /H 2
If the activation energy changes monotonically, a built-in potential is generated at both ends of the layer. That is, by depositing the intrinsic layer while continuously and monotonically changing the volume ratio of SiH 4 and H 2 , a built-in potential of 0.4 V can be applied to the intrinsic layer itself. For example, when making a p-i-n type photoelectric conversion element, after depositing a p-layer, that is, a boron-doped layer, the intrinsic layer is formed by continuously changing the volume ratio of SiH 4 from a large volume to a small volume ratio, and then , the activation energy of the P layer is about 0.4 eV (0.4 to 0.6 eV), which is the value from the valence band, and the conductor is 1.2 to 1.4 eV. eV
This is larger than 1.1 eV, which is the largest value in the intrinsic layer. Also, the activation energy of the n layer is 0.2~
0.3eV (from the conduction band), and the smallest value in the intrinsic layer is 0.6eV. Therefore, even if a built-in potential is applied to the intrinsic layer, no problem will arise in relation to the P layer or the n layer. The following table shows the intrinsic layer (i) deposited by conventional methods.
layer) and a p-i-n photoelectric conversion device using an intrinsic layer deposited by the method of this example.
This shows a comparison of the characteristics of i-n type photoelectric conversion elements. Here, the single intrinsic layer, that is, the intrinsic layer deposited by the conventional method, has a mixing ratio of SH 4 /H 2 of 20.
%, and the thickness is 5000A. The deposition conditions for layers other than the intrinsic layer are as follows. P:B 2 H 6 /SiH 4% ratio is 0.25% Thickness 150A N:PH 3 /SiH 4 % ratio is 1% Thickness 350A Further, the device with the intrinsic layer according to the present invention has an intrinsic layer after depositing the P layer for 150A. As a layer, a layer in which the mixing ratio of SiH 4 to H 2 (SH 4 /H 2 ) monotonically decreased from 100% to 5% was deposited for approximately 5000A, and then an n layer was deposited for approximately 350A. It is.

【表】 なお、同表は光量100mW/cm2の光を射照した
ときの特性を平均値として示したものである。 同表から明らかなように本実施例の方法を用い
た場合は従来に比べて大きく光電変換素子の特性
が向上し、変換効率が大きくなつていることがわ
かる。 当然のことながら本発明は、シヨツトキー型光
電変換素子の真性層としても有効である。 以上説明したように本発明のアモルフアス光電
変換素子の製造方法は実施が容易でかつ変換効率
の高い光電変換素子が得られるもので、工業的利
用価値が高い。
[Table] The table shows the average characteristics when irradiated with light at a light intensity of 100 mW/cm 2 . As is clear from the table, when the method of this example is used, the characteristics of the photoelectric conversion element are greatly improved compared to the conventional method, and the conversion efficiency is increased. Naturally, the present invention is also effective as an intrinsic layer of a Schottky photoelectric conversion element. As explained above, the method for manufacturing an amorphous photoelectric conversion element of the present invention is easy to implement and can yield a photoelectric conversion element with high conversion efficiency, and has high industrial utility value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、堆積層のフエルミ準位を不純物添加
によつて制御した場合、光伝導度が大幅に低下す
ることを示すための図、第2図は本発明のアモル
フアス光電変換素子の製造方法を実施する装置の
構成を示す図、第3図は本発明の方法の効果を説
明するため、SiH4とH2の混合比を変化させた時
の真性層の活性化エネルギーの変化を示した図、
第4図は本発明の方法の効果として真性層のフエ
ルミ準位を変化させても光伝導度が大きく変化し
ないことを説明する図である。 1……グロー放電反応管、2……排気口、3…
…ガス導入口、4……電極、5……基板ホルダー
兼ヒータ付電極、6……SiH4ボンベ、7……H2
ボンベ、8……ジボランボンベ、9……ホスフイ
ンボンベ。
FIG. 1 is a diagram showing that the photoconductivity is significantly reduced when the Fermi level of the deposited layer is controlled by adding impurities, and FIG. 2 is a diagram showing the method for manufacturing an amorphous photoelectric conversion element of the present invention. Figure 3 shows the change in the activation energy of the intrinsic layer when the mixing ratio of SiH 4 and H 2 is changed, in order to explain the effect of the method of the present invention. figure,
FIG. 4 is a diagram illustrating that as an effect of the method of the present invention, the photoconductivity does not change significantly even if the Fermi level of the intrinsic layer is changed. 1...Glow discharge reaction tube, 2...Exhaust port, 3...
...Gas inlet, 4...Electrode, 5...Substrate holder and electrode with heater, 6...SiH 4 cylinder, 7...H 2
cylinder, 8... diborane cylinder, 9... phosphine cylinder.

Claims (1)

【特許請求の範囲】[Claims] 1 基板上に形成したアモルフアスシリコン薄膜
よりなるp−i−n接合構造、もしくは金属/i
−nのシヨツトキー接合構造を有するアモルフア
ス光電変換素子の製造方法であつて、前記真性
(i型)層を形成する工程において、H2に対する
SiH4の混合比を、n層に向つて単調に減少させ
つつ前記真性層を堆積させ、真性層の活性化エネ
ルギーを低下させることを特徴とするアモルフア
ス光電変換素子の製造方法。
1 A pin junction structure consisting of an amorphous silicon thin film formed on a substrate, or a metal/i
A method for manufacturing an amorphous photoelectric conversion element having a Schottky junction structure of -n, wherein in the step of forming the intrinsic (i-type) layer,
A method for manufacturing an amorphous photoelectric conversion element, characterized in that the intrinsic layer is deposited while the mixing ratio of SiH 4 is monotonically decreased toward the n-layer, thereby lowering the activation energy of the intrinsic layer.
JP56088398A 1981-06-09 1981-06-09 Manufacture of amorphous photoelectric conversion element Granted JPS57202788A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56088398A JPS57202788A (en) 1981-06-09 1981-06-09 Manufacture of amorphous photoelectric conversion element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56088398A JPS57202788A (en) 1981-06-09 1981-06-09 Manufacture of amorphous photoelectric conversion element

Publications (2)

Publication Number Publication Date
JPS57202788A JPS57202788A (en) 1982-12-11
JPH0450756B2 true JPH0450756B2 (en) 1992-08-17

Family

ID=13941680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56088398A Granted JPS57202788A (en) 1981-06-09 1981-06-09 Manufacture of amorphous photoelectric conversion element

Country Status (1)

Country Link
JP (1) JPS57202788A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106531834B (en) * 2016-11-30 2018-01-30 华中科技大学 A kind of HIT solar cells and preparation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56138970A (en) * 1980-03-31 1981-10-29 Agency Of Ind Science & Technol Amorphous photoelectric converting element and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56138970A (en) * 1980-03-31 1981-10-29 Agency Of Ind Science & Technol Amorphous photoelectric converting element and manufacture thereof

Also Published As

Publication number Publication date
JPS57202788A (en) 1982-12-11

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