JPH0450753B2 - - Google Patents

Info

Publication number
JPH0450753B2
JPH0450753B2 JP57054578A JP5457882A JPH0450753B2 JP H0450753 B2 JPH0450753 B2 JP H0450753B2 JP 57054578 A JP57054578 A JP 57054578A JP 5457882 A JP5457882 A JP 5457882A JP H0450753 B2 JPH0450753 B2 JP H0450753B2
Authority
JP
Japan
Prior art keywords
substrate
mercury
charge
carrier concentration
mask material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57054578A
Other languages
Japanese (ja)
Other versions
JPS58171848A (en
Inventor
Hiroshi Takigawa
Mitsuo Yoshikawa
Tomoshi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57054578A priority Critical patent/JPS58171848A/en
Publication of JPS58171848A publication Critical patent/JPS58171848A/en
Publication of JPH0450753B2 publication Critical patent/JPH0450753B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • H01L27/14649Infrared imagers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明はフレームトランスフア型の半導体固体
撮像装置の製造方法に係り、特に同一半導体基板
上に密集して画素を構成した場合各画素の信号を
確実に分解できるように電荷堰を形成できる製造
方法に関する。
[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for manufacturing a frame transfer type semiconductor solid-state imaging device, and in particular, when pixels are densely arranged on the same semiconductor substrate, the signal of each pixel is The present invention relates to a manufacturing method that can form a charge weir so that it can be reliably decomposed.

(b) 技術の背景 近年、半導体技術の著しい進歩によつて多元半
導体、例えば水銀カドミウムテルル(HgCdTe)
の合金などは、その中での電荷の易動度が、従来
使われていたシリコン(Si)などよりもはるかに
大であることに注目され、多くの半導体装置、あ
るいは機能デバイスの試作が多元半導体を用いて
行われている。
(b) Technical background In recent years, significant progress in semiconductor technology has led to the development of multi-component semiconductors, such as mercury cadmium tellurium (HgCdTe).
It has been noted that the mobility of charge in materials such as alloys is much higher than that of conventionally used materials such as silicon (Si). This is done using semiconductors.

(c) 従来技術と問題点 フレームトランスフア型(以下FT型と称する)
の固体撮像装置もこの例に洩れないものであつ
て、これは例えば第1図に例示するごとくn型の
基板1上に作られた受光面上に絶縁膜2を介して
例えばCCDを複数条配設し、該CCDの複数の転
送電極3の内に周期的配列をなして透明電極を配
したものである。ただし第1図は電荷転送路を長
手方向から見た断面図である。こうした装置は撮
像装置に共通な性質として、隣接する各電荷転送
路6間に電荷堰を設けなければならないが、
HgCdTe中では不純物の拡散係数が極めて大きい
ので、このような半導体基板中に例えば拡散など
によつて、低キヤリヤ濃度の基板と同じ導電型の
高キヤリヤ濃度領域からなる電荷堰を構成するこ
とができない。
(c) Conventional technology and problems Frame transfer type (hereinafter referred to as FT type)
The solid-state imaging device shown in FIG. Transparent electrodes are arranged in a periodic arrangement among the plurality of transfer electrodes 3 of the CCD. However, FIG. 1 is a sectional view of the charge transfer path viewed from the longitudinal direction. In such a device, a charge weir must be provided between each adjacent charge transfer path 6, which is a common characteristic of imaging devices.
Since the diffusion coefficient of impurities in HgCdTe is extremely large, it is impossible to construct a charge weir consisting of a high carrier concentration region of the same conductivity type as a low carrier concentration substrate in such a semiconductor substrate, for example, by diffusion. .

したがつて従来は第1図に見られるようないわ
ゆるMIS構成体の性質を利用し、絶縁膜2上に形
成されたフイールドプレート7に電圧VFを印加
して該フイールドプレート7直下の半導体表面を
フラツトバンド状態あるいは累積状態として各電
荷転送路6間の分離を行なつて来た。但し8は電
荷転送路6を形成する電位の井戸(以下井戸と呼
ぶ)である。
Therefore, in the past, the properties of the so-called MIS structure as shown in FIG. The charge transfer paths 6 have been separated by using a flat band state or an accumulation state. However, 8 is a potential well (hereinafter referred to as a well) forming the charge transfer path 6.

また図には示していないがフイールドプレート
7が形成できない時にはその部分の絶縁膜厚を大
にすれば該絶縁膜2と半導体との界面近くの正の
固定電荷が多くなることを利用して、該絶縁膜厚
を大にし、その直下を例えば累積状態にして電荷
転送路6間の分離を行なつて来た。
Although not shown in the figure, if the field plate 7 cannot be formed, increasing the thickness of the insulating film in that area increases the number of positive fixed charges near the interface between the insulating film 2 and the semiconductor. The thickness of the insulating film has been increased, and the portion directly under the insulating film is placed in, for example, an accumulation state to separate the charge transfer paths 6.

しかしこのうち前者のフイールドプレート7を
形成するならば配設電極数が増え、そのために歩
留りが低下するという欠点がある。そしてまたこ
の前者においても、あるいは後者の絶縁膜厚を大
にするという方法においても、共に電荷転送路6
間の分離つまりアイソレーシヨンが充分ではな
く、仮に過剰信号光の入射などが生じればたちま
ちにして各電荷転送路6中の電荷は入りまじり、
いわゆるクロストークを生じるという欠点を有し
ていた。
However, if the former field plate 7 is formed, the number of electrodes to be provided increases, which has the drawback of lowering the yield. Also, in both the former method and the latter method of increasing the thickness of the insulating film, the charge transfer path 6
If the separation between the charge transfer paths 6, that is, the isolation, is not sufficient, and if excessive signal light is incident, the charges in each charge transfer path 6 will immediately mix together.
This has the disadvantage of causing so-called crosstalk.

(d) 発明の目的 本発明は上記従来の欠点に鑑みてなされたもの
で、基板材料としてのHgCdTe特有の熱処理によ
る性質を利用し、基板表層部のHg原子の比較的
容易な抜け出しならびに再導入の過程を利用して
所定部分だけに基板と同じ導電型の高キヤリヤ濃
度の個所を構成して、これによつて確実な電荷堰
を形成する固体撮像装置の製造方法を提供するこ
とを目的とするものである。
(d) Purpose of the Invention The present invention has been made in view of the above-mentioned conventional drawbacks, and utilizes the heat treatment properties unique to HgCdTe as a substrate material to allow relatively easy escape and re-introduction of Hg atoms from the surface layer of the substrate. The purpose of the present invention is to provide a method for manufacturing a solid-state imaging device in which a high carrier concentration of the same conductivity type as the substrate is formed only in a predetermined portion using the process described above, thereby forming a reliable charge dam. It is something to do.

(e) 発明の構成 そして、この目的は、本発明によれば、水銀カ
ドミウムテルルの半導体基板を材料として固体撮
像装置を作製する方法であつて、低濃度のアクセ
プタ不純物を含有した上記半導体基板に対して水
銀上記中で高温熱処理をほどこし、当該基板表層
部の水銀を抜きとることによりキヤリヤ濃度を一
旦高める工程と、その表面の電荷転送路形成予定
部に窓を有する拡散マスク材を配設する工程と、
水銀蒸気中で低温処理を行つて、上記拡散マスク
材で覆われていない前記基板表層部に水銀を導入
して当該表層部のキヤリヤ濃度を低め、前記拡散
マスク材直下に残置された高キヤリヤ濃度部分に
よつて電荷堰を形成する工程とを含むことを特徴
とする固体撮像装置の製造方法によつて達成され
る。
(e) Structure of the Invention According to the present invention, an object of the present invention is to provide a method for manufacturing a solid-state imaging device using a mercury cadmium telluride semiconductor substrate as a material, the semiconductor substrate containing a low concentration of acceptor impurities. A process of once increasing the carrier concentration by subjecting the substrate to high-temperature heat treatment in a mercury atmosphere and extracting the mercury from the surface layer of the substrate, and providing a diffusion mask material having a window in the area where the charge transfer path is to be formed on the surface thereof. process and
A low-temperature treatment is performed in mercury vapor to introduce mercury into the surface layer of the substrate that is not covered with the diffusion mask material to lower the carrier concentration in the surface layer, resulting in a high carrier concentration remaining directly under the diffusion mask material. This is achieved by a method for manufacturing a solid-state imaging device characterized by including the step of forming a charge dam by a portion.

(f) 発明の実施例 以下本発明の実施例を図面を用いて詳述する。(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図aに示すようにHgCdTe基板1を作製す
るのであるが、該基板1の結晶製作時にあらかじ
め低濃度のアクセプタ不純物、例えば銀(Ag)
を添加しておき、このウエハをHg蒸気中で低温
例えば250℃で約10日間熱処理を行う。こうす
れば上記基板1中の深層部に至るまで、メタルサ
イトの空格子点がHg原子によつて埋められ、そ
の結果、上述のあらかじめ添加しておいたアクセ
プタ不純物が支配的に導電型を決定するようにな
つて、基板1全体は第2図aに示したように低キ
ヤリヤ濃度のp型となる。
As shown in FIG. 2a, an HgCdTe substrate 1 is prepared. During the crystal production of the substrate 1, a low concentration of acceptor impurities, such as silver (Ag), is added in advance.
is added, and this wafer is heat-treated in Hg vapor at a low temperature, for example, 250° C., for about 10 days. In this way, the vacancies of the metal sites are filled with Hg atoms even deep in the substrate 1, and as a result, the acceptor impurity added in advance dominantly determines the conductivity type. As a result, the entire substrate 1 becomes p-type with a low carrier concentration as shown in FIG. 2a.

次にこの基板1を高温例えば500℃で約30分間熱
処理する。こうすれば該基板1の表層部の例えば
5μmの深さの所までの水銀原子が抜け出してメタ
ルサイトの空格子点が発生し、第2図bに見られ
るような高キヤリヤ濃度のp+型層9ができ上る。
Next, this substrate 1 is heat-treated at a high temperature, for example, 500° C., for about 30 minutes. In this way, for example, the surface layer of the substrate 1 can be
Mercury atoms up to a depth of 5 μm escape, creating metal site vacancies and forming a p + -type layer 9 with a high carrier concentration as shown in FIG. 2b.

そしてこうした基板表面に、第2図cに示した
ように例えば硫化亜鉛のような拡散マスク材10
を一面に形成し、電荷転送路形成予定部だけ窓W
を開く。さらにこうしてできたものに対してHg
蒸気中の前記と同じ低温熱処理をほどこすと、拡
散マスク材のない窓Wの部分の表層部には再び
Hgが拡散され、メタルサイトの空格子点が埋め
られる結果、第2図dに示すように、残された拡
散マスク材10の直下の部分以外の表層部は基板
1と同じ低キヤリヤ濃度のp型に戻り、電荷堰と
して働くp+層11のみが残される。
Then, as shown in FIG. 2c, a diffusion mask material 10 such as zinc sulfide is applied to the surface of the substrate.
is formed on one side, and a window W is formed only in the area where the charge transfer path is planned to be formed.
open. Furthermore, Hg
When the same low-temperature heat treatment as described above is applied in steam, the surface layer of the window W where there is no diffusion mask material will be covered again.
As a result of Hg being diffused and filling the vacancies in the metal sites, as shown in FIG. Returning to the mold, only the p + layer 11, which acts as a charge weir, remains.

この後拡散マスク材10を除去して露出した基
板表面に例えば1200〓程度の厚さの絶縁膜12を
配設し、さらに所定の部分にフイールド絶縁層1
3を形成すれば第2図eのようになる。
After that, the diffusion mask material 10 is removed and an insulating film 12 with a thickness of, for example, about 1200 mm is provided on the exposed substrate surface, and a field insulating layer 1 is further formed in a predetermined portion.
3, the result will be as shown in Figure 2e.

そしてこの上にニツケル(Ni)もしくはクロ
ーム(Cr)の導電膜14を一面に配設し、所定
部分にW′として示した分離領域を作れば第2図
fで2分された導電膜14はCCDの転送電極3
となるから、あとは該導電膜14に対してボンデ
イング配線を行えばFT型の固体撮像装置ができ
上る。
Then, by disposing a conductive film 14 of nickel (Ni) or chrome (Cr) on one surface and creating a separation region shown as W' at a predetermined portion, the conductive film 14 divided into two parts as shown in FIG. CCD transfer electrode 3
Therefore, all that is left to do is to perform bonding wiring to the conductive film 14 to complete the FT type solid-state imaging device.

この場合、第2図dの拡散マスク材10で覆わ
れていた部分の基板表層部には11として示した
p+半導体領域が残されたままになつているが、
この領域は治金学的に作られた電荷堰としての役
割を果たすようになり、したがつてここに第2図
f中に6として示した電荷転送路が画定されるこ
とになる。
In this case, the part of the substrate surface covered with the diffusion mask material 10 in FIG. 2d is shown as 11.
Although the p + semiconductor region remains,
This region will act as a metallurgically created charge weir, thus defining here the charge transfer path shown as 6 in FIG. 2f.

第3図a〜fは本発明の変形実施例を示す製造
工程を示すものであるが、第2図a〜fに示した
工程と対照的な所は第3図aに示したようにn型
HgCdTe基板1aの上にp-型HgCdTe層15を
エピタキシヤル技術で積み上げたウエハを用いる
点である。この場合p-型HgCdTe成長層15を
積み上げるに際しては、あらかじめ低濃度のアク
セプター不純物例えば銀(Ag)を添加しておく。
Figures 3a to 3f show the manufacturing process of a modified embodiment of the present invention, and the contrast with the process shown in Figures 2a to 3e is as shown in Figure 3a. mold
The point is that a wafer is used in which a p - type HgCdTe layer 15 is stacked on an HgCdTe substrate 1a by epitaxial technology. In this case, when stacking the p - type HgCdTe growth layer 15, a low concentration of acceptor impurity such as silver (Ag) is added in advance.

このウエハをHg蒸気中で高温熱処理すればp-
型HgCdTe層中のHg原子は抜け出して上記の層
15は第3図bに示したようにp+の導電型とな
るので、その表面に前述したような拡散マスク材
10を第3図cのように配設する。
If this wafer is heat-treated at high temperature in Hg vapor, p -
Hg atoms in the HgCdTe layer escape and the layer 15 becomes p + conductivity type as shown in FIG. Arrange it like this.

こうした後にこの試料をやはりHg蒸気中で低
温熱処理すれば、前記成長層15における表面の
拡散マスク10で覆われていない部分16はp-
型となるが拡散マスク10で覆われていた部分に
はp+型のHgCdTeが第3図dにおいて17とし
て示したように残されている。
After this, if this sample is also subjected to low-temperature heat treatment in Hg vapor, the portion 16 of the surface of the growth layer 15 that is not covered with the diffusion mask 10 is p -
In the part that was covered by the diffusion mask 10, p + type HgCdTe remains as shown as 17 in FIG. 3d.

したがつてこの上に第3図eのように絶縁膜1
2を配設しさらにフイールド絶縁層13を形成し
た上で、第3図fに示したように導電膜14を配
設すれば、第2図a〜fに示したものと同導電型
の半導体固体撮像装置ができ上がる。
Therefore, an insulating film 1 is formed on this as shown in FIG. 3e.
2 and further form a field insulating layer 13, and then a conductive film 14 as shown in FIG. 3f, a semiconductor of the same conductivity type as that shown in FIGS. A solid-state imaging device is completed.

すなわち本発明によれば、電荷堰は電界誘発方
式で作られたものでなく、治金学的方式で作製さ
れたものであるという点で従来のものと大きく異
なり、特に、上記変形実施例においてはpn接合
が各電荷転送路直下に存在することになるので、
強い光が入射した場合に電荷が転送路からあふれ
出てもこれは上記pn接合のビルドイン電界によ
つて基板1a方向に引かれるために隣接する電荷
転送路中に電荷が混入するような事態は生じない
ことになつて好都合である。
That is, according to the present invention, the charge weir is significantly different from the conventional one in that it is not made by an electric field induction method but by a metallurgical method. Since a pn junction exists directly under each charge transfer path,
Even if charges overflow from the transfer path when strong light is incident, they will be pulled toward the substrate 1a by the built-in electric field of the pn junction, so there is no possibility that charges will mix into the adjacent charge transfer path. It is convenient that this will not occur.

(g) 発明の効果 以上、詳細に説明したように、本発明の固体撮
像装置の製造方法を用いれば、電荷堰は治金学的
手法で作られたものとなるために各電荷転送路間
のアイソレーシヨンも完全なものとなるために、
実用上多大の効果が期待できる。
(g) Effects of the Invention As explained in detail above, if the method for manufacturing a solid-state imaging device of the present invention is used, the charge weir is made by a metallurgical method, so that In order to achieve perfect isolation,
Great practical effects can be expected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の固体撮像装置の構造を示した
図、第2図は本発明による上記装置の製造工程
図、また第3図は本発明の変形実施例になる製造
工程図である。 図において、1は半導体基板、2は絶縁膜、3
は転送電極、6は電荷転送路、7はフイールドプ
レート、8は電位の井戸、9は高キヤリヤ濃度の
p+層、10は拡散マスク材、11は電荷堰とし
て働くp+層、12は絶縁膜、13はフイールド
絶縁層、14は導電膜をそれぞれ示す。
FIG. 1 is a diagram showing the structure of a conventional solid-state imaging device, FIG. 2 is a manufacturing process diagram of the device according to the present invention, and FIG. 3 is a manufacturing process diagram of a modified embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is a semiconductor substrate.
is a transfer electrode, 6 is a charge transfer path, 7 is a field plate, 8 is a potential well, and 9 is a high carrier concentration
10 is a p + layer, 10 is a diffusion mask material, 11 is a p + layer serving as a charge weir, 12 is an insulating film, 13 is a field insulating layer, and 14 is a conductive film.

Claims (1)

【特許請求の範囲】 1 水銀カドミウムテルルの半導体基板を材料と
して固体撮像装置を作製する方法であつて、 低濃度のアクセプタ不純物を含有した上記半導
体基板に対して水銀蒸気中で高温熱処理をほどこ
し、当該基板表層部の水銀を抜きとることにより
キヤリヤ濃度を一旦高める工程と、 その表面の電荷転送路形成予定部に窓を有する
拡散マスク材を配設する工程と、 水銀蒸気中で低温処理を行つて、上記拡散マス
ク材で覆われていない前記基板表層部に水銀を導
入して当該表層部のキヤリヤ濃度を低め、前記拡
散マスク材直下に残置された高キヤリヤ濃度部分
によつて電荷堰を形成する工程とを含むことを特
徴とする固体撮像装置の製造方法。
[Claims] 1. A method for manufacturing a solid-state imaging device using a mercury-cadmium-tellurium semiconductor substrate, comprising: subjecting the semiconductor substrate containing a low concentration of acceptor impurities to high-temperature heat treatment in mercury vapor; A step of temporarily increasing the carrier concentration by removing mercury from the surface layer of the substrate, a step of disposing a diffusion mask material having a window in the area where the charge transfer path is to be formed on the surface, and a low-temperature treatment in mercury vapor. Then, mercury is introduced into the surface layer of the substrate not covered with the diffusion mask material to lower the carrier concentration in the surface layer, and a charge weir is formed by the high carrier concentration portion left directly under the diffusion mask material. A method for manufacturing a solid-state imaging device, comprising the steps of:
JP57054578A 1982-03-31 1982-03-31 Preparation of solid-state image pick-up apparatus Granted JPS58171848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57054578A JPS58171848A (en) 1982-03-31 1982-03-31 Preparation of solid-state image pick-up apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57054578A JPS58171848A (en) 1982-03-31 1982-03-31 Preparation of solid-state image pick-up apparatus

Publications (2)

Publication Number Publication Date
JPS58171848A JPS58171848A (en) 1983-10-08
JPH0450753B2 true JPH0450753B2 (en) 1992-08-17

Family

ID=12974578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57054578A Granted JPS58171848A (en) 1982-03-31 1982-03-31 Preparation of solid-state image pick-up apparatus

Country Status (1)

Country Link
JP (1) JPS58171848A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4654686A (en) * 1985-03-01 1987-03-31 Texas Instruments Incorporated High efficiency MIS detector
JPH0945953A (en) * 1995-08-01 1997-02-14 Nec Corp Array infrared detector

Also Published As

Publication number Publication date
JPS58171848A (en) 1983-10-08

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