JPH0450748B2 - - Google Patents
Info
- Publication number
- JPH0450748B2 JPH0450748B2 JP2003283A JP2003283A JPH0450748B2 JP H0450748 B2 JPH0450748 B2 JP H0450748B2 JP 2003283 A JP2003283 A JP 2003283A JP 2003283 A JP2003283 A JP 2003283A JP H0450748 B2 JPH0450748 B2 JP H0450748B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- sio
- active region
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 20
- 230000003647 oxidation Effects 0.000 description 15
- 238000007254 oxidation reaction Methods 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 241000293849 Cordylanthus Species 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000007800 oxidant agent Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法に関し、特に
IC，LSIなどの素子間分離技術を改良した製造方
法に係る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
It relates to a manufacturing method that improves isolation technology between devices such as ICs and LSIs.
従来例の構成とその問題点
従来、半導体装置特にMOSLSIの製造工程で
の素子間分離方法としては選択酸化法が一般的に
用いられている。この方法をｎ−チヤンネル
MOSLSIを例にして以下に説明する。Conventional Structure and its Problems Conventionally, a selective oxidation method has been generally used as a method for isolating elements in the manufacturing process of semiconductor devices, especially MOSLSIs. This method can be applied to n-channel
This will be explained below using MOSLSI as an example.
まず、第１図ａに示す如く（100）結晶面をも
つＰ型Si基板１上にSiO2膜２を熱酸化により成
長させ、更にこのSiO2膜２上にSi3N4膜３を堆積
する。つづいて写真蝕刻法により活性領域形成部
にレジスト膜４を形成し、これをマスクとして活
性領域部以外のSi3N4膜３をエツチング除去しSi3
N4膜３のパターン３′を形成する。その後、例え
ばボロンのイオン注入を行なつてフイールド部に
チヤンネルストツパ領域としてのp+領域５を形
成する（同図ｂ）。レジスト膜４を除去後Si3N4
膜パターン３′をマスクとして周知の選択酸化法
にしたがつてウエツト酸化を施し選択的に厚いフ
イールド酸化膜６を成長させる（同図ｃ）。ひき
つづきSi3N4膜パターン３′およびSiO2膜２をエ
ツチング除去してフイールド酸化膜６で分離され
た活性領域７を形成する（同図ｄ）。次いで第１
図ｅに示す如く活性領域７にゲート酸化膜８を介
して多結晶シリコンからなるゲート電極９を形成
した後、セルフアライン法によつて例えば砒素を
拡散してソース、ドレインとしてのn+領域１０，
１１を形成する。最後に層間絶縁膜としての
SiO2膜１２をたとえばCVDにより堆積し、n+領
域１０，１１およびゲート電極９に対応する
SiO2膜１２部分にコンタクトホール１３を開孔
した後、Ａ配線１４を形成してｎチヤンネル
MOS素子を製造する（同図ｆ）。 First, as shown in Figure 1a, a SiO 2 film 2 is grown by thermal oxidation on a P-type Si substrate 1 with a (100) crystal plane, and then a Si 3 N 4 film 3 is deposited on this SiO 2 film 2. do. Subsequently, a resist film 4 is formed in the active region formation portion by photolithography, and using this as a mask, the Si 3 N 4 film 3 outside the active region portion is removed by etching.
A pattern 3' of the N 4 film 3 is formed. Thereafter, for example, boron ions are implanted to form a p + region 5 as a channel stopper region in the field portion (FIG. 2B). Si 3 N 4 after removing resist film 4
Using the film pattern 3' as a mask, wet oxidation is performed according to a well-known selective oxidation method to selectively grow a thick field oxide film 6 (FIG. 3(c)). Subsequently, the Si 3 N 4 film pattern 3' and the SiO 2 film 2 are removed by etching to form an active region 7 separated by a field oxide film 6 (FIG. 4(d)). Then the first
As shown in FIG . ，
11 is formed. Finally, as an interlayer insulating film
A SiO 2 film 12 is deposited, for example by CVD, and corresponds to the n + regions 10, 11 and the gate electrode 9.
After opening a contact hole 13 in the SiO 2 film 12 part, an A wiring 14 is formed and an n-channel is formed.
MOS devices are manufactured (FIG. f).
しかしながら上述の従来方法では次に示すよう
な種々の問題点があつた。第２図は、前記第１図
ｃに示すSi3N4膜パターン３′をマスクにしてフ
イルード酸化膜６を形成した時の断面構造を詳し
く描いたものである。一般に選択酸化法ではフイ
ールド酸化膜６がＦ領域分だけ広がりをもち、
Si3N4膜パターン３′の下の領域に喰い込んで成
長することが知られている（第２図Ｆ領域）。こ
れはフイールド酸化中に酸化剤がSi3N4膜パター
ン３′下の薄いSiO2膜２を通して拡散していくた
めに酸化膜が形成される部分Ｄ、いわゆるバーズ
ビークとフイールド酸化膜６の厚い部分が横方向
にもぐり込んだ部分Ｅとからなる。前記Ｆ領域の
長さは、たとえばSi3N4膜パターン３′の厚さが
1200A、その下のSiO2膜２が500Aの条件で1μm
の膜厚のフイールド酸化膜６を成長させた場合、
約1μmに達する。このためフイールド領域の幅Ｃ
は二つのSi3N4膜パターン３′間の距離Ａを2μm
とすると、前記Ｆ領域が1μmであるから、4μm以
下に小さくできずLSI素子の高集積化にとつて大
きな妨げとなる。このようなことから最近、Si3
N4膜パターン３′の膜厚を厚くし、この下のSiO2
膜２を薄くしてバーズビークを抑制する方法が試
みられている。これは、Si3N4膜厚を厚くするこ
とによつてSi3N4膜端部が屈曲しにくくなり、こ
れによりバーズビークが小さくなるものである。
また、Si3N4膜下のSiO2膜厚を薄くすることによ
りSiO2断面積を小さくし酸化剤の横方向への拡
散をおさえたものである。しかし、前者ではフイ
ールド端部におけるSi3N4膜にクラツクが生じ、
後者では活性領域の周辺を中心にSi基板表面にス
トレスが加わり転位の発生があるなどの問題があ
つた。また、チヤンネルストツパ用にイオン注入
したボロンがフイールド酸化中に横方向に再拡散
して第３図ａに示す如く活性領域７の一部がp+
領域５となり実効的な活性領域がＧの幅からＨの
幅まで狭くなつてしまう。この結果トランジスタ
の電流が減少したり、しきい値電圧が上つてしま
うなどのナロウチヤンネル効果が生じ、この効果
は素子の微細化と共に問題となる。しかもp+領
域５が横方向に広がることにより第３図ｂの如く
活性領域７におけるn+領域１１とp+領域５の接
合部が広くなり、n+領域１１と基板１間の浮遊
キヤパシタが大きくなる。この浮遊キヤパシタは
素子が小さくなるに従い無視できなくなる。 However, the conventional method described above has various problems as shown below. FIG. 2 shows in detail the cross-sectional structure when the field oxide film 6 is formed using the Si 3 N 4 film pattern 3' shown in FIG. 1c as a mask. Generally, in the selective oxidation method, the field oxide film 6 expands by the F region,
It is known that the Si 3 N 4 film grows by digging into the region below the pattern 3' (region F in FIG. 2). This is because the oxidizing agent diffuses through the thin SiO 2 film 2 under the Si 3 N 4 film pattern 3' during field oxidation, resulting in the formation of an oxide film D, the so-called bird's beak and the thick part of the field oxide film 6. It consists of a part E that has sunk in laterally. The length of the F region is, for example, the thickness of the Si 3 N 4 film pattern 3'.
1200A, SiO 2 film 2 under it is 1μm at 500A
When growing a field oxide film 6 with a thickness of
It reaches approximately 1μm. Therefore, the width of the field area C
The distance A between the two Si 3 N 4 film patterns 3' is 2 μm.
In this case, since the F region is 1 μm, it cannot be made smaller than 4 μm, which is a major hindrance to high integration of LSI devices. Due to this, recently Si 3
The thickness of the N 4 film pattern 3' is increased, and the SiO 2 layer underneath is increased.
Attempts have been made to suppress bird's beak by making the film 2 thinner. This is because by increasing the thickness of the Si 3 N 4 film, the ends of the Si 3 N 4 film become less likely to bend, thereby reducing the bird's beak.
In addition, by reducing the thickness of the SiO 2 film under the Si 3 N 4 film, the cross-sectional area of SiO 2 is reduced and the lateral diffusion of the oxidizing agent is suppressed. However, in the former case, cracks occur in the Si 3 N 4 film at the edge of the field,
In the latter case, stress was applied to the Si substrate surface mainly around the active region, causing problems such as the generation of dislocations. In addition, boron ions implanted for the channel stopper are laterally re-diffused during field oxidation, and a part of the active region 7 becomes p + as shown in FIG. 3a.
This results in region 5, and the effective active region becomes narrow from the width of G to the width of H. As a result, narrow channel effects such as a decrease in transistor current and an increase in threshold voltage occur, and this effect becomes a problem as devices become smaller. Moreover, as the p + region 5 spreads laterally, the junction between the n + region 11 and the p + region 5 in the active region 7 becomes wider as shown in FIG. 3b, and the floating capacitor between the n + region 11 and the substrate 1 growing. This floating capacitor cannot be ignored as the device becomes smaller.
発明の目的
本発明は上述の従来例にみられた問題点を解消
するものであり、選択酸化法による喰い込みを抑
制することのできる半導体装置の製造方法を提供
するものである。OBJECTS OF THE INVENTION The present invention solves the problems seen in the above-mentioned conventional examples, and provides a method for manufacturing a semiconductor device that can suppress the bite caused by selective oxidation.
発明の構成
本発明は、要約すると、半導体基板表面に第一
の絶縁膜を形成し、前記第一の絶縁膜上の所定の
領域に窒化硅素膜を選択形成する工程と、全面に
多結晶半導体膜を少なくとも前記窒化硅素膜と同
等以上の厚さに形成する工程と、前記多結晶半導
体膜上から前記半導体基板に選択的に前記半導体
基板と同一導電形の不純物イオンを注入する工程
と、前記多結晶半導体膜および前記半導体基板の
一部表面を酸素もしくは水蒸気雰囲気中で酸化膜
に変換し、第二の絶縁膜を形成する工程とを備え
た半導体装置の製造方法である。すなわち、本発
明は活性領域の窒化硅素膜パターンを含めた表面
全体に多結晶半導体を形成することにより実効活
性領域幅を見かけ活性領域幅まで拡大し、この凸
部をマスクとしイオン注入によりチヤンネルスト
ツパ領域を実効活性領域幅に対しオフセツトの形
で形成したのち、多結晶半導体膜およびフイール
ド領域の半導体基板を一挙に酸化し、フイールド
酸化膜を形成するものである。Composition of the Invention To summarize, the present invention includes the steps of forming a first insulating film on the surface of a semiconductor substrate, selectively forming a silicon nitride film in a predetermined region on the first insulating film, and covering the entire surface with a polycrystalline semiconductor film. forming a film to have a thickness at least equal to or greater than the silicon nitride film; selectively implanting impurity ions of the same conductivity type as the semiconductor substrate into the semiconductor substrate from above the polycrystalline semiconductor film; This method of manufacturing a semiconductor device includes a step of converting a polycrystalline semiconductor film and a part of the surface of the semiconductor substrate into an oxide film in an oxygen or water vapor atmosphere to form a second insulating film. That is, the present invention expands the effective active region width to the apparent active region width by forming a polycrystalline semiconductor over the entire surface including the silicon nitride film pattern of the active region, and then uses this convex portion as a mask to perform channel strain reduction by ion implantation. After forming the pad region in an offset form with respect to the effective active region width, the polycrystalline semiconductor film and the semiconductor substrate in the field region are oxidized all at once to form a field oxide film.
実施例の説明
以下、ｎチヤンネルMOSLSIの製造方法を例
にあげて本発明を詳細に説明する。DESCRIPTION OF EMBODIMENTS The present invention will be described in detail below using a method for manufacturing an n-channel MOSLSI as an example.
まず第４図ａに示す如く（100）結晶面をもつ
ｐ型Si基板１上にSiO2膜２を熱酸化により成長
させ更に、このSiO2膜２上にSi3N4膜３を堆積す
る。つづいて、第４図ｂのように写真蝕刻法によ
り活性領域部にレジスト膜４を形成し、これをマ
スクとして活性領域以外のSi3N4膜をエツチング
除去してSi3N4膜パターン３′を形成する。レジ
スト膜４を除去後、第４図ｃのように多結晶シリ
コン１５を表面全体に形成する。このときの多結
晶シリコン１５の厚さは、後述のオフセツト域が
十分確保されるようにするために、Si3N4膜３の
厚さと同等もしくはそれ以上が好ましい。つづい
てボロンのイオン注入を全面に行なつてフイール
ド部分にチヤンネルストツパ領域としてのp+領
域１６を形成する。注入条件としては活性領域に
は注入されずフイールド領域にのみ注入される条
件とする。これにより、オフセツト域をもつてチ
ヤンネルストツパの注入が行なわれる。すなわち
従来方法では第１図ｂに示す如くチヤンネルスト
ツパ領域５が活性領域のSi3N4膜パターンのセル
フアライン法注入により活性領域と隣接してい
た。しかし本発明は第４図ｃに示すように多結晶
シリコン１５を形成することによりSi3N4膜パタ
ーン３′による活性領域幅Ｈが拡大されＩの幅と
なる。このため拡大された活性領域幅の片側部分
Ｊ，Ｋも多結晶シリコン１５が厚く形成され、ほ
ぼ第４図ｃに示したＬと同等の膜厚となる。した
がつてチヤンネルストツパ用注入も活性領域拡大
部分Ｊ，Ｋには入らず、いわゆるオフセツトで形
成される。次にフイールド領域の酸化膜を適当に
するために多結晶シリコン１５をリアクテイブイ
オンエツチング等の異方性エツチング方法を用い
てエツチングを行ない、この膜を完全にエツチン
グ除去せず、第４図ｄのように、約500Å程度残
す。この時、前記第４図ｃ中に示すように、活性
領域拡大部分Ｊ，Ｋでの多結晶シリコン膜厚Ｌが
その他の多結晶シリコン膜厚ＭよりSi3N4膜パタ
ーン３′の膜厚分だけ厚くなる。このため異方性
エツチングにより多結晶シリコン１５をエツチン
グした場合、活性領域拡大部分Ｊ，Ｋの多結晶シ
リコンには、Si3N4膜パターン３′の膜厚分と残
した500Å分の多結晶シリコンの膜厚とを加えた
部分が残る。ついで第４図ｅのようにSi3N4膜パ
ターン３′をマスクとしてウエツト酸化を施し選
択的に厚いフイールド酸化膜１８を成長させる。
この時同図ｄで、窒化硅素膜パターン３′端部に
多結晶シリコンの傾斜部１７ががあるためSi3N4
膜パターン３′下に酸化が進行するには時間を要
する。すなわち第４図ｄの要部拡大図である第５
図においてａ−a′からｂ−b′の方向に酸化が進行
するが、ここで同図中のと′を同一距離とす
ると、SiO2膜２に酸化剤（酸素原子）が到達す
る時間は、点ｃと点ｄとでは異なり、ａ−a′から
ｂ−b′の間の多結晶シリコン１５の酸化時間分だ
け点ｄに酸化剤の到達する時間がおくれることに
なる。したがつて、酸化剤は従来方法よりはSi3
N4膜パターン３′下の薄いSiO2膜２を通して拡散
していくために時間を要し、したがつてバーズビ
ークの発生程度は小さくなる。また、Si3N4膜パ
ターン３′上にも多結晶シリコン１５が少し残つ
ているため、これが酸化されSi3N4膜パターン
３′の端部をおさえる働きをし、さらにバーズビ
ークの発生を低減させる。次にフイールド酸化
後、活性領域上の薄いSiO2膜１８′をエツチング
除去し、その後Si3N4膜パターン３′をエツチン
グ除去する。次にSi3N4膜パターン３′下の薄い
SiO2膜２をエツチング除去し、その後フイール
ド領域で分離された活性領域にMOS、バイポー
ラ等の能動素子を形成して半導体装置を製造す
る。 First, as shown in FIG. 4a, a SiO 2 film 2 is grown on a p-type Si substrate 1 with a (100) crystal plane by thermal oxidation, and then a Si 3 N 4 film 3 is deposited on this SiO 2 film 2. . Next, as shown in FIG. 4b, a resist film 4 is formed in the active region by photolithography, and using this as a mask, the Si 3 N 4 film outside the active region is removed by etching to form the Si 3 N 4 film pattern 3. ′ is formed. After removing the resist film 4, polycrystalline silicon 15 is formed over the entire surface as shown in FIG. 4c. The thickness of the polycrystalline silicon 15 at this time is preferably equal to or greater than the thickness of the Si 3 N 4 film 3 in order to ensure a sufficient offset region to be described later. Subsequently, boron ions are implanted into the entire surface to form a p + region 16 as a channel stopper region in the field portion. The implantation conditions are such that it is not implanted into the active region but only into the field region. This allows the channel stopper to be implanted with an offset region. That is, in the conventional method, as shown in FIG. 1B, the channel stopper region 5 was adjacent to the active region by self-alignment implantation of the Si 3 N 4 film pattern in the active region. However, in the present invention, by forming polycrystalline silicon 15 as shown in FIG. 4c, the active region width H formed by the Si 3 N 4 film pattern 3' is expanded to a width I. Therefore, the polycrystalline silicon 15 is formed thickly on the one side portions J and K of the expanded active region width, and the film thickness becomes approximately the same as that of L shown in FIG. 4c. Therefore, the channel stopper implantation does not enter the active region enlarged portions J, K, but is formed in a so-called offset manner. Next, in order to form an appropriate oxide film in the field region, the polycrystalline silicon 15 is etched using an anisotropic etching method such as reactive ion etching. Leave about 500 Å as shown. At this time, as shown in FIG. 4c, the polycrystalline silicon film thickness L at the active region enlarged portions J and K is larger than the other polycrystalline silicon film thickness M than the film thickness of the Si 3 N 4 film pattern 3'. It gets thicker by that amount. For this reason, when the polycrystalline silicon 15 is etched by anisotropic etching, the polycrystalline silicon in the enlarged active region portions J and K contains the film thickness of the Si 3 N 4 film pattern 3' and the remaining 500 Å of polycrystalline silicon. A portion including the silicon film thickness remains. Next, as shown in FIG. 4e, wet oxidation is performed using the Si 3 N 4 film pattern 3' as a mask to selectively grow a thick field oxide film 18.
At this time, as shown in Figure d, there is a sloped part 17 of polycrystalline silicon at the end of the silicon nitride film pattern 3', so Si 3 N 4
It takes time for oxidation to progress under the film pattern 3'. In other words, Fig. 5 is an enlarged view of the main part of Fig. 4d.
In the figure, oxidation progresses in the direction from a-a' to b-b', but if and' in the figure are the same distance, the time it takes for the oxidant (oxygen atoms) to reach the SiO 2 film 2 is , points c and d are different, and the time for the oxidizing agent to reach point d is delayed by the oxidation time of polycrystalline silicon 15 between a-a' and bb'. Therefore, the oxidizing agent is less Si 3 than in the conventional method.
It takes time to diffuse through the thin SiO 2 film 2 under the N 4 film pattern 3', and therefore the degree of occurrence of bird's beak becomes smaller. In addition, since a small amount of polycrystalline silicon 15 remains on the Si 3 N 4 film pattern 3', this is oxidized and works to suppress the edge of the Si 3 N 4 film pattern 3', further reducing the occurrence of bird's beak. let Next, after field oxidation, the thin SiO 2 film 18' on the active region is etched away, and then the Si 3 N 4 film pattern 3' is etched away. Next, the thin layer under the Si 3 N 4 film pattern 3'
The SiO 2 film 2 is removed by etching, and then active elements such as MOS and bipolar are formed in active regions separated by field regions to manufacture a semiconductor device.
発明の効果
以上のように本発明によれば、チヤンネルスト
ツパはオフセツト域をもたせて形成できるため従
来方法のような活性領域における拡散領域とチヤ
ンネルストツパ領域の接合部の広がりが低減でき
る。したがつてナロウチヤンネル効果と浮遊キヤ
パシタの抑制が可能となる。さらにバーズビーク
が少なくマスクに対し忠実度の高い微細な絶縁分
離領域を形成することができ高集積度の半導体装
置の製造に大きく寄与する。Effects of the Invention As described above, according to the present invention, since the channel stopper can be formed with an offset region, it is possible to reduce the spread of the junction between the diffusion region and the channel stopper region in the active region as in the conventional method. Therefore, narrow channel effects and floating capacitors can be suppressed. Furthermore, it is possible to form fine insulation isolation regions with fewer bird's beaks and high fidelity with respect to the mask, which greatly contributes to the production of highly integrated semiconductor devices.
第１図ａ〜ｆは従来の選択酸化法を用いたｎチ
ヤンネルMOSLSIの製造工程を示す構造断面図、
第２図は前記工程の選択酸化後の基板状態を示す
拡大断面図、第３図ａ，ｂは従来の選択酸化法に
よる問題点を説明するための断面図、第４図ａ〜
ｅは本発明の一実施例を説明するためのｎチヤン
ネルMOSLSIの製造工程を示す構造断面図、第
５図は本発明におけるフイールド酸化時の酸化剤
の拡散過程を説明する断面図である。
１……ｐ型シリコン基板、２……SiO2膜、３
……Si3N4膜、４……フオトレジスト、５……p+
領域（チヤンネルストツパ領域）、６……フイー
ルド領域（SiO2）、７……活性領域、８……ゲー
ト酸化膜、９……ゲート電極、１０，１１……
n+領域（ソースドレイン）、１２……CVDSiO2
膜、１３，１４……Ａ電極、１５……多結晶シ
リコン、１６……p+領域（チヤンネルストツパ
領域）、１８……フイールド領域（SiO2）、１
８′……シリコンナイトライドパターン上SiO2
膜。
Figures 1a to 1f are structural cross-sectional views showing the manufacturing process of an n-channel MOSLSI using the conventional selective oxidation method.
FIG. 2 is an enlarged sectional view showing the state of the substrate after selective oxidation in the above process, FIGS.
e is a structural sectional view showing the manufacturing process of an n-channel MOSLSI for explaining an embodiment of the present invention, and FIG. 5 is a sectional view illustrating the diffusion process of an oxidizing agent during field oxidation in the present invention. 1...p-type silicon substrate, 2...SiO 2 film, 3
...Si 3 N 4 film, 4...photoresist, 5...p +
region (channel stopper region), 6... field region (SiO 2 ), 7... active region, 8... gate oxide film, 9... gate electrode, 10, 11...
n + region (source drain), 12...CVDSiO 2
Film, 13, 14... A electrode, 15... Polycrystalline silicon, 16... p + region (channel stopper region), 18... Field region (SiO 2 ), 1
8'...SiO 2 on silicon nitride pattern
film.
Claims (1)
記第一の絶縁膜上の所定の領域に窒化硅素膜を選
択的に形成する工程と、全面に多結晶半導体膜を
少なくとも前記窒化硅素膜と同等以上の厚さに形
成する工程と、前記多結晶半導体膜上から前記半
導体基板に選択的に前記半導体基板と同一導電形
の不純物イオンを注入する工程と、前記多結晶半
導体膜および前記半導体基板の一部表面を酸素も
しくは水蒸気雰囲気中で酸化膜に変換し、第二の
絶縁膜を形成する工程とを備えたことを特徴とす
る半導体装置の製造方法。1. Forming a first insulating film on the surface of a semiconductor substrate, selectively forming a silicon nitride film in a predetermined region on the first insulating film, and forming a polycrystalline semiconductor film over the entire surface at least with the silicon nitride film. a step of selectively implanting impurity ions of the same conductivity type as the semiconductor substrate from above the polycrystalline semiconductor film into the semiconductor substrate; 1. A method for manufacturing a semiconductor device, comprising the step of converting a part of the surface of a substrate into an oxide film in an oxygen or water vapor atmosphere to form a second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003283A JPS59145539A (en) | 1983-02-09 | 1983-02-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003283A JPS59145539A (en) | 1983-02-09 | 1983-02-09 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59145539A JPS59145539A (en) | 1984-08-21 |
| JPH0450748B2 true JPH0450748B2 (en) | 1992-08-17 |
Family
ID=12015722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003283A Granted JPS59145539A (en) | 1983-02-09 | 1983-02-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59145539A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283854A (en) * | 1988-05-10 | 1989-11-15 | Nec Corp | Manufacture of semiconductor device |
-
1983
- 1983-02-09 JP JP2003283A patent/JPS59145539A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59145539A (en) | 1984-08-21 |
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