JPH04502677A - データパス素子の分析方法 - Google Patents

データパス素子の分析方法

Info

Publication number
JPH04502677A
JPH04502677A JP2503093A JP50309390A JPH04502677A JP H04502677 A JPH04502677 A JP H04502677A JP 2503093 A JP2503093 A JP 2503093A JP 50309390 A JP50309390 A JP 50309390A JP H04502677 A JPH04502677 A JP H04502677A
Authority
JP
Japan
Prior art keywords
stage
delay
pipeline
multiplier
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2503093A
Other languages
English (en)
Japanese (ja)
Inventor
アサト，クレイフトン　サトシ
ドラキア，スレシュ　キショルブハイ
ディッツェン，クリストフ
Original Assignee
ブイエルエスアイ　テクノロジー，インコーポレイティド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ブイエルエスアイ　テクノロジー，インコーポレイティド filed Critical ブイエルエスアイ　テクノロジー，インコーポレイティド
Publication of JPH04502677A publication Critical patent/JPH04502677A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Complex Calculations (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Noise Elimination (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)
JP2503093A 1989-01-13 1990-01-12 データパス素子の分析方法 Pending JPH04502677A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29705789A 1989-01-13 1989-01-13
US297,057 1989-01-13

Publications (1)

Publication Number Publication Date
JPH04502677A true JPH04502677A (ja) 1992-05-14

Family

ID=23144674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2503093A Pending JPH04502677A (ja) 1989-01-13 1990-01-12 データパス素子の分析方法

Country Status (4)

Country Link
JP (1) JPH04502677A (pl)
DE (1) DE4090021T (pl)
GB (1) GB2244829B (pl)
WO (1) WO1990008362A2 (pl)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07141148A (ja) * 1993-11-16 1995-06-02 Kanebo Ltd パイプライン並列乗算器

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519626A (en) * 1993-07-09 1996-05-21 Hewlett-Packard Company Method of dividing a pipelined stage into two stages in a computer-aided design system
US9110689B2 (en) 2012-11-19 2015-08-18 Qualcomm Technologies, Inc. Automatic pipeline stage insertion

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875391A (en) * 1973-11-02 1975-04-01 Raytheon Co Pipeline signal processor
US4263651A (en) * 1979-05-21 1981-04-21 International Business Machines Corporation Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks
US4549280A (en) * 1982-12-20 1985-10-22 Sperry Corporation Apparatus for creating a multiplication pipeline of arbitrary size
US4736333A (en) * 1983-08-15 1988-04-05 California Institute Of Technology Electronic musical instrument
US4799182A (en) * 1984-10-16 1989-01-17 The Commonwealth Of Australia Cellular floating-point serial pipelined multiplier
JPS61114338A (ja) * 1984-11-09 1986-06-02 Hitachi Ltd 乗算器
US4736335A (en) * 1984-11-13 1988-04-05 Zoran Corporation Multiplier-accumulator circuit using latched sums and carries
US4698760A (en) * 1985-06-06 1987-10-06 International Business Machines Method of optimizing signal timing delays and power consumption in LSI circuits
US4827428A (en) * 1985-11-15 1989-05-02 American Telephone And Telegraph Company, At&T Bell Laboratories Transistor sizing system for integrated circuits
US4811260A (en) * 1986-11-13 1989-03-07 Fujitsu Limited Signal processing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07141148A (ja) * 1993-11-16 1995-06-02 Kanebo Ltd パイプライン並列乗算器

Also Published As

Publication number Publication date
DE4090021T (pl) 1991-11-21
WO1990008362A3 (en) 1990-09-07
GB2244829B (en) 1993-01-13
WO1990008362A2 (en) 1990-07-26
GB2244829A (en) 1991-12-11
GB9114332D0 (en) 1991-09-04

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