GB2244829A - Method for analyzing datapath elements - Google Patents
Method for analyzing datapath elementsInfo
- Publication number
- GB2244829A GB2244829A GB9114332A GB9114332A GB2244829A GB 2244829 A GB2244829 A GB 2244829A GB 9114332 A GB9114332 A GB 9114332A GB 9114332 A GB9114332 A GB 9114332A GB 2244829 A GB2244829 A GB 2244829A
- Authority
- GB
- United Kingdom
- Prior art keywords
- stage
- datapath
- analyzing
- delays
- datapath elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001934 delay Effects 0.000 abstract 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3875—Pipelining a single stage, e.g. superpipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Noise Elimination (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
- Complex Calculations (AREA)
Abstract
According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an equation such as: Ds=DbNb+C; where Ds is the estimated stage delay, Db is a delay associated with communication between bits in the stage, Nb is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US29705789A | 1989-01-13 | 1989-01-13 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9114332D0 GB9114332D0 (en) | 1991-09-04 |
GB2244829A true GB2244829A (en) | 1991-12-11 |
GB2244829B GB2244829B (en) | 1993-01-13 |
Family
ID=23144674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9114332A Expired - Fee Related GB2244829B (en) | 1989-01-13 | 1991-07-03 | Method for analyzing datapath elements |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPH04502677A (en) |
DE (1) | DE4090021T (en) |
GB (1) | GB2244829B (en) |
WO (1) | WO1990008362A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5519626A (en) * | 1993-07-09 | 1996-05-21 | Hewlett-Packard Company | Method of dividing a pipelined stage into two stages in a computer-aided design system |
JPH07141148A (en) * | 1993-11-16 | 1995-06-02 | Kanebo Ltd | Pipeline parallel multiplier |
US9110689B2 (en) | 2012-11-19 | 2015-08-18 | Qualcomm Technologies, Inc. | Automatic pipeline stage insertion |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3875391A (en) * | 1973-11-02 | 1975-04-01 | Raytheon Co | Pipeline signal processor |
US4263651A (en) * | 1979-05-21 | 1981-04-21 | International Business Machines Corporation | Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks |
US4549280A (en) * | 1982-12-20 | 1985-10-22 | Sperry Corporation | Apparatus for creating a multiplication pipeline of arbitrary size |
US4698760A (en) * | 1985-06-06 | 1987-10-06 | International Business Machines | Method of optimizing signal timing delays and power consumption in LSI circuits |
US4736333A (en) * | 1983-08-15 | 1988-04-05 | California Institute Of Technology | Electronic musical instrument |
US4736335A (en) * | 1984-11-13 | 1988-04-05 | Zoran Corporation | Multiplier-accumulator circuit using latched sums and carries |
US4752905A (en) * | 1984-11-09 | 1988-06-21 | Hitachi, Ltd. | High-speed multiplier having carry-save adder circuit |
US4799182A (en) * | 1984-10-16 | 1989-01-17 | The Commonwealth Of Australia | Cellular floating-point serial pipelined multiplier |
US4811260A (en) * | 1986-11-13 | 1989-03-07 | Fujitsu Limited | Signal processing circuit |
US4827428A (en) * | 1985-11-15 | 1989-05-02 | American Telephone And Telegraph Company, At&T Bell Laboratories | Transistor sizing system for integrated circuits |
-
1990
- 1990-01-12 JP JP2503093A patent/JPH04502677A/en active Pending
- 1990-01-12 WO PCT/US1990/000266 patent/WO1990008362A2/en active Application Filing
- 1990-01-12 DE DE19904090021 patent/DE4090021T/de not_active Withdrawn
-
1991
- 1991-07-03 GB GB9114332A patent/GB2244829B/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3875391A (en) * | 1973-11-02 | 1975-04-01 | Raytheon Co | Pipeline signal processor |
US4263651A (en) * | 1979-05-21 | 1981-04-21 | International Business Machines Corporation | Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks |
US4549280A (en) * | 1982-12-20 | 1985-10-22 | Sperry Corporation | Apparatus for creating a multiplication pipeline of arbitrary size |
US4736333A (en) * | 1983-08-15 | 1988-04-05 | California Institute Of Technology | Electronic musical instrument |
US4799182A (en) * | 1984-10-16 | 1989-01-17 | The Commonwealth Of Australia | Cellular floating-point serial pipelined multiplier |
US4752905A (en) * | 1984-11-09 | 1988-06-21 | Hitachi, Ltd. | High-speed multiplier having carry-save adder circuit |
US4736335A (en) * | 1984-11-13 | 1988-04-05 | Zoran Corporation | Multiplier-accumulator circuit using latched sums and carries |
US4698760A (en) * | 1985-06-06 | 1987-10-06 | International Business Machines | Method of optimizing signal timing delays and power consumption in LSI circuits |
US4827428A (en) * | 1985-11-15 | 1989-05-02 | American Telephone And Telegraph Company, At&T Bell Laboratories | Transistor sizing system for integrated circuits |
US4811260A (en) * | 1986-11-13 | 1989-03-07 | Fujitsu Limited | Signal processing circuit |
Non-Patent Citations (3)
Title |
---|
IEEE Transactions on Computers, vol C-27, No 9, Sept 1978, IEEE, pp 855-865. * |
Proc IEEE Int Conf on Acoustics, Speech & Signal Processing,Mar 1985, vol 4, IEEE, pp 1461-1464. * |
Proc of Custom Integrated Circuits Conf, May 1989, IEEE, pp 23.2.1-23.2.4. * |
Also Published As
Publication number | Publication date |
---|---|
GB2244829B (en) | 1993-01-13 |
WO1990008362A3 (en) | 1990-09-07 |
GB9114332D0 (en) | 1991-09-04 |
DE4090021T (en) | 1991-11-21 |
JPH04502677A (en) | 1992-05-14 |
WO1990008362A2 (en) | 1990-07-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19980112 |