JPH04502677A - How to analyze data path elements - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] How to analyze data bus elements field of invention TECHNICAL FIELD The present invention relates generally to techniques for determining delays through data bus elements, and In particular, it concerns techniques for determining signal delays through multistage data bus elements. It is something that

A logic unit such as an inverter typically controls each digital bit of the data bus. Works individually on each page. In such units, the operation on one bit is the data There is little, if any, effect on the operation of other bits on the bus. but However, for high-speed multi-stage computation units such as multipliers and The operation of one bit in a bit often depends on the results of operations of other bits. for example, A typical multiplier may include multiple carry-save adders and a final multiply-pull adder. unknown. In such multipliers, the carry bit is often the lower order bit is generated during the operation, and its carry bit is used in higher order bit operations of the multiplier. be exposed. The carry bit must be carried through all bits of the pull adder. The processing time required by the ripple adder is partially multiplied by Depends on the number of bits in the number.

In order to provide high-period operation of the arithmetic function units, so-called pipeline stages are used for the units. Inserted into the knit. Pipeline stages in arithmetic elements have significant advantages However, they also have a latency time (to process one word completely). The required time) can also be increased. In other words, the pipeline stage adds an additional processing step to the arithmetic element so that the element It requires more time to process. Nevertheless, the arithmetic element Output frequency (i.e. processed per unit time) word count) despite the increased latency due to the insertion of pipeline stages in the device. may increase without any change. This result indicates that the pipeline stage processes words with elements first. The problem lies in the fact that it allows the next word to start working before it is completed. follow Although pipeline stages increase the latency of the elements, they also increase the operation of the arithmetic elements. Increase cropping cycle.

Therefore, the use of pipeline stages requires a performance trade-off between period and latency. Ru. necessary to obtain the desired operating period to achieve optimal or near-optimal performance. It is desirable to insert only the minimum number of necessary pipeline stages. In other words , pipeline stages usually connect functional elements at maximum distance. ea+ent).

Effective placement of pipeline stages in a multi-stage data bus device is to requires a fairly accurate estimate of the delay through. Additionally, minimizing computational complexity In order to do so, the placement technique should be relatively simple to implement. Therefore, the book The main purpose of the invention is to provide a simple and effective method for determining the delays encountered in data bus elements. The aim is to clarify the technology.

Brief overview of the invention Briefly, the present invention relates to a method for determining delay through multi-stage data bus elements. It is something that According to the invention, the delay through each stage of data bus elements is one can be estimated by the formula, i.e. Di = Db Nb + C It is. So, is the estimated stage delay, and Db is the delay between bits in one stage. The delay associated with communication, Nb is the number of bits of the data bus element, and C is a constant . Based on the estimated delay, the pipeline stage positions of the data bus functional elements are calculated. It becomes possible to calculate

Brief description of the drawing In the attached drawings, FIG. 1 is a schematic diagram of a conventional 5×5 unsigned carry-save array multiplier; Figure 2 is a schematic logic circuit depicting the full adder circuit used in the multiplier in Figure 1. FIG. 3 is a schematic logic circuit depicting a half adder circuit used in the multiplier of FIG. Figure 4 shows the 5x5 unsigned carry-save array multiplier section including pipeline stages. A schematic circuit, and Figure 5 shows a technique for estimating the delay occurring in an NXM array multiplier. Figure 6 is a diagram provided to aid in explaining the is a functional representation of an NXM array multiplier, and Figure 7 is a flowchart depicting the process of determining the arrangement of pipeline stages of a multi-stage data bus element. -Fig.

Detailed description of the preferred embodiment In the following, the invention will be explained in terms of carry-save array multipliers. deer However, this embodiment is a simple implementation of elements that perform parallel data operations on the data bus. This is an example. In other words, the present invention can be applied to arithmetic operators other than array multipliers. It should be understood that it is possible.

A conventional 5.times.5 carry-save array multiplier 2 is depicted in FIG. Multiplier 2 is It is designed for fast multiplication of two 5-bit numbers A and B. symbol symbol Then, the number A is pitched from the lowest bit to the most significant bit F aO+ a1. a 2+a: includes l and a4. Similarly, the 5-bit number B is bo, b +, bz.

Contains b3 and b4.

Multiplier 2 in FIG. 1 includes multiple columns of full adders, each indicated by the letter FA Consists of steps. Therefore, the first column of multipliers consists of full adders 12, 14, 16 and 18, the second column includes full adders 22, 24, 26 and 28, and the third column includes full adders 22, 24, 26 and 28. including adders 32, 34, 36 and 38, and the fourth column includes full adders 42, 44. ．． 46 and 48 included. The final stage of multiplier 2 is full addition! 52, 54.56 and 58.

In the operation of multiplier 2 in FIG. 1, each full adder receives 3 bits of power; to produce a sum output and a carry output. Focus on various adders in Figure 1 Inputs are listed in Table 1. The total output of the full adder is given by the subscript 'S''. The carry output is indicated by a subscript "C".

Thus, for example, the sum and carry outputs of adder 14 are 14s and 14c, respectively. The “ai bj” inputs listed in Table 1 are ANDed at each address. It shows the respective bits of numbers A and B that are logically combined by an operation.

Adder input Adder input 12 (La+bs, aobt 36 26c+28s+azbs14 0, a zbo+arb+ 38 28C, a4bz+asbz16 0+aJ(1+a ! t)+42 32c, 34s, aoba18 0+aabo+azb+4 4 34C+363+arba22 12c, 14s, aobt 46 3 6c+ 38s, atba24 14c, 16s, a+bl 48 38c+ aabx+a3bs26 16c, 18s+azbz 52 42c+44s , 028 18c, a4b+, a3bz 54 44c, 46s, 52c32 22c, 24s, aobt 56 46c, 48s, 54c34 24c, 26 s, a+b:+58 48c, a4ha+56cTable 1 In a typical system using multiplier 2 in Figure 1, the input cover sofa is is provided before the multiplier to store the multiplier and multiplicand to be processed. moreover, A typical system is suitable for establishing synchronization between a;bJ large inputs to the multiplier. A connected between the cover sofa and the adding stage to ensure that the Use ND gate. Such buffer and gate circuits are not known in the art. For that reason, we will not discuss it further here.

The operation of multiplier 2 will now be described. For such an explanation, the binary number A=10 An example is given where 011 is multiplied by B=01100. (A=19 in decimal) B-12) Multiplication using paper and pencil is described below.

19 = 10011 Multiplicand X12 = XO1100 multiplier ooooo.

ooooo.

ooooo.

228 011100100 product Therefore, the multiplication process of two binary numbers is accomplished by successive additions and shifts. It is understood that In the multiplication process shown above, the consecutive focus of the multiplier is The lowest bit is seen first. If the multiplier bit is 1, the multiplicand is copied Ru. Otherwise zeros are copied. and the number of consecutive columns to the left from the previous column is shifted one position to. Finally the numbers are added to give a sum equal to the product of the multiplications.

The multiplication of the number AXB=P by the multiplier 2 of FIG. The inputs and outputs of are revealed. In the first stage, adders 12, 14, 16 and (18 is the input cell) (0, 0, 0), (0, 0, 0), (0, O, O), (0°0.0) respectively, and the respective output sets (0°0), (0, O), (0, O), (0, O) (sum, carry) is given. The lowest value of the product P The cut is P. −=ao　bo　=0. Bit P is the total output of adder 12 Yes, and in this example it is O. In the second stage, adders 22, 24, 26 and 28 are Input cent (0,0,1), (0,0,1), (0°0,O), (0,O,O ) and output set (1,0).

Give (1,O), (0,0), (0,0). Bit P2 is the sum of adder 22 output, in this case l. Third stage adders 32, 34, 36 and 38 The respective inputs to are (0,1,1), (0,0,1), (0,O,O), (0°1.0), and the respective outputs are (0,1) and (1,O).

(0, O), (1, O). Bit P3 is the sum output of adder 32; is 0. Next, the inputs of the fourth stage are (1, 1, O), (0, O, O), (0, 1,0), (0°1.0), and the respective outputs are (0,1), (0,O).

(1,0), (1,O). In this example, bit P4, the total output of adder 42 is is O.

Further, in the operation of multiplier 2 of FIG. 1 according to the previous example, ripple carry adder 50 The first adder 52 receives the input set (1°Q,0) and provides an output (1,0). I can do it. Therefore, Ps is 1. The adder 54 is sequentially manually operated) (0, 1°O) and outputs (1,0). Bit P6 is therefore 1. addition The adder 56 receives (0, 1, O) and outputs (1°0), and the adder 58 receives (0, 1, O) and outputs (1°0). 0, O, O) and outputs (0, O). Therefore bits P, and P8 are They are 1 and 0, respectively. As you can see, the product p (P, P, Pb Ps P a　P3　Pg　P+　Pa　) is 011100100, which is continuous Consistent with the results drawn above and obtained by the addition and shift technique.

FIG. 2 shows an example of a full adder. In this example, the full adder consists of two XOR gates. The combination of gates 60 and 62, two AND gates 64 and 66, and OR gate 68 Therefore, it is given.

The sum of bits Xi and Yl and input carry bit C8 is Xi + Yi + Ci = It can be expressed as (Xi + Yi) + Ci. Therefore, toft X1 and Y is applied to the input gate of the first XOR gate 60. Output of XOR gate 60 is applied to the input terminal of the XOR gate 62, which receives bit C1 as the second input. receive. The output of XOR gate 62 represents the sum of the input bits.

Furthermore, regarding FIG. 2, the carry output is ci+l = xi y, +Xi Ci It should be understood that it may be expressed as +Yi C4. Rules for pool algebra By manipulating this expression according to the rule, the carry output is C1゜r　=X4　Y6　 It can be expressed as + (XH+Y4)C4. Therefore, in the system of Figure 2 , bits X8 and Yi are applied to the input terminals of AND gate 64. AND game 66 performs an XOR game to produce the resulting representation (Xi + Yi)Ci. ) 60 and an input terminal connected to the input carry bit C1. lastly , and the AND gate 64 to produce the output carry bit C84. The output of gate 66 is connected to the input terminal of OR gate 68.

Referring again to FIG. 1, full adders 12, 14, 16 and 18 are each set to 0. It can be seen that it has one input.

This means that the first stage of each full adder is replaced by a half adder stage to minimize the circuit. Allow yourself to be given. An example of a suitable half-adder circuit is shown in FIG. drawn The half-adder circuit includes an XOR gate 70 and an AND gate 72, each with a receiving It has an input terminal connected to input pin) X= and Yi. XOR gate 70 The total output Si = Xi + Yi is determined, and the AND gate 72 outputs carry -C3゜ , =Xi Y, is determined.

In practice, the carry-save array multiplier 2 as depicted in Figure 1 is relatively fast. It is possible to generate the product of two numbers A and B. In other words, such a circuit It has relatively little latency expressed in terms of clock cycles. However, that A circuit like It is characterized by the fact that it must be processed. More specifically, The multiplier 2 in FIG. The carry bits from 12 are added to adders 22, 32, 42, 52, 54, 56 and 58 for complete transmission. And at that very moment, The multiplier can begin processing other sets of numbers that are multiplied together. Therefore, any given Although it is fast in terms of combining the number of pairs obtained, multiplier 2 in Fig. The output period is relatively slow with respect to the number of different numbers that can be multiplied in a given time interval.

Furthermore, the overall efficiency of the circuit in Figure 1 is such that each full adder in the circuit consumes most of the processing cycles. It can be said that it is low from being an idol for any period of time.

In order to increase the output period of a multi-stage data bus element such as multiplier 2 in FIG. A brine stage can be inserted between one or more of these stages. These parameters The iline stage is essentially a memory that stores the partial results produced by the previous functional stage. It is a register. Also, in a multiplier, the pipeline stage is processed by the later addition stage. It can be used to store multipliers and multiplicands in order to The simplest implementation In this case, the pipeline stage usually consists of two to four D-type flip-flops. , where each flip-flop is equivalent to one input bit to the next stage. It functions to temporarily store one output bit from the previous summing stage. multiplier The advantage of inserting pipeline stages in multi-stage data bus devices such as After forwarding the partial product to the pipeline stage, the adder stage processes the other set of numbers. It is given as such.

Figure 4 shows a carry save array with a pipeline stage inserted between its adder stages. – indicates a multiplier. For simplicity, only the first uni stage of the multiplier is shown. . Through the use of pipeline stages, the multiplier of Figure 4 can provide high output cycles. . This is because the multiplier processes the second pair of numbers before it finishes processing the first pair of numbers. This is because you can start processing numbers. The pipeline stage, however, This increases the number of stages that partial products must be passed through the multiplier. Therefore, this In an arithmetic unit such as a multiplier, there is a pipeline between each addition stage. It is understood that it is not always required or practical to insert an in stage. It should be. Furthermore, the delay through the different summing stages in the multiplier of Fig. 1 is It should be understood that they are not necessarily the same. For example, ripple cap Lee adder 50 typically performs more processing than any one of the first four adder stages. requires more time to complete the processing cycle and is therefore larger. has a long delay. As a result, a pipeline stage is placed between each crotch of the multiplier. Rather, for example, it is possible to place pipeline stages only after the second and fourth adder stages. may be more practical. In that case, the operating period of the multiplier is will be determined by the maximum delay through the processing stages placed between the pline stages. . According to this example, the hardware requirements increase even as the multiplier output period increases. However, it will be reduced to the extent that the increase in latency is minimized. .

The smallest or almost Determine the delay through the individual stages of the element to determine the minimum number of Vibration stages. It is necessary to define

One way to estimate these delays is at the gate level (i.e. per gate) By modeling the element with. According to the gate-level modeling method, the data Tabas elements can be thought of as individual gates associated with their component parts, each with an associated and the sum of the delays through all gates along the path is Gives an estimate of the overall element delay. For example, the delay through the full adder in Figure 2 is Estimated by summing the delays along the bus consisting of XOR gates 60 and 62 It is possible. However, gate-level approaches to modeling delays are always is not valid. There are inefficiencies in that methodology because parallel data In devices with This is because they can be removed. Additionally, gate-level modeling is typically time-consuming. However, the estimation is too strong. Due to such drawbacks, gate-level models is considered impractical in most situations.

Other known methods of estimating delay through a data bus include the delay per data bus element. By modeling the spread. However, such device-level modeling is the timing of the data bus when pipeline stages are added to the data bus elements. It has the disadvantage that it cannot show whether or not it changes. Furthermore, the element The Bell modeling is done by adding pipeline stages to reduce the cycle time of the data bus. The location in the element is not shown so that it may be added.

Therefore, modeling methods estimate the delays encountered at individual stages of a multistage data bus element. required to do. One modeling approach that aligns with this requirement is to The delay through the data bus element stage is a function of the number of bits communicating with the data bus element stage. Therefore, modeling is possible. For example, one particularly adaptable modeling equation is , Da = Db Nb + C (1) , where Dl is the stage delay and Db is the delay proportional to the number of bits of the data bus element. , N1 is the number of bits of the data bus element, and C depends on the number of bits of the data bus. is a constant representing the delay that does not occur. Bit operations do not depend on other bit operations. In all cases, Db is equal to zero.

Equation (1) above is similar to that typically found in adders, ALUs, and multiplier elements. It can be easily applied to multiple carry adder IEs. Such an adder is has a delay resulting from the communication of It can be estimated that On the other hand, elements that do not change or do not communicate with the signal components have no delay proportional to the number of bits on the data bus. Therefore, bit - For components of the element with independent delay, the parameter Db can be set to zero. To demonstrate the use of equation (1) for delay estimation, we construct a multistage data bus element. Reference is made to FIG. In Figure 5, the NXM bit array multiplier is a carry Consists of N bit strings consisting of M rows of save adders and pull-carry adders .

An input cover sofa is provided to temporarily store the multiplicand and multiplier before the first addition stage. It will be done. As depicted in Figure 5, one input buffer stage has an estimated stage delay equal to C. each carry-save adder corrects the estimated delay and The ripple carry adder has an estimated delay of BN+D.

By applying equation (1) to the multiplier in Figure 5, the delay through the first four stages can be can be modeled as C+3A. The delay through the three intermediate stages is 3A. It is possible to model the The delay through the last pull-carry adder is BN+D It can be modeled as Finally, the entire NXM bit multiplier is AM+B It can be modeled as a delay estimated as a whole of N100. , where A is a constant delay through a carry-save adder and B is a ripple carry per bit delay for the adder, C is the input buffer delay, and D is the ripple This is the constant delay of the carry adder.

In Figure 6, there is a pipeline stage after every three carry-save adders. A multistage data bus consisting of the multiplier of FIG. 5 with pipeline stages inserted as follows. elements are shown. Therefore, the modified multiplier has a delay of 3A+C. segment and the final segment with a delay of BN+D (i.e. ripple cap) including a Lee adder stage). Each summing stage has a target for processing by a particular segment. Note that it requires an additional input buffer to store the multiplier and the multiplier. Should. Also, a pipeline stage inserted at the indicated location allows the multiplication The minimum cycle time of the device is the maximum value of 3A+C and BN+D added to the pipeline stage. The total delay caused by

Here, the modeling techniques described above demonstrate that multistage data bus elements are typically It can be understood that this reflects the fact that it includes files. Understand this repetition By doing so, the modeling technique requires relatively less processing time than gate-level modeling. for determining pipeline stage placement, despite requiring time and computational capacity. Provide sufficient details.

A more generalized technique for inserting pipeline stages into multistage data bus devices is Discussed in conjunction with FIG. This technology can be used, for example, in automated integrated circuit design systems. It may also be incorporated into the stem.

The first step in the process, tabulated in Figure 7, is to select the maximum desired delay DH. That is. This delay is typically approximately equal to the inverse of the desired operating period of the data bus elements. may be determined, for example, by the operating period of other functional elements of the data bus. Not possible. Initially, the element stage counter ■ is initialized to zero, and the cumulative delay variable D T is set to zero.

The next step in the process, tabulated in FIG. It is to calculate the extension. In practice, the first indicated column is usually the element being analyzed. The child's final data processing stage appears. For the indicated stage, the calculated stage delay, Dl, is that The maximum delay is compared to . If the delay of the first indicator stage is the maximum delay Ds, If the delay is larger, the maximum delay DH is reset to a value equal to the individual stage delay and the processing is started again.

Otherwise, the total cumulative delay D7 is determined by the stage delay time of the next adjacent stage of the element. will be increased. The increased overall delay D is then compared to the maximum delay time D . If the value D is less than the value D, the stage counter is incremented and delay is calculated for the next stage.

In fact, the process shown in the table in FIG. This continues until it is confirmed that A exceeds the maximum delay D. At that time, the piper The in stage is inserted before the verified stage, and the cumulative delay D↑ is attached to the delay of the verified stage. set equal to the added vibline stage's inherent delay. (first For data flow through a multi-stage element where the instruction stage is the final data flow stage, the package The pipeline stage is inserted “downstream” from the stage where the cumulative delay Da exceeds the maximum delay D9. There will be. ) Then the stage counter is incremented and processing continues on to the next stage. We can continue by considering the elements of Processing is performed through each individual stage of data bus elements. Proceed as described above.

With this concatenation, the basis of the above processing is that the cumulative delay through the multi-stage data bus elements is sequentially calculated. When the stage being calculated and considered has a cumulative delay greater than the desired maximum delay, It is understood that at any time a pipeline stage is inserted within a device. this such that the pipeline stages are arranged at a maximum or near maximum distance from each other. . As a result of the above processing, a multi-stage data base can therefore be created with minimal increase in its latency. This increases the operating cycle of the element.

In practice, the maximum delay D associated with the first designated element stage is related to data flow. to additionally reflect delays through independent elements before and after the indicator stage. (There In this case, the first specified element stage is the final data processing stage of the element, and is an independent element stage. follows the first pointing element in terms of data flow, while The first commanded element stage is its first data processing stage, and the independent element first It precedes the indicating element. ) Furthermore, in performing the above processing, the set The output delay time is taken into account as well as the delay of any pipeline stages of the output and device. must be In such a pipeline stage, elements are added as a result of the analysis. Includes those belonging to the element prior to the above analysis as well as those that were previously analyzed.

The Vibrine, embodiments and operation of the present invention are described in the foregoing specification; The inventions intended to be protected are limited to the specific disclosed form. It has not been. Rather, the disclosed form is to be regarded as illustrative rather than limiting. Should. Those skilled in the art will appreciate that variations and modifications are within the spirit of the invention. It will be understood that it may be done without departing from the concept.

False 'fortune -, t, , L, a, ζ Special Table Sen4-502677 (7) Submission of translation of written amendment (Article 184-8 of the Patent Law) July 1991 IC; Sun

Claims (5)

[Claims] 1. A method of arranging pipeline stages in a multi-stage datapath element, the method comprising: a) For each functional stage of the datapath element, the information associated with communication between bits within the stage; Determine the estimated delay time, which reflects the delay, the number of bits in the datapath elements, and a constant. b) determining the location of the pipeline stage placement according to the estimated stage delay; That, and c) placing the pipeline stage at the determined position; A method characterized by: 2. A method of arranging pipeline stages in a multi-stage datapath element, the method comprising: a) For each functional stage of the datapath element, estimation by substantially the following equation: Determining the delay time, i.e. Ds=DbNb+C where Ds is the estimated stage delay, Db is the delay associated with communication between bits within the stage, and N b is the number of bits in the datapath element, and C is a constant; b) calculating a position of a pipeline stage arrangement according to the estimated stage delay; and c) placing a pipeline stage at the location. How to do it. 3. The location of the pipeline stage power distribution is selected for the estimated stage delay and datapath elements. 3. The method according to claim 2, wherein the calculation is performed based on the calculated operating period. 4. Db is an element stage where the operation regarding a bit does not depend on the operation regarding other bits. 4. A method according to claim 3, characterized in that the method is set equal to zero. 5. A multi-stage datapath element consists of multiple one-dimensional carries followed by a ripple-carry adder stage. - A carry-save array multiplier including a save adder stage. The method described in Section 3.