JPH0449785B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device having an insulating film grown on a semiconductor substrate. . [Background technology] Semiconductor integrated circuit device equipped with dynamic random access memory (hereinafter referred to as DRAM)
The memory cell consists of a series circuit of an information storage capacitive element and a switch MISFET. The information stored in this memory cell is determined to be "1" or "0" by the dummy cell. The dummy cell is
It consists of an information judgment capacitor, a switch MISFET, and a clear MISFET that clears the reference signal accumulated in the information judgment capacitor. The information determining capacitive element needs to have a capacitance value that is half that of the information storage capacitive element in order to determine whether the information is "1" or "0". The information storage capacitive element and the information determination capacitive element are MIS type capacitive elements, that is, composed of a semiconductor, an insulating film, and an electrode. In order to prevent soft errors caused by alpha rays and to achieve high integration, there is a tendency to use pores (or narrow grooves) in information storage capacitive elements and information determination capacitive elements. However, when pores of different shapes and sizes are used, processing variations such as pore processing variations occur in the manufacturing process. In particular, in order to prevent unnecessary increases in the manufacturing process, the pores are configured to have the same depth, so it is necessary to correct three-dimensional processing variations two-dimensionally, such as the shape and size of the pores. occurs. For this reason, although the pores of both capacitive elements have uniform processing variations, the predetermined area ratio changes, making it difficult to configure a capacitance value of 2:1. As a result of studies on such technology, the present inventor has:
We have found a problem in that the margin in the information read operation becomes smaller and malfunctions are more likely to occur, which lowers the electrical reliability of the DRAM read operation. Note that DRAM, which has memory cells composed of information storage capacitive elements that utilize pores, is, for example,
It is described in Japanese Patent Publication No. 58-12739. [Object of the Invention] An object of the present invention is to provide a technique that can improve electrical reliability in a semiconductor integrated circuit device. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows. That is, in a semiconductor integrated circuit device having a capacitive element that utilizes pores, insulating films formed with different crystal planes are used to configure capacitive elements having different predetermined ratios of capacitance values. This makes it possible to use pores of the same shape and size and to suppress variations in the ratio of capacitance values between capacitive elements due to processing variations, thereby improving the electrical reliability of semiconductor integrated circuit devices. be able to. The structure of the present invention will be described below.
This will be explained along with an example in which the present invention is applied to. [Example] FIG. 1 is a diagram for explaining an example of the present invention.
FIG. 2 is an equivalent circuit diagram showing a main part of a DRAM memory cell array. In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. In Figure 1, SA ₁ , SA ₂ , ... are sense amplifiers, and BL ₁₁ , BL ₁₂ , BL ₂₁ , BL ₂₂ are sense amplifiers.
This is a bit line extending in the row direction from one end of SA ₁ and SA ₂ . WL ₁ , WL ₂ are word lines for dummy cells extending in the column direction, and WL ₃ , WL ₄ , . . . are word lines for memory cells extending in the column direction. M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂ , . . . are memory cells that hold charges serving as information. Memory cell M is MISFETQ ₁₁ for switch,
Q ₁₂ , Q ₂₁ , Q ₂₂ , ... and the information storage capacitive element C ₁₁ ,
It is composed of C ₁₂ , C ₂₁ , C ₂₂ ,... Vcc is a fixed potential Vcc terminal (for example, 5 [V] or more than the threshold voltage [Vth] that forms an inversion layer)
It is. D ₁₁ , D ₁₂ , D ₂₁ , D ₂₂ ,... are dummy cells,
It is designed to hold such charge that it is possible to determine whether the information of the memory cell M is "1" or "0". Dummy cell D is MISFET for switch _{Q D11} , Q _D12 ,
Q _D21 , Q _D22 ,... and information determination capacitive element C _D11 ,
C _D12 , C _D21 , C _D22 ,... and information judgment capacitive element C _D
For clearing to clear the charge accumulated in
It is composed of MISFETCQ. _φD is a terminal connected to the gate electrode of MISFETCQ for clearing. The memory cell array includes a plurality of memory cells M arranged in rows and columns. The dummy cell array is configured by arranging a plurality of dummy cells D in a matrix. Next, a specific configuration of an embodiment of the present invention will be described. 2 to 8 are diagrams of a DRAM for explaining one embodiment of the present invention, and FIG. 2 is a schematic plan view of a wafer showing the arrangement of memory cells and dummy cells, and FIG. 4 is a plan view of essential parts of the memory cell array and dummy cell array in a predetermined manufacturing process, FIG. 5 is a perspective sectional view taken along the -cutting line in FIG. 3, and FIG. 6 is a -cutting line in FIG. 4. 7 is a perspective sectional view taken along the - section line in FIG. 3, and FIG. 8 is a sectional view taken along the - section line in FIG. 4. Note that in FIGS. 3 and 4, insulating films provided between each conductive layer are not shown in order to make the structure easier to understand. In FIGS. 2 to 8, reference numeral 1 denotes a wafer (semiconductor substrate) made of p ^- type single crystal silicon, and is used to configure a DRAM. This wafer 1 is composed of an orientation flat 1A having a (100) crystal plane and a semiconductor element forming surface (principal surface portion) 1B having a (100) crystal plane. 1C is a pattern of a plurality of semiconductor chips formed on the wafer 1 before dicing. 2 is a field insulating film between memory cells,
Between dummy cells and peripheral circuits (not shown),
For example, it is provided on the upper main surface of the semiconductor substrate 1 between semiconductor elements constituting a read circuit and a write circuit. The field insulating film 2 is configured to electrically isolate semiconductor elements and define regions in which they are formed on the semiconductor substrate 1. This field insulating film 2 is formed by selective thermal oxidation technology of the semiconductor substrate 1. 3A and 3C are pores (or narrow grooves), and pore 3
A is cut in the main surface of the semiconductor substrate 1 in the memory cell formation region, and a pore 3C is provided in the main surface of the semiconductor substrate 1 in the dummy cell formation region. Pore 3A is orientation flat 1A
The shape is configured along the a-a line orthogonal to the line or the parallel b-b line. That is, all the side surfaces of the pore 3A are composed of (100) crystal planes, and the bottom surface thereof is composed of (100) crystal planes. The pore 3A constitutes an information storage capacitive element. Pore 3C is orientation flat 1A
The shape is constructed along the c-c line that intersects with the angle of about 45[degrees]. That is, all the side surfaces of the pore 3C are composed of (110) crystal planes, and the bottom surface thereof is composed of (100) crystal planes. The pore 3C is configured to constitute a capacitive element for information determination. The pores 3A and 3C are formed by the same manufacturing process, for example, using an anisotropic etching technique.
It is a rectangular shape with dimensions of approximately 1.0 × 2.0 [μm], and 5.0 [μm].
m] depth. 4A and 4C are insulating films, and at least pore 3
It is provided on the upper main surface of the semiconductor substrate 1 along lines A and 3C. The insulating films 4A and 4C are formed of silicon oxide films formed by thermal oxidation technology. The insulating film 4A constitutes a capacitive element for information storage, and the insulating film 4C constitutes a capacitive element for information determination. The growth rate of the insulating films 4A and 4C is dependent on the crystal plane, and can be formed to have a thickness as shown in Table 1 listed at the end of the specification, for example. Regarding the crystal plane dependence of the growth rate of silicon oxide films, see, for example, Kogyo Kenkyukai Publishing,
It is described in Junichi Nishimura (ed.), Semiconductor Research 16, VLSI Technology 3, Semiconductor Process, p271, p272. Thereby, an information storage capacitor element and an information determination capacitor element having a predetermined capacitance value can be constructed using the pores 3A and 3C having the same shape and dimensions. In other words, it is possible to substantially uniformize processing variations in the corners of the pores 3A, 3C due to the etching technology in the manufacturing process, and the capacitance values of the information storage capacitor element and the information determination capacitor element can be adjusted to the insulating films 4A, 4C.
The film thickness can be approximately set at . Therefore,
Since fluctuations in the ratio of capacitance values between the information storage capacitor and the information determination capacitor can be suppressed, the margin in the information read operation can be increased. In addition, the capacitance of the information storage capacitor or the information determination capacitor is approximately determined by the side surfaces of the pores 3A and 3C, which have large areas, but the shape of the field insulating film 2 determines the difference in the capacitance between the two. You may make adjustments. Reference numeral 5 denotes a conductive plate, which is provided above the insulating films 4A, 4C so as to fill the pores 3A, 3C, and to be integrated and electrically connected to the adjacent ones. The conductive plate 5 constitutes one electrode (connected to the terminal Vcc) of the information storage capacitive element or the information determination capacitive element. The conductive plate 5 is, for example, a CVD
It consists of a polycrystalline silicon film formed using technology. The information storage capacitive element C mainly includes a main conductor substrate 1, a pore 3A, an insulating film 4A, and a conductive plate 5.
It is composed of. The information determining capacitive element _CD is mainly composed of a semiconductor substrate 1, a pore 3C, an insulating film 4C, and a conductive plate 5. An insulating film 6 is provided to cover the conductive plate 5. The insulating film 6 is the conductive plate 5
and a conductive layer provided thereon are electrically isolated from each other. Reference numeral 7 denotes an insulating film, which is mainly provided on the upper main surface of the semiconductor substrate 1 in the MISFET formation region. The insulating film 7 is configured to mainly constitute a gate electrode of a MISFET. 8A or 8B is a conductive layer, which is provided on a predetermined upper part of the insulating layers 7 and 6. The conductive layer 8A mainly constitutes the gate electrode of the MISFET. The conductive layer 8B constitutes a word line WL. The conductive layers 8A and 8B are
For example, polycrystalline silicon film, high melting point metal film (Mo,
Ta, Ti, W), silicide film (MoSi ₂ , TaSi ₂ ,
TiSi ₂ , WSi ₂ ) or a combination thereof. Reference numeral 9 denotes an n ⁺ type semiconductor region, which is provided on the main surface of the semiconductor substrate 1 on both sides of the conductive layer 8A.
The semiconductor region 9 is configured to mainly constitute a source region or a drain region of a MISFET. MISFETQ, Q _D , and CQ are mainly composed of a semiconductor substrate 1 , an insulating film 7 , a conductive layer 8 , and a pair of semiconductor regions 9 . Reference numeral 10 denotes an insulating film, which is provided to cover the conductive layers 8A and 8B. The insulating film 10 is a conductive layer 8
It is configured to electrically isolate A and 8B from a conductive layer provided thereon. Reference numeral 11 denotes a connection hole, which is provided by removing the insulating films 7 and 10 above a predetermined semiconductor region 9. A conductive layer 12 is provided extending over the insulating film 10 so as to be electrically connected to a predetermined semiconductor region 9 via the contact hole 11 . This insulating film 12 constitutes a bit line BL. The conductive layer 12 is made of, for example, an aluminum film. In this embodiment, semiconductor elements such as memory cells are formed on the semiconductor substrate 1, but a well region may be provided and the semiconductor element may be formed in the well region. Further, the capacitive element is set to 1/2 Vcc (≒2.5 [V]), which is approximately half the voltage Vcc applied to the conductive plate 5, and an n-type semiconductor region is provided on the substrate surface of the capacitive element part. Good too. By doing so, it is possible to make more effective use of the technique of forming a thin oxide film whose thickness is accurately controlled in consideration of the dependence of crystal planes. That is, by lowering the voltage applied to the conductive plate 5, the insulation film breakdown voltage of the insulation film of the dielectric film of the capacitive element can be made relatively small, so the film thickness can be reduced and the capacitance per unit area can be reduced. You can make it bigger. Also, the voltage applied to the conductive plate 5 is set to the ground potential Vss (=0
[V]) may also be used. [Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained. (1) In a semiconductor integrated circuit device having a capacitive element that utilizes pores, by configuring capacitive elements with different predetermined capacitance values using insulating films formed with different crystal planes, it is possible to create capacitors with the same shape. ,
Since pores with different dimensions can be used, it is possible to suppress variations in the ratio of capacitance values between capacitive elements due to variations in processing. (2) According to (1) above, the capacitance value of the information storage capacitor element and the information determination capacitor element of DRAM is approximately 2:1.
Therefore, the margin in the read operation can be increased. (3) According to (2) above, malfunctions in information read operations can be suppressed, so the electrical reliability of the DRAM can be improved. (4) According to (1) above, a complicated circuit such as, for example, a 1/2 Vcc system is not required, so the circuit design becomes simple. (5) According to (1) above, capacitive elements with different capacitance values can be configured without increasing the number of manufacturing steps. As above, the invention made by the present inventor has been specifically explained based on the above-mentioned Examples, but the present invention is not limited to the above-mentioned Examples, and the present invention can be applied within the scope of the invention without departing from the gist thereof. Of course, various modifications can be made. For example, in the embodiments described above, the present invention is applied to a DRAM, but the present invention can be applied to any semiconductor integrated circuit device having capacitive elements with different capacitance values. Further, in the above embodiments, the present invention is applied to a semiconductor integrated circuit device having capacitive elements having different capacitance values, but
It may also be applied to a semiconductor integrated circuit device having MISFET. 【table】

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the present invention.
2 to 8 are equivalent circuit diagrams showing main parts of a DRAM memory cell array. FIGS. 2 to 8 are diagrams of a DRAM for explaining an embodiment of the present invention. FIG. FIGS. 3 and 4 are plan views of main parts of the memory cell array and dummy cell array in a predetermined manufacturing process, and FIG. 5 is a schematic plan view of the wafer shown in FIG.
6 is a sectional view taken along the cutting line - in FIG. 4, FIG. 7 is a perspective sectional view taken along the - cutting line in FIG. 3, and FIG. 8 is a sectional view taken along the cutting line -
FIG. 4 is a sectional view taken along the - section line in FIG. 4. In the figure, 1... wafer (semiconductor substrate), 3...
Pore, 4, 7... Insulating film, 5... Conductive plate,
8... Conductive layer, 9... Semiconductor region, M... Memory cell, D... Dummy cell, C... Capacitive element for information storage, C _D ... Capacitive element for information determination, Q, Q _D , CQ
...It is MISFET.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a capacitive element configured by providing a pore or a narrow groove in a semiconductor substrate, and providing an insulating film and a conductive film along the pore or narrow groove, providing a first capacitive element configured using an insulating film formed on a first crystal plane of the semiconductor substrate;
A semiconductor integrated circuit device comprising a second capacitive element configured using an insulating film formed in a second crystal plane different from the first crystal plane. 2 The first capacitive element and the second capacitive element are
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device comprises a dynamic random access memory. 3 The first capacitive element or the second capacitive element is
Claim 2, characterized in that the capacitive element is configured as an information storage capacitive element or an information determining capacitive element.
2. The semiconductor integrated circuit device described in . 4 The first crystal plane or the second crystal plane is the first crystal plane.
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a side view of a pore or a narrow groove of a capacitive element or a second capacitive element. 5. The semiconductor integrated circuit device according to claim 1, wherein the first crystal plane is a (100) plane, and the second crystal plane is a (110) plane.