WO2001099162A2 - Gate oxidation for vertical trench device - Google Patents
Gate oxidation for vertical trench device Download PDFInfo
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- WO2001099162A2 WO2001099162A2 PCT/US2001/019882 US0119882W WO0199162A2 WO 2001099162 A2 WO2001099162 A2 WO 2001099162A2 US 0119882 W US0119882 W US 0119882W WO 0199162 A2 WO0199162 A2 WO 0199162A2
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- WIPO (PCT)
- Prior art keywords
- trench
- crystal plane
- substrate
- sidewalls
- oxide
- Prior art date
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- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 11
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
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- 238000013459 approach Methods 0.000 description 5
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- 238000003860 storage Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 238000013500 data storage Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
Definitions
- the present invention relates generally to an integrated circuit ("IC") and method of forming thereof, and more particularly to an integrated circuit vertical trench device and method of forming thereof.
- IC integrated circuit
- the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device, and devices have approached sizes down to tenths of microns and less.
- devices There is some limit, however, as to how far a horizontally oriented semiconductor device can be shrunk, and as devices are made even smaller, it is generally becoming increasingly difficult to further miniaturize a device's horizontal dimensions.
- the decreasing horizontal dimensions of semiconductor devices generally tend to create problems in the operational characteristics of the semiconductor devices.
- DRAM dynamic random access memory
- a DRAM may include millions or billions of individual DRAM cells, each cell storing one bit of data.
- a DRAM memory cell typically includes an access field-effect transistor (“FET”) and a storage capacitor.
- FET access field-effect transistor
- the access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations.
- the data charges on the storage capacitor are periodically refreshed during a refresh operation.
- Semiconductor memory density is typically limited by a minimum lithographic feature size that is imposed by lithographic processes used during fabrication. There is a continuing need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs.
- One way of increasing the data storage capacity of semiconductor memories is to reduce the amount of integrated circuit horizontal planar area consumed by each memory cell. For horizontally oriented devices, this may be done by decreasing the size of the access FET or the storage capacitor, or both. This approach has limits, however, due to minimum producible structure size in a given fabrication technology, and the problems associated with devices with small dimensions, such as hot carriers, punch through, and excess leakage.
- planar area reduction is the use of a three-dimensional arrangement of the access FET and the storage capacitor.
- One such arrangement is a planar FET next to a deep trench capacitor.
- a trench typically has a depth of 5-8um and an oval top-down-view shape.
- the trench capacitor has plates which are located vertically along the walls of the trench instead of being parallel to the surface of the integrated circuit substrate. This permits a large capacitance per planar unit area of substrate, while at the same time allowing the device to be of a manageable size for purposes of operation.
- the vertical trench transistor in conjunction with a vertical trench capacitor in a memory cell.
- the vertical capacitor is generally fabricated in a trench, with one conductive plate being formed in the substrate, the dielectric being formed on the trench sidewalls, and the other conductive plate being formed in the interior of the trench.
- a vertical trench transistor is generally fabricated adjacent to an upper portion of the trench, with the source and drain being fabricated in the substrate, and the vertically-oriented gate being fabricated in the trench.
- the gate insulator is an oxide produced by thermal oxidation of the trench sidewall.
- the thickness of the gate insulator generally determines the threshold voltage required to turn on the device. Ideally, the gate insulator thickness should be uniform along the channel length and width.
- the oxidation rate of the trench sidewall is generally highly dependent upon the crystal plane orientation of the sidewall.
- different crystal planes may generate oxides of very different thicknesses when subjected to the same thermal oxidation process.
- a trench formed in a substrate e.g., a rounded (including oval) trench, top-down view
- different crystal orientations are exposed to the oxidation process because the sidewalls cut through different crystal planes in the substrate.
- Thermal oxidation of the sidewalls thus results in different oxide thicknesses around the trench dependent upon crystal orientation.
- a non-uniform oxide thickness for the gate insulator may cause leakage and other device reliability problems.
- the non-uniformity may cause inconsistent threshold voltages from device to device.
- One proposal to alleviate this problem is a selective wet etch using, for example, an NH 4 OH solution.
- This solution generally etches the ⁇ 100> crystal planes faster than the ⁇ 110> crystal planes, which may result in an octagonal trench shape with relatively longer ⁇ 110> plane sides (4 of the 8 sides), and smaller ⁇ 100> plane cut-off corners (the other 4 sides).
- the oxidation rate between the ⁇ 110> planes and the ⁇ 100> crystal planes is typically on the order of 2:1.
- the primary ⁇ 110> sides grow a thick oxide
- the ⁇ 100> corners grow a thinner oxide.
- the active area of the vertical trench is formed adjacent to a ⁇ 110> plane side with the thick oxide serving as a gate oxide.
- a selective etch is used to provide a different crystal plane orientation on the trench sidewalls than that of prior art devices.
- a ⁇ 100> crystal plane sidewall is used for the channel region, and ⁇ 110> crystal planes are used in the corner regions.
- Gate oxidation may then be performed such that the oxide is thicker in the corner regions than on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area.
- a DRAM IC comprises a deep trench located in a semiconductor substrate, the trench having an upper portion comprising primary sidewalls with a second crystal plane and comer sidewalls with a first crystal plane, a thin oxide on at least one primary sidewall, a thick oxide on two corner sidewalls adjacent the at least one primary sidewall, and an active area of a vertically oriented device located in the substrate adjacent the at least one primary sidewall.
- the first crystal plane is a ⁇ 110> crystal plane
- the second crystal plane is a ⁇ 100> crystal plane.
- a method of forming a vertically oriented device on a semiconductor substrate comprises forming a deep trench in the semiconductor substrate, wherein the trench has a rounded perimeter, and wherein the trench comprises sidewalls with first and second substrate crystal planes, selectively etching the first substrate crystal plane in at least an upper portion of the trench using a crystal plane dependent etch, thereby forming trench primary sidewalls comprising the second crystal plane, and smaller trench corner sidewalls comprising the first crystal plane, oxidizing at least one primary sidewall and two adjacent corner sidewalls using crystal plane dependent oxidation, wherein a thin oxide is formed on the at least one primary sidewall, and wherein a thick oxide is formed on the adjacent trench corner sidewalls, and forming an active area of the vertically oriented device in the substrate adjacent the thin oxide.
- an HF/H 2 O 2 wet solution is used for the selective etch.
- the oxidation is selective toward the first substrate crystal plane over the second substrate crystal plane by
- An advantage of a preferred embodiment of the present invention is that a DRAM, memory cell may be formed with a trench capacitor and a vertical transistor, thus using devices of manageable size yet occupying minimal horizontal planar area.
- Another advantage of a preferred embodiment of the present invention is that the vertical gate oxide is substantially uniform across the channel width and length, providing reduced chance of leakage, and consistent threshold voltages from device to device.
- Another advantage of a preferred embodiment of the present invention is that the corners of the trench provide a thick grown oxide for device isolation.
- Another advantage of a preferred embodiment of the present invention is that the resulting structure is relatively insensitive to active area/deep trench misalignment, providing for a more robust process than those used in the prior art.
- Another advantage of a preferred embodiment of the present invention is that the difference in the oxide thickness around the vertical trench surface/sidewall corner is minimized because the relatively thinner oxide is intended to coincidence with the transistor channel.
- FIGURES 1A and 1B are plan and cross-sectional views, respectively, of a prior art round deep trench
- FIGURES 2-5 are plan views of the prior art structure of FIGURE 1 at various subsequent stages of fabrication
- FIGURES 6A and 6B are plan and cross-sectional views, respectively, of a round deep trench in accordance with a preferred embodiment.
- FIGURES 7-10 are plan views of the structure of FIGURE 6 at various subsequent stages of fabrication.
- the invention relates to integrated circuits, including memory ICs such as random access memories (“RAM”s), DRAMs, synchronous DRAMS ("SDRAM”s), merged DRAM- logic circuits ("embedded DRAM”s), or other circuits.
- RAM random access memories
- DRAM dynamic random access memories
- SDRAM synchronous DRAMS
- merged DRAM- logic circuits merged DRAM- logic circuits
- semiconductor processes and structures including vertical capacitors, vertical transistors, trench capacitors and trench transistors, the connections between such semiconductor devices, or other processes and structures.
- Figs. 1A and 1 B there are illustrated a top-down view and a cross- sectional view, respectively, of an initial fabrication stage of prior art device 100 comprising deep trench 102 etched into silicon substrate 104.
- Trench 102 typically has an oval shaped with rounded sidewalls. Sides 106 and 108 of trench 102 have a ⁇ 110> crystal plane orientation, while corners 110 of trench 102 have a ⁇ 100> crystal plane orientation.
- the sidewalls of trench 102 are further etched, for example, to provide a flatter surface on which to form a gate oxide. As shown in Fig.
- a selective wet etch using NH 4 OH is selective to the ⁇ 100> crystal planes over the ⁇ 110> crystal planes, thus forming a trench with primarily ⁇ 110> crystal plane sidewalls 112 and 114, and ⁇ 100> crystal plane corners 116.
- the etched sidewalls of the trench are thermally oxidized to form a gate oxide for the vertical trench transistor.
- the thermal oxidation process is crystal plane dependent, and is selective to the ⁇ 110> crystal plane over the ⁇ 100> crystal plane, typically by a ratio of about 2:1. Therefore a thin oxide 122 is formed in the trench corners, and a thick oxide 118, 120 is formed on the trench primary sides. In Fig. 3, thick oxide 118 is intended to be a gate oxide for the transistor.
- active area 124 for the transistor is formed in substrate 104 adjacent thick gate oxide 118.
- the threshold voltage for the transistor is determined by the thickness of thick oxide 118.
- a problem may exist however, with the thin oxide 122 at the corners of the trench. If the ⁇ 100> crystal plane overlaps with active area 124, then active area 124 will intersect with a thinner oxide over at least a portion of the active area. This may detrimentally affect the threshold voltage of the device, device leakage, and device reliability.
- the device is also susceptible to process variations. Active area 126 is misaligned with thick gate oxide 118, causing it to intersect with thin oxide 122, with the same potential device problems as discussed above.
- Figs. 6A and 6B there are illustrated a top-down view and a cross-sectional view, respectively, of an initial fabrication stage of vertical device 200 comprising deep trench 202 etched into silicon substrate 204.
- Trench 202 preferably has ah oval shaped with rounded sidewalls.
- sides 206 and 208 of trench 202 have a ⁇ 100> crystal plane orientation, while corners 210 of trench 202 have a ⁇ 110> crystal plane orientation.
- the design or wafer notch orientation has been rotated, for example, about 45° from that shown in Figs. 1A-1 B.
- a trench capacitor may be formed in a lower portion of trench 202, comprising an outer plate formed in the substrate (e.g., by doping), a node dielectric (e.g., silicon dioxide) formed on the trench sidewalls and an inner plate (e.g., polysilicon) formed in trench 202.
- An isolation collar e.g., silicon dioxide
- a buried strap connection may be formed between the trench capacitor inner electrode and the region of the substrate which will contain the transistor active area.
- a selective etch is performed on the exposed substrate sidewalls.
- the selective etch may be performed on the whole trench, or more preferably on just an upper portion of the trench.
- the selective etch may be performed on the entire upper portion of the trench, or more preferably on one section of the trench upper portion.
- an H 2 O/HF/H 2 O 2 solution with a ratio of 200:1 :4, respectively, is used to perform the wet etch, although other etching solutions and concentrations may be used.
- a trench top oxide may be formed in the trench overlying the polysilicon capacitor inner plate and the polysilicon buried strap.
- the trench top oxide is preferably silicon dioxide, but may be silicon nitride or any other suitable insulator material.
- a sacrificial oxidation/etching may also be performed to remove excess polysilicon material from the trench.
- dopant implantation may be performed to change the conductivity of particular layers.
- the exposed sidewalls of trench 200 are subjected to thermal oxidation to form the transistor gate oxide.
- a conventional thermal gate oxidation with well known reliability parameters is preferably used.
- the ⁇ 100> crystal planes on primary sidewalls 212 and 214 generally oxidize only about half as fast as the ⁇ 110> crystal planes on corner sidewalls 216.
- the slower growing oxidation permits better thickness and uniformity control of the gate oxide formed on primary sidewall 212 than prior art approaches.
- thin oxides 218 and 220 are formed on the primary sidewalls of the trench, while thick oxides 222 are formed on the corner sidewalls.
- the difference in the ⁇ 110>: ⁇ 100> oxidation rate is now a beneficial process characteristic because the thick oxides on the ⁇ 110> planes provide self-isolation of the corner areas.
- thin oxide 218 is used as the gate oxide for the vertical trench transistor.
- a transistor active area 224 is implanted in the substrate adjacent gate oxide 218. Only the ⁇ 100> crystal plane trench sidewall is used for the transistor channel region, instead of the ⁇ 110> crystal plane used in the prior art.
- the thickness of thin gate oxide 218 is well-controlled and is uniform across the channel region, providing improved device reliability and consistent threshold voltages from device to device.
- An example demonstrating the improved robustness of the process is illustrated in Fig. 10.
- the structure is generally less sensitive to active area/trench misalignment than structures in the prior art.
- active area 226 is misaligned with the gate oxide 218, and actually overlaps corner sidewall thick oxide 222. Introducing a thick oxide into the active area/gate oxide interface, however, does not significantly degrade the performance of the transistor, because the thin oxide still primarily determines the device is characteristics.
- DRAM cell including connections to word and bit lines, may be completed using conventional DRAM processing techniques.
- the resulting DRAM may then be employed in a variety of cpmmercial and consumer electronics devices, including computers.
- the transistor active area may be formed at an angle to the primary sidewall of the deep trench, or may intentionally overlap with the thick oxide in the corner sidewalls.
- the vertical transistor is preferably a single side transistor, but may be implemented in other ways.
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
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- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
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Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01948584A EP1292982A2 (en) | 2000-06-21 | 2001-06-21 | Gate oxidation for vertical trench device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US59878800A | 2000-06-21 | 2000-06-21 | |
US09/598,788 | 2000-06-21 |
Publications (2)
Publication Number | Publication Date |
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WO2001099162A2 true WO2001099162A2 (en) | 2001-12-27 |
WO2001099162A3 WO2001099162A3 (en) | 2002-07-18 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US2001/019882 WO2001099162A2 (en) | 2000-06-21 | 2001-06-21 | Gate oxidation for vertical trench device |
Country Status (3)
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EP (1) | EP1292982A2 (en) |
TW (1) | TW526584B (en) |
WO (1) | WO2001099162A2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4217420A1 (en) * | 1991-05-27 | 1992-12-03 | Mitsubishi Electric Corp | Trench storage capacitor for high density DRAM(s) - uses rectangular trench with (100) walls and bottom plane to improve oxide thickness and threshold control with die oriented parallel to (110) planes |
US5861104A (en) * | 1996-03-28 | 1999-01-19 | Advanced Micro Devices | Trench isolation with rounded top and bottom corners and edges |
US5905283A (en) * | 1994-08-31 | 1999-05-18 | Nec Corporation | Method of forming a MOS transistor having gate insulators of different thicknesses |
EP1071129A2 (en) * | 1999-07-22 | 2001-01-24 | Infineon Technologies North America Corp. | Crystal-axis-aligned vertical side wall DRAM and process for manufacture thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61194867A (en) * | 1985-02-25 | 1986-08-29 | Hitachi Micro Comput Eng Ltd | Semiconductor integrated circuit device |
JPS63197365A (en) * | 1987-02-12 | 1988-08-16 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPH01189172A (en) * | 1988-01-25 | 1989-07-28 | Sharp Corp | Semiconductor device |
-
2001
- 2001-06-21 WO PCT/US2001/019882 patent/WO2001099162A2/en not_active Application Discontinuation
- 2001-06-21 EP EP01948584A patent/EP1292982A2/en not_active Withdrawn
- 2001-06-21 TW TW090115145A patent/TW526584B/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4217420A1 (en) * | 1991-05-27 | 1992-12-03 | Mitsubishi Electric Corp | Trench storage capacitor for high density DRAM(s) - uses rectangular trench with (100) walls and bottom plane to improve oxide thickness and threshold control with die oriented parallel to (110) planes |
US5905283A (en) * | 1994-08-31 | 1999-05-18 | Nec Corporation | Method of forming a MOS transistor having gate insulators of different thicknesses |
US5861104A (en) * | 1996-03-28 | 1999-01-19 | Advanced Micro Devices | Trench isolation with rounded top and bottom corners and edges |
EP1071129A2 (en) * | 1999-07-22 | 2001-01-24 | Infineon Technologies North America Corp. | Crystal-axis-aligned vertical side wall DRAM and process for manufacture thereof |
Non-Patent Citations (3)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 011, no. 023 (E-473), 22 January 1987 (1987-01-22) & JP 61 194867 A (HITACHI MICRO COMPUT ENG LTD;OTHERS: 01), 29 August 1986 (1986-08-29) * |
PATENT ABSTRACTS OF JAPAN vol. 012, no. 481 (E-694), 15 December 1988 (1988-12-15) & JP 63 197365 A (MATSUSHITA ELECTRIC IND CO LTD), 16 August 1988 (1988-08-16) * |
PATENT ABSTRACTS OF JAPAN vol. 013, no. 481 (E-838), 31 October 1989 (1989-10-31) & JP 01 189172 A (SHARP CORP), 28 July 1989 (1989-07-28) * |
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TW526584B (en) | 2003-04-01 |
EP1292982A2 (en) | 2003-03-19 |
WO2001099162A3 (en) | 2002-07-18 |
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