JPH0449715A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To suppress the steep rise of the output wave form of an ECL logic circuit by attaching delay time difference to the driving signal of two output transistors. CONSTITUTION:The output of a driving circuit 1 which inputs an input signals from an input terminal is connected to the base of the output transistor 4. Also, the output of a driving circuit 2 to which the same input signal as that to the driving circuit 1 is inputted via a delay circuit 3 is connected to the base of the output transistor 5. The collectors and emitters of the output transistors 4, 5 are connected mutually, which forms the output of an emitter- follower. Only the output transistor 4 is driven at initial rise time, and no output transistor 5 is driven since it is a delay circuit, therefore, the rise of the output wave form is moderated. After the lapse of prescribed delay time, the output transistor 5 is driven. Thereby, the rise of the output is not steepened, and the occurrence of ringing, etc., can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor logic circuit, and particularly to a semiconductor logic circuit including an output circuit of an ECL type logic circuit.

[Conventional technology]

Conventionally, the output circuit of this type of ECl-type logic circuit is
As shown in the figure, it is composed of a drive circuit 1 that drives according to a signal from an input terminal, and an output transistor 2 that generates an ECL level output signal to the output wheel.

[Problem to be solved by the invention]

In the conventional ECL type logic circuit described above, the drive factor is set to a value that can sufficiently drive the output load.
As shown in Figure 4, the output waveform has a steep rise to F.
This may cause ringing or noise, and in severe cases may cause malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor logic circuit that can prevent a steep rise in an output waveform.

[Means for resolving division issues]

The ECL logic circuit of the present invention includes a first drive circuit, and a second drive circuit in which the input signals input to the first drive circuit and the same input signals (e, -x) are inputted manually via an extension circuit. , a first output I to which the output of the first drive circuit is connected to the base.
- a second output transistor, such as a transistor, to which the output of the second drive circuit is connected to the base; 1, the mitter and the collector of the first and second transistors; [Embodiment] Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit showing one embodiment of the present invention.

The output of the drive circuit J, which receives the input signal from the input terminal, is connected to the base of the output transistor 4. Further, the output of the drive circuit 2, which receives the input signal from the drive circuit 1 via the delay circuit 3, is connected to the base of the output transistor 5. Output 1 - The collectors and emitters of transistors 4 and 5 are connected to each other to form the output of an emitter follower.

FIG. 2 does not show the F18 output waveform according to this embodiment. As shown in the figure, at the initial stage of rising 1-5, only the output transistor 4 is driven, and the 8-output transistor 5 is not driven because of the delay circuit, so the rise of the output waveform is gradual. Become. Thereafter, after a predetermined delay time has elapsed, the output l transistor 5 is driven.

As a result, the rise of the output does not become steep, and the occurrence of ringing and the like can be suppressed.

The delay circuit explained here may have a circuit configuration,
It may also be an element such as a resistor.

Of course, setting the delay time in delay circuit 3, output 1
-Free standing by changing the capacity of the transistor 4.5)
Needless to say, it is possible to control the waiting time.

〔Effect of the invention〕

As explained above, by creating a delay time difference in the drive signals of the two output transistors of the present invention, ECL
This has the effect of suppressing the rise of the output waveform of the logic circuit from becoming steep, and suppressing the occurrence of linking and the like.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a circuit diagram showing a conventional example. FIG. 4 is an output waveform diagram of the conventional logic circuit shown in FIG. 1.2...Drive circuit, 3...Delay circuit, 4.5...
・Output l~ransistor. floor 1 diagram

Claims (1)

[Claims] A first drive circuit, a second drive circuit that receives the same input signal as the first drive circuit via a delay circuit, and an output of the first drive circuit connected to a base. and a second output transistor having a base connected to the output of the second drive circuit, and an emitter follower in which the emitters and collectors of the first and second transistors are connected to each other. A semiconductor logic circuit characterized by having an output.