JPH0449646A - Ic package - Google Patents

Ic package

Info

Publication number
JPH0449646A
JPH0449646A JP16013690A JP16013690A JPH0449646A JP H0449646 A JPH0449646 A JP H0449646A JP 16013690 A JP16013690 A JP 16013690A JP 16013690 A JP16013690 A JP 16013690A JP H0449646 A JPH0449646 A JP H0449646A
Authority
JP
Japan
Prior art keywords
lead frame
package
die pad
ground
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16013690A
Other languages
Japanese (ja)
Inventor
Shunsuke Fujimoto
俊介 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16013690A priority Critical patent/JPH0449646A/en
Publication of JPH0449646A publication Critical patent/JPH0449646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Abstract

PURPOSE:To decrease inductance and reduce ground noise by putting it in the double lead frame structure wherein the lead frame of an IC package is double, and uniting its one set with a die pad, and also making all pins into ground pins. CONSTITUTION:An IC package has the shape of double frame structure comprised of a lead frame 2 and a lead frame 3 of J type united with a die pad, or the like. The lead frame united with a die pad is in the shape of a plate inside the package body (mold part), and has the shape of a lead frame outside the package body 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＩＣパッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an IC package.

〔従来の技術〕[Conventional technology]

従来、この種のＩＣパッケージは、−組のリードフレー
ムしか持たず、従ってグランドピンは１本であり、同時
スイッチング時には、グランドピンのインダクタンスが
大きい為、グランドノイズが大きく、誤動作が起きやす
くなっていた。Conventionally, this type of IC package has only one pair of lead frames, and therefore has one ground pin.During simultaneous switching, the inductance of the ground pin is large, causing large ground noise and making malfunctions more likely. Ta.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のＩＣパッケージは、ダイパッドとグラン
ドピンのリードフレームが各々別の部品で構成される為
、チップのグランドとグランドピンのリードフレームは
、長いボンディングワイヤで結ばなければならず、又、
グランドピンは大抵の場合コーナーピンであり、しかも
１本しかないので、チップよりプリント配線基板までの
インダクタンスは大きく、グランドノイズの発生源にな
っていた。In the conventional IC package described above, the die pad and ground pin lead frames are each made up of separate parts, so the chip ground and ground pin lead frames must be connected with long bonding wires.
In most cases, the ground pin is a corner pin, and since there is only one, the inductance from the chip to the printed wiring board is large and becomes a source of ground noise.

又、グランドノイズをおさえる為には、グランドピンの
センターピン化が上られるが、従来のものとピンコンバ
チでなくなるので使用しにくいという欠点があった。In addition, in order to suppress ground noise, the ground pin can be made into a center pin, but this has the disadvantage that it is difficult to use because the pins are not compatible with conventional ones.

さらに、ＳｏＰなどは、パッケージの熱抵抗が小さく、
信頼性上問題であった。Furthermore, packages such as SoP have low thermal resistance,
There was a problem with reliability.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のＩＣパッケージは、リードフレームと、ダイパ
ッドと一体となったＪ型リードフレーム（全ピングラン
ド）の２重リードフレーム（ダブルリードフレーム）構
造を有している。The IC package of the present invention has a double lead frame structure including a lead frame and a J-shaped lead frame (all pin lands) integrated with a die pad.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の斜視図、第２図は第１図の
Ａ−Ａ断面図である。FIG. 1 is a perspective view of an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA in FIG.

従来のリードフレーム２に加え、ダイパッドと一体とな
ったＪ型などのリードフレーム３との二重リードフレー
ム形状を本発明のＩＣパッケージは有している。ダイパ
ッドと一体となったリードフレームは、パッケージ本体
１（モールド部）内では、−枚の板状になっており、パ
ッケージ本体１外では、従来よりのリードフレーム形状
を有している。In addition to the conventional lead frame 2, the IC package of the present invention has a double lead frame shape including a lead frame 3 such as a J-shape integrated with a die pad. The lead frame integrated with the die pad has a plate shape inside the package body 1 (mold part), and has a conventional lead frame shape outside the package body 1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＩＣパッケージのリード
フレームを二重にしたダブルリードフレーム構造にし、
その１組をダイパッドと一体化するとともに全ピンをグ
ランドピンとすることにより次の様な効果がある。As explained above, the present invention has a double lead frame structure in which the lead frame of an IC package is doubled.
By integrating one set with the die pad and making all the pins ground pins, the following effects can be obtained.

即ち、従来のＩＣパッケージであると、グランドピンが
一本しかなり、シかもコーナーピンであった為、インダ
クタンスが大きくグランドノイズも大きいものになって
いたが、全ピングランドピンのリードフレームを一組設
けると、インダクタンスが小さくなりグランドノイズも
低減できる効果がある。In other words, in conventional IC packages, there was only one ground pin, and it was often a corner pin, resulting in large inductance and large ground noise. Providing a pair has the effect of reducing inductance and ground noise.

又、信号線用のリードフレームを従来通りの規格に合せ
ておき、全ピングランドピンのリードフレームをＪ型の
ものにしておくと、このグランドピン用のパッドがなく
ても従来通りの場所にアッセイできる。Also, if the lead frame for the signal line is made to the same standard as before, and the lead frame for all the pin ground pins is J-shaped, even if there is no pad for this ground pin, it can be placed in the same place as before. Can be assayed.

さらに、ダイパッドと一体をなし、リードフレームがす
べてグランドピンになっているので、パッケージの放熱
板にもなっており、熱抵抗を下げることができる効果が
ある。Furthermore, since it is integrated with the die pad and all of the lead frames are ground pins, it also serves as a heat sink for the package, which has the effect of lowering thermal resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の斜視図、第２図は第１図の
Ａ−Ａ断面図である。 １・・・パッケージ本体、２・・・リードフレーム、３
・・・リードフレーム、４・・・ボンディング線、５・
・・ＩＣチップ。FIG. 1 is a perspective view of an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1...Package body, 2...Lead frame, 3
... Lead frame, 4... Bonding wire, 5.
...IC chip.

Claims (1)

【特許請求の範囲】[Claims] 　通常のリードフレーム（ＤＩＰ，ＳＯＰｅｔｃ）と、
グランドとされたダイパッド（フラグ）部と一体となっ
たＪ−Ｂｅｎｄリードフレームの二重のリードフレーム
を有することを特徴とするＩＣパッケージ。Normal lead frame (DIP, SOPetc),
An IC package characterized by having a double lead frame of a J-Bend lead frame that is integrated with a die pad (flag) section that is grounded.
JP16013690A 1990-06-19 1990-06-19 Ic package Pending JPH0449646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16013690A JPH0449646A (en) 1990-06-19 1990-06-19 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16013690A JPH0449646A (en) 1990-06-19 1990-06-19 Ic package

Publications (1)

Publication Number Publication Date
JPH0449646A true JPH0449646A (en) 1992-02-19

Family

ID=15708654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16013690A Pending JPH0449646A (en) 1990-06-19 1990-06-19 Ic package

Country Status (1)

Country Link
JP (1) JPH0449646A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2724054A1 (en) * 1994-06-09 1996-03-01 Samsung Electronics Co Ltd SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE
WO2002085082A1 (en) * 2001-04-09 2002-10-24 Matsushita Electric Industrial Co., Ltd. Surface mounting type electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2724054A1 (en) * 1994-06-09 1996-03-01 Samsung Electronics Co Ltd SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE
WO2002085082A1 (en) * 2001-04-09 2002-10-24 Matsushita Electric Industrial Co., Ltd. Surface mounting type electronic component
US6828667B2 (en) 2001-04-09 2004-12-07 Matsushita Electric Industrial Co., Ltd. Surface mounting type electronic component

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