JPH0449316B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal measuring device used for adjusting a video tape recorder.

Conventional configurations and their problems In recent years, video tape recorders (VCRs) have become extremely popular, and in order to further develop them in the future, it is expected that manufacturing costs will be reduced by improving mass production.
In particular, there is a strong demand for automation of adjustment processes and inspection processes that mainly rely on manual labor.

In general, the VTR's luminance signal recording system uses an emphasis circuit that emphasizes the high-frequency characteristics of the luminance signal during recording to improve the signal-to-noise ratio during playback. White clip/dark clip circuit that suppresses the tip level of the spike to a predetermined level.
A clamp circuit clamps the sync chip level of the luminance signal input to the lower FM modulator to a constant potential in order to correspond to the carrier frequency of the FM signal, and amplifies the FM signal modulated by the FM modulator. It consists of a recording amplifier that supplies recording current to the video head. In such a configuration, the above-mentioned white clip/dark clip circuit generally sets the sync chip level to the white peak level at 100% in order to prevent variable adjustment due to the emphasized luminance signal, and adjusts the rising and falling spike levels. It has a function to adjust (white clip, dark clip level adjustment) to a predetermined ratio.

Conventionally, in adjusting the white clip and dark clip levels described above, the luminance signal to be adjusted is monitored with an oscilloscope, the value from the sync chip to the white peak level is measured from the waveform on the oscilloscope, and the value is A method is adopted in which the white clip level and dark clip level are adjusted so that the value from the sync chip level or white peak level to the clip level becomes a predetermined value.

However, as mentioned above, while monitoring the waveform on the oscilloscope, the white clip level
The method of adjusting the dark clip level hinders the automation of the adjustment process and makes it difficult to obtain a high degree of adjustment accuracy.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a video signal measuring device that can automate the adjustment process or inspection process in the brightness signal recording system of a VTR.

Structure of the Invention The video signal measuring device of the present invention is an S/
The input signal state of the H circuit, the sample pulse generation circuit that synchronizes with the input video signal and supplies sample pulses to the S/H circuit during the period when the input video signal is at the white peak level, the emphasis circuit, the clamp circuit, etc. A mode control means for controlling the S/H circuit to sequentially output a clamp potential, a white peak potential, and each clip potential of the white clip/dark clip circuit, and a voltmeter for measuring the potential of the output signal of the S/H circuit. configured, which allows the VTR
The white peak level, sync chip level, white clip level, and dark clip level of the video signal in the recording system can be measured as DC potentials, and as a result, automation of the white clip level and dark clip level adjustment process and inspection process is possible. This is what makes it possible.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram in one embodiment of the present invention, and FIGS. 2a to 2d are waveform diagrams of main parts in FIG. 1. In Fig. 1, reference numeral 1 denotes a clamp circuit, in which a video signal is input from one end and a clamp capacitor 1a outputs a video signal with the sync chip level clamped from the other end, and the collector terminal is the output terminal of the clamp capacitor 1a. The emitter terminal is connected to the other terminal of the reference voltage source 1d whose end is grounded, and the base terminal is connected to the resistor 1d.
It consists of a PNP transistor 1d connected to one terminal of the transistor b. Reference numeral 2 denotes an emphasis circuit, which includes OP-AMP2a to which the output of the clamp circuit 1 is normally input to the positive phase input side, a resistor 2b connected to the output terminal of OP-AMP2a, and a resistor 2b connected to the negative phase input terminal, and OP-
A resistor 2 whose one end is connected to the negative phase input terminal of AMP2a and whose other end is grounded via a capacitor 2d.
It is composed of c. 3 is white clip
Dark clip circuit, NPN transistor 3c,
Consists of a PNP transistor 3b, resistors 3a, 3d, and variable resistors 3e, 3f with tap terminals,
PNP transistor 3d and NPN transistor 3c
The emitter terminals of each of the emitter terminals are connected in common to the output terminal of the OP AMP 2a, which is the output terminal of the emphasis circuit 2. The resistor 3a is connected between the collector terminal of the PNP transistor 3b and ground, and the resistor 3d is connected between the collector terminal of the NPN transistor 3c and the power supply terminal _Vcc . The tap terminal of the variable resistor 3e is connected to the base terminal of the PNP transistor 3b, and one of the other two terminals other than the tap terminal is grounded and the other is connected to the power supply terminal _Vcc . The tap terminal of the variable resistor 3f is connected to the base terminal of the NPN transistor 3c, and the other two terminals are connected to the power supply terminal _Vcc and the ground point, respectively, similarly to the variable resistor 3e. Note that a clamp circuit 1, an emphasis circuit 2, a white clip/dark clip circuit 3, and a video circuit are configured. Reference numeral 5 denotes a sample pulse generating means, which includes a V synchronization separation circuit 5a that detects a vertical synchronization signal from a video signal, and delays the output pulse of the V synchronization separation circuit 5a to keep the video signal low for at least the vertical blanking period.
A pulse delay circuit 5b that outputs Level, an H synchronization separation circuit 5c that detects a horizontal synchronization signal from a video signal, a pulse delay circuit 5d that delays the output pulse of the H synchronization separation circuit for a certain period of time, and pulse delay circuits 5b, 5d. AND gate 5e that ANDs the output of
It is composed of Reference numeral 4 denotes a sample/hold (S/H) circuit to which the output of the emphasis circuit 2 is input, and samples the input signal using the output pulse of the AND gate circuit 5e. A voltmeter 7 measures the output voltage of the S/H circuit. 6
is a mode control means, and switches 6a, 6
It is composed of b, 6c, 6d, and 6e.

The operation of the video signal measuring device according to this embodiment configured as described above will be described below. First, terminal A is connected to _a video signal as _shown in FIG. signal) is being input. This video signal is input to the H synchronization separation circuit 5c and output as a horizontal synchronization signal as shown in FIG. 2b. This horizontal synchronizing signal is input to the pulse delay circuit 5d, and the T ₂ of the video signal is
is delayed by a period T ₃ such that the pulse occurs during a period T 3 to obtain the signal shown in FIG. 2c. The video signal is also input to a V synchronization separation circuit 5a, which outputs a vertical synchronization signal. This vertical synchronizing signal is input to the pulse delay circuit 5b, which outputs a pulse that is at a low level during a period that sufficiently covers the vertical blanking period of the video signal and is at a high level during other periods. Furthermore, the output pulses of each of the pulse delay circuits 5b and 5d are input to an AND gate 5e, and the output thereof is supplied as a sample pulse to the S/H circuit 4.

In white peak level measurement mode,
Switches 6a and 6b are in the ON state, switch 6c,
6d is in the OFF state. That is, the video signal is supplied to the capacitor 1a via the switch 6a,
A clamp pulse that turns on the transistor 1c during the sync chip level period of the video signal is supplied from the terminal B to the input side terminal of the resistor 1b via the switch 6b. In other words, the video signal is set to the sync chip level by the clamp circuit at the potential of the reference voltage source 1d.
It is clamped to _ECL and supplied to the emphasis circuit 2. In the emphasis circuit 2, if the values of the resistors 2b and 2c are R _f and R _g (Ω), and the capacitor 2d is C(F), then {1+(R _f +R _g )CS}/(1+R _g CS) S: Laplacian It can be expressed as a transfer function where the DC gain is 1 and the high frequency gain is (1+R _f /R _g )
As shown in FIG. 2d, the output of the emphasis circuit is a signal in which a positive spike voltage occurs when the input signal rises, and a negative spike voltage occurs when the input signal falls. Figure 2 d
In the signal, the potential E _SL is the clamp potential at the sink chip level, E _WL is the white peak potential, E _WC is the white clip potential clipped by the PNP transistor 3b, and E _DC is the dark clip potential clipped by the NPN transistor 3c. Indicates potential. This signal is input to the S/H circuit 4, and the white peak level of the signal is detected by the above-mentioned sample pulse generating means output pulse (pulse for sampling the white peak level of the signal shown in FIG. 2d except for the vertical blanking period). The level is sampled and the E _WL converted to direct current is measured by a voltmeter 7.

In the clamp potential measurement mode, switches 6a, 6b, and 6d are turned off, and switch 6c is turned on.
voltage _Vcc is applied to the resistor 1b via the switch 6c, and the NPN transistor 1c is turned on.
The clamp potential _ECL of the reference voltage source 1d is always input to the S/H circuit 4 via the emphasis circuit 2, sampled and held by the S/H circuit 4, and measured by the voltmeter 7.

In white clip potential measurement mode,
Switches 6a, 6b, and 6c are turned OFF, and depending on the state of switch 6c OFF, NPN transistor 1c
Turn off. Then turn on switch 6d,
By closing the switch 6e to the _Vcc side, a DC potential _Vcc higher than E _WL is applied to the clamp circuit 2, and as a result, E _WL corresponding to the base potential of the PNP transistor 3b [E _WL = (base of PNP transistor 3b Potential)+(forward base-emitter voltage of PNP transistor 3b)] is input to the S/H circuit 4 and measured by the voltmeter 7.

In dark clip level measurement mode,
Switches 6a, 6b, 6c are OFF, switch 6
d is turned ON, the switch 6e is closed to the ground side, and as a result, the NPN transistor 3c is in the operating state, and E _DC [E _DC = (NPN transistor 3c) corresponding to the base potential of the NPN transistor 3c
base potential) - (forward voltage between the base and emitter of the NPN transistor 3c)] is the S/H circuit 4
and is measured by the voltmeter 7.

As described above, according to this embodiment, the clamp potential, white peak potential, white clip potential, and dark clip potential of a video signal in the recording system of a video circuit can be detected as a DC voltage. In addition, the white clip level d and the dark clip level β can be obtained as d = ( _EWL - E _CL ) / (E _WL - E _CL ) β = (E _WL - E _DC ) / (E _WL - E _CL ), respectively. I can do it. In other words, as is clear from the above equation, by detecting E _WL , E _CL , E _WC , and E _DC using the same sample and hold circuit, the white clip level and dark clip level can be obtained without being affected by the sample and hold circuit. be able to.

Effects of the Invention As is clear from the above explanation, according to the present invention, the clamp potential, white peak potential, dark clip potential, and white clip potential of a video signal to be recorded can be measured as DC potentials, that is, as digital signals. This makes it possible to easily adjust the white clip and dark clip levels and automate the inspection process, which was difficult in the past.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram in one embodiment of the present invention, and FIGS. 2a to 2d are waveform diagrams of main parts in FIG. 1. DESCRIPTION OF SYMBOLS 1... Clamp circuit, 2... Emphasis circuit, 3... White clip/dark clip circuit, 4... S/H circuit, 5... Sample pulse generation means, 6... Mode control means, 7...
voltmeter.

Claims (1)

[Claims] 1 An emphasis circuit that emphasizes the high-frequency characteristics of the input video signal; a white clip/dark clip circuit that clips the tip level of the spikes that are emphasized by the emphasis circuit and that occur at the rising and falling portions of the video signal; an S/H circuit that is used to adjust a white clip level and a dark clip level of a video circuit and that samples and holds an output signal of the video circuit, which is composed of a clamp circuit that clamps a sync chip level to a predetermined clamp potential; Controls input signal states of a sample pulse generation circuit that synchronizes with the input video signal and supplies sample pulses to the S/H circuit, the emphasis circuit, and the clamp circuit during a period when the input video signal is at a white peak level. A mode control means for the S/H circuit to sequentially output a clamp potential, a white peak potential, and each clip potential of the white clip/dark clip circuit, and a voltmeter for measuring the potential of the output signal of the S/H circuit. A video signal measuring device comprising: