KR900008447Y1 - Correction circuit for reproducing control signal - Google Patents

Abstract

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Description

Phase delay compensation circuit of playback control signal

1 is a conventional video signal recording and reproducing circuit diagram.

2 is a waveform diagram according to FIG.

3 is a phase delay compensation circuit diagram of a reproduction control signal according to the present invention.

4 shows a waveform according to FIG.

* Explanation of symbols for main parts of the drawings

1: control head 2: regenerative amplifier

3: Schmitt trigger amplifier 4: Capstan phase detector

5: tracking monomultivibrator 6: capstan reference signal generator

7 Capstan phase off output stage 8 Gate pulse generator

9: sampling and holding circuit S1: switch

Q1, Q2: transistor C1: capacitor

IC1: Buffer Amplifier IC2: Comparator

The present invention relates to an image signal recording and reproducing apparatus, and in particular, delays the phase of a reproduction control signal to reduce the phase error of the capstan motor phase control, and also provides a tracking free for optimal tracking of the track recorded in the image head during reproduction. The present invention relates to a phase delay compensation circuit of a reproduction control signal that minimizes errors when setting a setting value.

In the conventional video signal recording / reproducing circuit, as shown in FIG. 1, the recording control signal REL CTL detected from the recording / reproducing control head 1 passes through the reproducing amplifier 2 to the input terminal of the Schmitt trigger amplifier 3. The tracking monomultivibrator 5 connected to the capstan phase error output stage 7 via a capstan phase detector 4, and to a capstan reference signal generator 6 connected to the capstan phase amplifier 4. As a configuration connected to the phase detector 4, the operation state thereof will be described according to the circuit diagram of FIG. 1 and the waveform diagram of FIG. 2. When the video signal is recorded, the control signal REC CTL is taped through the control head 1 during recording. The recorded signal is reproduced through the control head 1 at the time of reproducing. At this time, the signal is reproduced through the reproducing amplifier 2 since the signal [mv] is a weak signal as shown in FIG. when amplified as b) In the Schmitt trigger amplifier is standing sikimyeo Schmitt trigger amplifier 3 (3) generates a square wave, such as (c) is thereby applied to the capstan phase detector (4). In the capstan phase detector 4, a reference signal from the capstan reference signal generator 6 is delayed for a predetermined time by the tracking monomultivibrator 5, and a signal applied from the Schmitt trigger amplifier 3 is applied. In comparison, an error signal is output to the capstan phase error output stage 7 to be used as a phase control signal of the capstan motor control.

However, since the signal detected from the control head 1, i.e., (a) of FIG. 2 is very weak, it is amplified by the regenerative amplifier 2 and applied to the Schmitt trigger amplifier 3, where the original control head 1 The difference between the detected signal and the square wave output through the Schmitt trigger amplifier (3) is a new time difference (T) as shown in (d) and (e) of FIG. 2 to obtain accurate capstan phase control and tracking values. There was this.

In order to solve the above problems, the present invention minimizes the phase delay of the original signal using the Schmitt trigger signal, and connects the gate pulse generator and the sampling and hold circuit to generate the maximum value of the control signal. This configuration is described below with reference to FIG. 3.

The regenerative amplifier 2 to which the control head 1 is connected is connected to the base of the transistor grounded transistor Q1 through the Schmitt trigger amplifier 3 and to the terminal C of the gate pulse generator 8 at the same time. The emitter of the transistor Q1 is connected to the capstan phase error output terminal 7 through the capstan phase detector 4, and the tracking mono multivibrator 5 to which the capstan reference signal generator 6 is connected is connected to the capster phase detector 4. Is connected to the buffer amplifier IC1 fleece stage and the comparator IC2 minus stage of the sampling and holding circuit 9, and the negative end of the buffer amplifier IC1 is connected to its output stage. Is connected to the plus end of the comparator IC2 via a switch S1 connected to the sampling signal output terminal F of the gate pulse generator 8, and the plus end of the comparator IC2 is connected to the capacitor C1. Ground connection The discharge control signal terminal G of the pulse generator 8 is connected to the collector of the transistor Q1 connected to the base, and the output terminal of the comparator IC2 is connected to the emitter of the transistor Q1 and at the same time the gate pulse generator With the configuration connected to the terminal H of (8), the operation state and the effect thereof will be described as the circuit diagram of FIG. 3 and the waveform diagram of FIG.

In FIG. 3, the same number [mv] of control signals REC CTL as in FIG. 4 (a) in which the control head 1 is reproduced is amplified by the reproducing amplifier 2 so that a signal as in FIG. Waveform (c) of FIG. 4 is output from the output terminal of the Schmitt trigger amplifier 3, and the output signal of the reproducing amplifier 2 as shown in FIG. The signal applied to the negative stage of the buffer amplifier IC1 plus the comparator IC2 and applied to the buffer amplifier IC1 is configured to control sampling by the signal output from the gate pulse generator 8.

That is, the sampling control signal generates pulses at the time interval T by generating pulses at the standing time of the Schmitt trigger amplifier 3 as shown in (f) of FIG. It can be set to a proper value.

When the control signal is generated from the sampling signal output terminal F of the gate pulse generator 8 and applied to the switch S1, the switch S1 repeats ON / OFF, but the switch S1 The output of the buffer amplifier IC1 is charged to the condenser C1 through the switch S1, the switch S1 is closed and the switch S1 of the gate pulse generator 8 is closed. The transistor Q2 is turned on by the pulse shown in FIG. 4 (g) output from the discharge control signal terminal G to discharge the charging voltage of the capacitor C1.

At this time, the comparator IC2 compares the charging potential of the capacitor C1 with the output signal b of the regenerative amplifier 2 applied to the negative terminal, that is, a signal as shown in FIG. In Fig. 4 (d) and (e), the standing time T of the Schmitt trigger signal is increased toward the peak value of the regeneration control signal, so that the sampling signal and the terminal generated at the terminal F of the gate pulse generator 8 When the signal magnitude applied to the positive terminal of the comparator IC2 increases due to the discharge control signal generated in (g) compared to the signal magnitude of the negative terminal, the output of the comparator IC2 is low until the maximum value of the control signal. The level is maintained and applied to the capstan phase detector 4.

According to the above, the signal is decreased from the state where the output of the regenerative amplifier 2 reaches the maximum value, and the positive terminal of the comparator IC2 is charged to the capacitor C1 by the terminal F signal of the gate pulse generator 8. Since the voltage is in the maximum state, the signal of the high state is output to the comparator (IC2) output terminal as shown in FIG.

That is, since the output signal of the comparator IC2 is applied to the capstan phase detector 4 at the position of the original signal, the time difference T is minimized.

Here, the transistor Q1 controlling the output of the comparator IC2 is turned on when the signal C passing through the Schmitt-trigger amplifier 3 is low, thereby changing the output of the comparator IC2 to a low state, so that it is the same as the original signal. When the output of the comparator IC2 falls to a low state, a signal is output from the terminal G of the gate pulse generator 8 to conduct the transistor Q2 to completely discharge the charging voltage of the capacitor C1. The output of (IC2) is kept at a low level so as to prepare to repeatedly perform the above-described operation to which the next control signal is applied.

Therefore, the present invention minimizes the error when setting the tracking preset value for tracing the recorded track to the optimal state by minimizing the recorded control signal with the original signal during playback as described above. It has the effect of minimizing the phase shift when controlling.

Claims (1)

In a video signal recording and reproducing circuit including a reproducing amplifier (2), a Schmitt trigger amplifier (3), and a capstan phase detector (4), the output of the reproducing amplifier (2) is provided with a buffer amplifier (IC1), a switch (S1), and It is applied to the buffer amplifier IC1 of the sampling and holding circuit 9 composed of the transistor Q2 and the capacitor C1 and simultaneously applied to the negative terminal of the comparator IC2, and the output terminal signal of the Schmitt trigger amplifier 3 is the transistor ( The sampling control circuit 9 is applied to the base C of Q1) and applied to the terminal C of the gate pulse generator 8, and outputs the sampling signal F discharge control signal G output from the gate pulse generator 8; Is applied to the switch S1 and the transistor Q2 to be sampled, and the output of the regenerative amplifier 2 and the signal sampled at the sampling hold 9 are compared by the comparator IC2 to increase the control portion T. ), The collector terminal of transistor Q1 is turned low. By compensating the phase delay of the reproduced control signal, it characterized in that the phase detector is configured to be applied to the capstan (4) if the circuit.